MODE USING SAID CURRENT SOURCE

FIELD OF THE INVENTION

The invention relates to the field of volatile memory devices and particularly to Static Random Access Memories (SRAMs).

In particular, the invention relates to an SRAM comprising a matrix arrangement of memory cells arranged in rows and columns, the cells in each column being connected to a bit line for that column, each cell comprising a plurality of transistors, the matrix of memory cells being powered by a power supply.

In addition, the invention relates to a method of putting an SRAM into a given operational mode, the SRAM comprising a matrix arrangement of memory cells arranged in rows and columns, the cells in each column being connected to a bit line for that column, each cell comprising a plurality of transistors.

BACKGROUND OF THE INVENTION

An SRAM is a type of volatile memory. This means that the memory cells of the memory retain their data as long as power to the cells remains applied, but that the data will eventually be lost when the memory cells are not powered any more. An SRAM cell typically makes use of four transistors forming a bistable latching circuit by cross-coupling two inverters, each built out of two transistors. This bistable latching circuit has two stable states: one stable state can be used to represent, and so store, a logical "0", and the other stable state can be used to represent a logical "1". In general, next to these four transistors, two other transistors are used as access transistors, which access transistors serve to control the access to the bistable latching circuitry during read or write operations from/to that circuitry. Although it is possible to build an SRAM cell out of five transistors (also called a "5T-cell") - four for the two cross-coupled inverters and one as an access transistor for access to the bistable circuitry - the most common SRAM cell is currently built out of six transistors (also called a "6T-cell"), in which two transistors serve as access transistors. The bistable latching circuitry can then, via the access transistors, be connected to a bitline and to a line on which the inverse of the bitline is present, respectively. The line on which the inverse of the bitline is present - also called the bitline's complement - is usually made available because the connection of such a bistable latching circuit to the bitline and its complement allows a higher noise margin. Other types of SRAM cells using more transistors to deal with one bit of information are also in use, but the 6T-SRAM cell generally prevails, because the use of more transistors will cost more space to build and, so, will eventually lead to a more expensive memory, as effectively less SRAM cells can be made on a single silicon wafer. The most common SRAM cell makes use of four nMOS transistors and two pMOS transistors, created in known CMOS-processes. The SRAM cells are powered by an internal or external voltage, source which can be used to apply a potential difference across the SRAM cells.

An SRAM cell can be in a read mode, a write mode or a sleep mode, also known as standby mode. In the read mode, the stored information in the cell is read by reading out the state of the bistable circuit, whereas, in the write mode, the bistable circuit assumes one of the above-mentioned two states, as dictated by the information which has to be stored. The SRAM cell is in a sleep mode when the access transistors essentially do not allow access to the bistable circuitry. Because of the nature of the SRAM cells and their use of two cross-coupled inverters, stored information will only be retained in the cells as long as there is some minimal voltage, also called minimal retention voltage, across these cells. Because of this remaining voltage difference, a leakage current will inherently flow through the SRAM cell. Of course, one would like to have as low a leakage current as possible through an SRAM cell when such a cell is put into sleep mode. Unfortunately, the minimal retention voltage strongly depends on technological parameters of the chip design, as well as on factors such as temperature. To assure that all the cells have the minimal retention voltage across the cells under all circumstances, one always has to take into account the worst possible scenario. This means that, in total, there will be a much higher leakage current flowing through the SRAM than is necessary. That one cannot reduce this leakage current during sleep mode is a major disadvantage of the SRAMs of the prior art.

A further disadvantage of the SRAMs of the prior art is the problem that often occurs when some cells of the memory are not fully functional after manufacturing. This is normally taken care of either by discarding the particular SRAM chip in question or by providing the SRAM with additional redundant cells that can replace the defective cells. If there is an excessive leakage current flowing through said defective SRAM cells, this may cause the total current flowing through the SRAM as a whole to exceed the maximum allowable DC current for that SRAM. This may lead to serious problems, such as overheating of the SRAM chip. Next to that, the current flowing through an SRAM with such defective cells will not be as low as possible whenever the memory cells of the SRAM are put into sleep mode, again leading to a higher standby power than necessary.

Yet another disadvantage of the current SRAM design is that, in modern CMOS technologies, it is becoming increasingly difficult to create SRAM cells that have enough stability during read operations and during sleep mode, and, yet, can also be written to satisfactorily. In the most commonly used 6T-cell - employing two pMOS transistors and four nMOS transistors - making the pMOS transistors strong will improve the stability during read and sleep mode, but at the same time, will generally cause a deterioration in the write performance of the cell. A possible solution to this problem, suggested in literature, is the reduction of the voltage difference across the memory cell; however, this still does not resolve the conflicting requirements associated with optimized read, sleep and write performance.

SUMMARY OF THE INVENTION

It is an object of the invention to overcome the aforementioned disadvantages.

In particular it is an object of the invention to reduce the leakage current occurring when memory cells of an SRAM are put into sleep mode.

It is another object of the invention to provide an arrangement whereby a matrix of SRAM cells is provided with just enough power to maintain the states of said cells.

Moreover it is an object of the invention to increase, for a given SRAM cell with strong pMOS transistors providing a good stability during read of the memory cell, the ability to write to such a cell, if desired.

These and other objects are achieved in a Static Random Access Memory as set forth above in the second opening paragraph, characterized in that the power supply comprises a current source.

The invention is based on the insight that, if power is supplied to a matrix arrangement of memory cells via a current source, one can force memory cells into sleep mode and at the same time limit the current to a level that is just enough to retain the content of said cells. This makes it possible to attain a very low leakage current in sleep mode. In addition, the use of a current source also makes it possible to increase the write margin of SRAM cells designed to have enough stability during read operations and during sleep mode, by supplying the cell with a limited current. A power supply based on a current source will also limit the current flowing through a defective memory cell. The skilled artisan will appreciate that, for optimal results, different scenarios will call for the use of different types / arrangements of current source. For example:

1) During sleep mode of a memory cell, the use of a constant current source is preferable, because the use of such a current source allows the leakage current during sleep mode - which by the use of a constant current source will be independent of temperature - to be as low as possible.

2) During write mode of a memory cell, the use of an adjustable or varying current source is preferable, as the ability to write data to a memory cell will be dependent on the (varying) actual difference between the effective impedance of two current paths, as will be explained later below.

In one embodiment of the invention, separate current sources are used for separate slices of said matrix arrangement, in which a separate slice of the matrix arrangement comprises one or more of said columns (of memory cells). In this embodiment, there are many current sources, each current source supplying a separate slice of the matrix arrangement, instead of one current source for the whole matrix. The total current supplied to the matrix is now split into several smaller sub-currents to each slice. This has the advantage that, if there is a defective cell present in one of the slices, an excessive leakage current through that slice will no longer be possible, unlike the case when the matrix is powered by a voltage source. Since the maximum possible current through a slice will only be a small part of the total current supplied to the whole matrix, the current leakage through a slice with a defective cell will not be of substantial influence on the other (non-defective) slices. Yet another advantage of this embodiment is that, if the matrix is provided with a global word line which is divided into a plurality of local word lines (also called a divided word line), the supply of current to separate slices of the matrix will make it possible to access selected slices and to put non-selected slices into sleep mode.

A further embodiment of an SRAM according to the present invention is characterized in that it comprises tracking means for tracking the strength of at least one designated transistor, an output of said tracking means being used to adjust at least one current source. As will be explained in more detail below in relation to Fig. 5, during write mode of an SRAM cell in which two strong pMOS transistors connected to the highest potential are used in the cross-coupled inverters concerned, the strength of a pair of nMOS transistors series-connected to one such pMOS transistor can be tracked to adjust the current source connected to that cell. This allows optimal adjustment of the (limited) current supply to that cell. The tracking of the strength of said nMOS transistors (or another designated set of transistors) may, for instance, be done using a well-known "current mirror" principle, which allows a situation whereby, during write mode of an SRAM cell, a current having a predefined relation with the current flowing through the transistors connected to one of the two pMOS transistors of the cross-coupled inverters can be obtained. The obtained current can then be used for the optimal adjustment of the current source connected to the cell involved.

The invention also provides a method of putting a Static Random Access Memory into a given operational mode, the memory comprising a matrix arrangement of memory cells arranged in rows and columns, the cells in each column being connected to a bitline for that column, each cell comprising a plurality of transistors, characterized by the steps of: providing at least one current source as power supply to the matrix of memory cells and using said current source to provide a current that forces the memory cells of said matrix into said operational mode.

In such a method, said operational mode may be a sleep mode or a write mode, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following section, the invention will be described by way of embodiments, with reference to the attached schematic drawings, in which:

Fig. 1 shows a schematic representation of a prior-art SRAM connected to a voltage supply.

Fig. 2 shows a schematic representation of an embodiment of the present invention.

Fig. 3 shows another embodiment of the invention in which the SRAM is divided into separate slices, whereby each slice comprises one or more columns of the SRAM.

Fig. 4 shows a schematic representation of an embodiment of the invention in which the SRAM is divided into separate slices and in which the SRAM comprises global and local word lines.

Fig. 5 shows a more detailed embodiment of the present invention in the case of a memory cell employing a 6T architecture. In the Figures, like reference numerals are used to indicate like features.

DETAILED DESCRIPTION OF EMBODIMENTS

Background art

With reference to Fig. 1, part of a prior-art SRAM 1 comprising a matrix arrangement of memory cells 7 arranged in rows and columns is schematically shown. SRAM 1 is currently frequently embodied as embedded memory, and can have any size suitable for the application in which it is used. At present, memory sizes ranging from a couple of kilobits to 32 Mbit exist. An SRAM memory cell 7 is typically comprised of a bistable latching element built out of two cross-coupled inverters 14, 14' and one or more access transistors 12, 12'. A cross-coupled inverter 14/14', in its turn, is typically built out of two transistors 10, 11 / 10', 11'. A bistable latching element (14 + 14') has two stable states in which it can reside, as long as it is connected to an appropriate power supply; it is therefore possible to store a bit of information in the latching element by forcing it into one of its stable states, representing either a logical "0" or a logical "1". The bistable latching element (14 + 14') is connected to a bitline 8 through at least one access transistor 12, whereby, in general, the access transistor 12 is connected to a write line 13, which write line 13 can be given a voltage level that determines whether the access transistor 12 connects the latching circuit to said bitline 8 or not. The write line 13 is also often called a word line, as it allows a word of, for instance, 8 bits wide in an 8-bit wide SRAM, to be written or read in a write or read cycle, respectively. Connection of the latching element to a bitline 8 is necessary so as to read out information stored in the element during read mode or to store a bit of information into the latching circuit during write mode: the information present in the memory cell 7 will be put on the bitline 8 during the read mode, whereas the information to be stored into the memory cell 7 will be put on the bitline 8 during write mode. Theoretically, it would be enough to connect the two cross coupled inverters to only one bitline 8 with only one access transistor 12; however, in practice, two access transistors 12, 12' are used, one for connecting the bistable element to the bitline 8 itself and the other for connecting the bistable element to another line 8', namely the bitline's complement line. On this latter line 8', the inverse value of the value on the bitline 8 is present. The reason for using these two access transistors 12, 12' connected to the bitline 8 and its complement 8' is that such an arrangement improves the noise margin. Therefore, the six-transistor SRAM memory cell 7 (also called "6T-cell"), with two access transistors 12, 12' and four transistors 10, 11, 10', 11 ' for the two cross-coupled inverters 14, 14', is the most currently used SRAM cell 7. Some SRAM cell designs use more than six transistors, but, as they use more space per cell to build on an integrated circuit (IC), they are generally less favored. The transistors used may, for example, be bipolar junction transistors, or Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The use of MOSFET transistors in an SRAM cell is very common today, as such transistors can be made in Complementary Metal Oxide Semiconductor (CMOS) technologies, which are at present commonly used in the semiconductor industry. Another reason why MOSFETs are often used is that they generally consume less power than transistors of the bipolar junction field type.

As the SRAM 1 is a volatile memory, it has to be connected to a power supply, even if it is in sleep mode, which is also called the standby mode; accordingly, prior- art SRAMs are connected (in all modes) to a voltage supply, which is depicted in Fig. 1 by (the voltage difference between) voltage lines V _DD and Vss- At present, SRAMs made in CMOS are powered by a voltage difference of about 0.9 to 3.3 Volt, mostly depending on the age of the employed technology: the newer the technology, the lower the voltage differences that are necessary. The SRAM memory cells 7 will draw current according to their design specifics and status. During sleep mode, the current drawn by the SRAM 1 will be the sum of the leakage currents of the memory cells 7 in the SRAM. These leakage currents depend, for example, on the employed technology, applied voltage difference, design choices, and, even more importantly, on temperature. This temperature dependence, in particular, is a great drawback of the SRAM 1 presently used, because said leakage currents depend exponentially on the temperature. The SRAM design of the prior art also suffers from the drawback that, if there is a defective memory cell 7 present in the SRAM's array, the current flowing through that defective memory cell may be excessive; as a result, a total current flowing through the (whole) SRAM array 1 may exceed an allowable maximum, leading to problems like overheating of the SRAM.

Embodiment 1

Fig. 2 depicts an embodiment of the present invention. Again, the SRAM 1 is present, but now electrical power is supplied to the SRAM array via a current source 2. It is this use of a current source 2 as a power supply to the SRAM array 1 that allows the current drawn by the memory cells 7 of the array to be controlled. The skilled artisan will appreciate that, for example: The current source 2 can be a constant current source supplying a fixed current, but can also be a variable current source supplying a variable current - allowing one to compensate for process, voltage and temperature influences, for example.

The current source 2 can be designed to track the strength of transistors employed in a bitline write circuit. One way to achieve such tracking is through the use of the so-called "current mirror" principle. This principle can be used to copy the current flowing through the bitline 8, and to use this copied current to adjust the current source 2. Another possibility is to use the copied current as current source 2 itself.

A common basic circuit to perform the "current mirror" principle in CMOS is the coupling of two pMOS transistors in such a way that they have a common gate, which common gate is connected to the drain of the pMOS transistor through which the current to be copied flows. The copied current will then flow through the other pMOS transistor. Depending on the layout of the employed transistors (i.e. the width/length ratios, etc.), the current flowing through a bitline 8 can be copied in this manner; this copied current can then, in turn, be used to adjust a current source 2 (or used as a current source 2 by itself). It is, of course, also possible to obtain a "copied" current with a strength other than exactly the same strength as the current flowing through the bitline 8, by choosing another layout of the employed transistors; the layout could, for instance, be chosen such that the "copied" current is half the current flowing through the bitline 8.

Use of a current source 2 in accordance with the invention has the advantage that it now becomes possible to force memory cells 7 into sleep mode while limiting the current to the nMOS sub-threshold level, i.e. the sub-threshold current which is generally the main component of the current during sleep mode of a memory cell. At the same time, the power dissipated in sleep mode can be kept as low as possible - in principle, just enough to maintain the states of the bistable latching circuits (14 + 14') of the memory cells 7. The current source 2 automatically creates the right amount of voltage across the array of memory cells to maintain them in sleep mode. Control of the current also makes it possible to place memory cells 7 in write mode in an optimized manner, as will be further elucidated hereunder with respect to Fig. 5.

It should be noted that, in read mode of the SRAM, there is hardly any current drawn by the memory cells 7. Consequently, in this mode, it is of relatively little importance what current source 2 is employed as a power supply: in addition to the relatively strong current (typically in the micro-Ampere range) associated with putting memory cells into write mode, a weaker current (typically in the nano-Ampere range) - like the current associated with keeping memory cells in sleep mode - may also be sufficient. It is also possible to apply a conventional potential difference across the array of memory cells during read mode. This could, for instance, be achieved by putting a switch (not depicted) in parallel with the current source 2. In read mode, this switch could be closed, thereby short-circuiting the current source 2 and shunting a conventional potential difference (e.g. V _DD -V _SS ) across the memory array; in this way, the highest possible voltage is supplied to the memory cell and the maximum stability for reading is achieved. On the other hand, in sleep or write mode, said switch could be opened, so that power supply to the memory will occur via the current source 2 according to the invention.

Embodiment 2

Fig. 3 shows another embodiment of the present invention in which the SRAM array is divided into slices 4, 4', 4", and in which, for every slice, the power supply comprises a separate current source 3, 3', 3". The slices 4, 4', 4" each comprise one or more columns of the matrix arrangement of memory cells of the SRAM. A useful size of such a slice would be a size related to the architecture of the so-called Y-decode/sense amplifiers (i.e. the decode/sense amplifiers that are normally connected to one or more pairs of bitlines to deal with the signals on those bitlines). As, at present, such a bit line decode/sense amplifier serves, for example, 4 or 8 columns, an obvious choice of the size of a slice would be this size, of, for example, 4 or 8 columns, which is also the commonly used size of a section of SRAM reserved for redundancy (to replace faulty cells).

Again, these current sources 3, 3', 3" could be any suitable current source, including an adjustable current source, but current sources capable of supplying a constant current independent of process, voltage and temperature variations may be preferable. The separate current sources 3, 3', 3" - of which the individual currents add up to the current supplied to the SRAM as a whole (see Fig. 2, in which only one current source is used) - may share the same control circuitry. In this embodiment, if there is a defective cell present in one slice - which, in a prior-art SRAM, would tend to cause an excessive current through that cell (and slice), from the point of highest potential to the point of lowest potential - the current will now, instead, be limited by the current source for that particular slice. As a result, the current flowing through a slice with such a defective cell will be no different than the current flowing through a non-defective cell. Embodiment 3

Yet a further embodiment of the present invention is described in relation to Fig. 4. Fig. 4 shows two slices 4, 4' of an SRAM, in which, in slice 4', a memory cell 7 is depicted. Memory cell 7 is connected to a bit line 8 and to its complement 8', as well as to a local word line 6. The Figure also shows a global word line 5 and a signal line 9, often called a block select line, which makes the selection of a slice of the SRAM possible. This global/local word line structure, also known as divided word line structure, makes it possible to select a slice of the SRAM for read and/or write operations and put the other slices into sleep mode. Of course, this is advantageous for power reduction in the SRAM as a whole. The term "global word line" is also often used to indicate the situation as perceived from outside the SRAM (slices), while, internally, such a global word line may be divided into multiple local word lines. An example of a memory with such a structure is a 1 Mbit memory with 1024 columns and 1024 global word lines, each divided into 32 local word lines.

Embodiment 4

Fig. 5 shows in more detail a 6T SRAM memory cell 7 according to the present invention. Use is made of two pMOS transistors 10, 10' as pull-up transistors and two nMOS transistors 11, 11' as pull-down transistors. Also shown are the bitline 8 and its complement 8', as well as a (local or global) word line 13. According to the invention, the memory cell is powered by a current source 2. The depicted 6T-cell is written by pulling down the internal "high" mode of one of the inverters 14, 14'. During write mode, the pulldown transistors 11 and 11 ' hardly play a role; in a memory cell according to the prior art, it is the fighting of a strong pMOS pull-up transistor 10 against two other nMOS pull-down transistors, connected in series with that particular pMOS pull-up transistor 10, that matters (said series-connected pull-down transistors being the access transistor 12 and a pull-down transistor in an associated (non-depicted) write buffer). In a worst case scenario, said series- connected nMOS pull-down transistors are too weak, and the pMOS pull-up transistor 10 too strong, to pull down the internal "high" mode of the inverter involved, so that writing of the memory cell fails. Therefore the design of such memory cells has to be such that under all conditions said series-connected nMOS pull-down transistors are stronger than the pMOS pull-up transistor 10. Care should, for instance, also be taken with respect to the statistical spread of the employed nMOS and pMOS transistors.

A power supply comprising a current source 2 according to the present invention makes it continually possible for the internal "high" mode of an inverter to be pulled down, as long as the employed current supply is weaker than said series-connected nMOS pull-down transistors. By setting a maximum on the current supplied by the pMOS transistor 10, it becomes possible to write to memory cells that would suffer from write-fail when using a power supply comprising a conventional voltage source, as in the prior art.

As is easily understood, there are only two requirements for the current source 2 during write mode: first, the current has to be smaller than the current supplied by the so- called column write buffer (i.e. a circuit that forces the data to be written on the pair of bit lines 8, 8' during a write cycle) and larger than the expected leakage current of the column involved. The net result of this approach is, that for a given memory cell 7, the write margin increases without compromising the read margin.

Although preferred embodiments of the memory and methods of the present invention have been illustrated in the accompanying drawings and described in the foregoing detailed description, it should be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit of the invention as set forth and defined by the following claims. The skilled person will, for example, understand that the position of the current source or current sources is not limited to the depiction in the drawings; instead of placing a current source between the line with the highest potential and the SRAM(-slice), alternatives like placing the current source between the SRAM(-slice) and the line with the lowest potential are also possible. Also, the division of the SRAM into slices with global and local word lines is not obligatory: the skilled artisan will understand that the principles described could easily be used for other SRAM matrix arrangements, including a matrix arrangement in which the slices do not have the same size and/or current supplies. In addition, the tracking means as described are not limited to circuits performing the "current - mirror" principle, let alone that only the described basic circuit can be used; said basic circuit can be modified in many different ways well within the grasp of the skilled artisan. Moreover, the use of a shunting switch to choose between the operation of the SRAM in read mode and in write or sleep mode is not confined to the use of a switch for the SRAM memory as a whole; such a switch could also be used for separate current sources connected to different slices of an SRAM. In addition, the invention is also not limited to the 6T-cell as described in relation to Fig. 5, which description only served an elucidatory purpose.