Title:
STIMULUS INFORMATION COMPILING METHOD AND SYSTEM FOR TESTS
Document Type and Number:
WIPO Patent Application WO/2017/024845
Kind Code:
A1
Abstract:
A stimulus information compiling method for tests is disclosed comprising the following steps: selecting and using stimulus information which follows a statistics-normal distribution and is analyzed and measured by validity to form a stimulus information database (Q); reasonably setting at least one stimulus information to be a test including at least one test sequence, for a subject to make a selection according to his or her personal interests; comparing a test score of the subject with that of a valid sample person in a normal distribution model, thereby confirming the distribution of the subject in each cognitive dimension. A test score of the subject is compared with that of a valid sample person in a normal distribution model, thereby confirming the test result of the subject.
Inventors:
WO JIANZHONG (CN)
LIU YANG (CN)
LIU YANG (CN)
Application Number:
PCT/CN2016/082805
Publication Date:
February 16, 2017
Filing Date:
May 20, 2016
Export Citation:
Assignee:
BEIJING HUANDU INST OF WISDOM-MIND TECH LTD (CN)
International Classes:
G06F17/30; A61B5/16; G06F19/28
Foreign References:
CN102293656A | 2011-12-28 | |||
CN105105772A | 2015-12-02 | |||
CN105025036A | 2015-11-04 | |||
CN105011952A | 2015-11-04 | |||
CN104992080A | 2015-10-21 | |||
CN105139317A | 2015-12-09 | |||
CN103561651A | 2014-02-05 | |||
US20050089206A1 | 2005-04-28 | |||
CN103873854A | 2014-06-18 |
Attorney, Agent or Firm:
HAIHONG JIACHENG INTELLECTUAL PROPERTY & PARTNERS (CN)
Download PDF:
Previous Patent: BOLT CONNECTION STRUCTURE BETWEEN COLUMN AND BEAM IN ALUMINUM ALLOY HOUSE
Next Patent: WAFER LEVEL CHIP PACKAGING METHOD
Next Patent: WAFER LEVEL CHIP PACKAGING METHOD