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Patent Searching and Data


Title:
STORAGE DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/130144
Kind Code:
A1
Abstract:
Provided is a novel storage device. The storage device has a plurality of memory cells arranged in a matrix. Each memory cell has a transistor and a capacitance element. Each transistor has a first gate and a second gate which have regions that overlap each other through a semiconductor layer. The storage device has functions for operating in a "write mode", a "read mode", a "refresh mode" and an "NV mode". In the "refresh mode", data retained in the memory cells is read and then rewritten to said memory cells over a first amount of time. In the "NV mode", data stored in the memory cells is read, then rewritten to said memory cells over a second amount of time, and then a potential is supplied to the second gates to turn off the transistors. Operating in the "NV mode" allows data to be stored for a long time even if the power supply to the memory cells is stopped. Multi-value data can be stored in the memory cells.

Inventors:
ONUKI, Tatsuya (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
MATSUZAKI, Takanori (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
KATO, Kiyoshi (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
YAMAZAKI, Shunpei (398, Hase, Atsugi-sh, Kanagawa 36, 〒2430036, JP)
Application Number:
IB2018/059984
Publication Date:
July 04, 2019
Filing Date:
December 13, 2018
Export Citation:
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Assignee:
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. (398 Hase, Atsugi-shi Kanagawa, 36, 〒2430036, JP)
International Classes:
G11C14/00; G11C11/405; H01L21/8242; H01L27/108; H01L29/786
Foreign References:
JP2017174489A2017-09-28
JP2017143255A2017-08-17
JP2017108397A2017-06-15
JP2016139452A2016-08-04
JP2018056558A2018-04-05
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