BACKGROUND

[0001] Quantization is the process of mapping a set of continuous input values onto a discrete set, such as rounding values to some unit of precision. In digital signal processing, the difference between the actual analog value and the quantized digital values is called a quantization error. Similarly, when storing a resistance value on a memristor, the difference between a targeted analog value (i.e., the ideal and desired result of writing an analog value to memristor) and the actually obtained analog value (i.e. , the imperfect result of writing an analog value to a memristor) is called writing error.

BRI EF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings illustrate various examples of the principles described herein and are a part of the specification. The illustrated examples are given merely for illustration, and do not limit the scope of the claims.

[0003] Fig. 1 is a block diagram of a memory device according to one example of the principles described herein.

[0004] Fig. 2 is a circuit diagram of a number of serial 1T1 R memory cells electrically coupled in parallel to form an array according to one example of the principles described herein.

[0005] Fig. 3 is a circuit diagram of a number of serial 1T1 R memory cells electrically coupled in parallel with the array electrically coupled to a chain shift register according to one example of the principles described herein. [0006] Fig. 4 is a number of circuit diagrams demonstrating the propagation of a signal through a parallel array of serial 1T1 R memory cells according to one example of the principles described herein.

[0007] Fig. 5 is a circuit diagram of a number of parallel 1T1 R memory cells electrically coupled in series to form an array according to one example of the principles described herein.

[0008] Fig. 6 is a circuit diagram of a number of parallel 1T1 R memory cells electrically coupled in series with the array according to another example of the principles described herein

[0009] Fig. 7 is a number of circuit diagrams demonstrating the propagation of a signal through a serial array of parallel 1T1 R cells according to one example of the principles described herein.

[0010] Fig. 8 is a circuit diagram to convert a stream of discrete analog resistance values into a voltage waveform according to one example of the principles described herein.

[0011] Fig. 9 is a flowchart showing a method of storing a discrete analog sequence according to one example of the principles described herein.

[0012] Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

DETAILED DESCRIPTION

[0013] As described above, writing an analog value into a memristor is an imperfect process. When storing an analog signal stream into an array of memristors, the resulting corrupted analog values can be thought of as the sum of two signal streams, the ideal signal stream plus an error signal stream. Each error can be measured at the time of its creation, and then taken into account as subsequent values in the analog stream are written. Oversampling (to create bandwidth above that of the ideal signal stream) and noise shaping (to push the error signal stream's energy into the portion of the spectrum created by oversampling) may be used to attenuate the effect of the error signal stream on the ideal signal stream. The ideal signal stream can then later be recovered from the stored corrupted stream with a filtering operation. In the case of standard noise shaping by differentiation, the recovery filter would be a low-pass filter. Low-pass filtering of a discrete signal may be accomplished by the addition of neighboring samples in the signal stream

[0014] The present specification describes the use of memristive devices to store a discrete-time analog signal using the properties of the memristors to shape the noise and restore the analog sequence of the signal by shifting a window of cell selection signal sequentially along a length of a string of memristive devices.

[0015] The specification further describes a method of storing a discrete analog sequence, including programming, in an ordered sequence, a set of targeted analog values in a number of memristive bit cells, and attenuating writing errors by noise-shaping. This method may further include restoring the discrete analog sequence by shifting a window of memristive bit cell selection signals sequentially along the number of memristive bit cells.

[0016] The present specification further describes resistive random access memory, including a number of memristive devices electrically coupled together to form an array of memristive devices, each memristive device including a field-effect transistor and a memristor electrically coupled with the filed-effect transistor wherein a discrete analog sequence is stored on the resistive random access memory cell by programming, in an ordered sequence, a set of targeted analog values in the memristive bit cells, and attenuating writing errors by noise-shaping.

[0017] The present specification also describes a memory device, including a number of memristive cells, each memristive cell including a transistor and a memristor electrically coupled to the transistor wherein a discrete analog sequence is stored on the memory device by programming, in an ordered sequence, a set of targeted analog values in the memristive cells, and attenuating writing errors by noise-shaping.

[0018] As used in the present specification and in the appended claims, the term "memristive device" is meant to be understood broadly as any device that stores a value as a resistance. In one example, a memristive device may be a passive two-terminal electronic device that is built to express only the property of memristance. In another example, the memristive device may be a unipolar resistive random-access memory (RRAM). In yet another example, the memristive device may be a phase change random-access memory (PCRAM). In still another example, the memristive device may be a memristor.

[0019] As used in the present specification and in the appended claims, the term "memristance" is meant to be understood as a property of an electronic component such that 1.) bipolar switching - an electronic charge that flows in one direction through a circuit creates an increased resistance while if charge flows in the opposite direction in the circuit, the resistance will decrease, or 2.) unipolar switching - a current of a particular magnitude flowing in either direction creates an increased resistance while a current of a different magnitude flowing in either direction causes a decreased resistance. If the flow of charge is stopped by turning off the applied voltage, the component will 'remember' the last resistance that it had, and when the flow of charge starts again the resistance of the circuit will be what it was when it was last active.

[0020] Further, as used in the present specification and in the appended claims, the term "a number of" or similar language is meant to be understood broadly as any positive number including 1 to infinity.

[0021] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough

understanding of the present systems and methods. It will be apparent, however, to one skilled in the art that the present apparatus, systems and methods may be practiced without these specific details. Reference in the specification to "an example" or similar language means that a particular feature, structure, or characteristic described in connection with that example is included as described, but may not be included in other examples.

[0022] Turning now to the figures Fig. 1 is a block diagram of a memory device according to one example of the principles described herein. The memory device (100) may be implemented in an electronic device.

Examples of electronic devices include servers, desktop computers, laptop computers, personal digital assistants (PDAs), mobile devices, smartphones, gaming systems, and tablets, among other electronic devices.

[0023] The memory device (100) may include a number of transistors (105) and a number of memristors (110) electrically coupled to each of the transistors to form a number of memristive memory cells. At least two transistor-memristor configurations will be described herein, however, the present specification contemplates other configurations that accomplishes the functionality of the memory device (100) described herein. Additionally, a number of transistor-memristor memory cells may be electrically coupled together to form at least two different kinds of arrays.

[0024] In one example, each memristor is coupled to a transistor in series. The present specification will refer to this as a serial 1T1 R memory cell. In this example, an array of transistor-memristor memory cells are created by electrically coupling together the serial 1T1 R memory cell in parallel. This configuration may be seen in Fig. 2 of the present specification and will be described in more detail below.

[0025] In another example, each memristor is coupled to a transistor in parallel. The present specification will refer to this as a parallel 1T1 R memory cell. In this example, an array of transistor-memristor memory cells are created by electrically coupling together the parallel 1T1 R memory cells in series. This configuration may be seen in Fig. 5 and will be discussed in more detail below.

[0026] During operation, the memory device (100) receives as input a discrete analog signal (1 15). As will be described below, this discrete analog signal is stored on the memristors of the memory cells in an ordered sequence as targeted analog values. Memristive devices are used occasionally to store either a high-resistive state or a low-resistive state. However, the present memory device (100) uses the continuum of states that exist in a memristive device to store, as close as possible, the values of the discrete-time analog signals. Each resistive state that each memristor is set to may indicate a particular analog value of the discrete analog signal.

[0027] The transistor-memristor memory cells described above may include a bipolar resistive random-access memory (RRAM) cell or a unipolar RRAM cell. In bipolar RRAM, a relatively low resistive state are can be set when sufficient current is ran through in one direction while a relatively high resistive state can be reset when a current is ran through in the opposite direction. In a unipolar RRAM cell, the switching between the lower and higher states is accomplished by using the same polarity of current to set and reset the cell.

[0028] Fig. 2 is a circuit diagram of a number of serial 1T1 R (205) memory cells electrically coupled in parallel to form an array (200) according to one example of the principles described herein. In the example shown in Fig. 2, 8 serial 1T1 R (205) memory cells are shown and labeled as R Rs. As described above, the serial 1T1 R (205) memory cells are arranged in parallel with each terminal end being electrically coupled to a top terminal voltage (V _T ) and a bottom terminal voltage (V _B ). Each serial 1T1 R (205) memory cell may then have an analog signal programmed to it by setting a resistive state of the memristor in the serial 1T1 R (205) memory cell. Thus, a discrete-time ordered sequence representing a number of discrete analog values may be programmed on the parallel group of serial 1T1 R (205) memory cells. The current (210) through the selected serial 1T1 R (205) memory cell is show in Fig. 2 as a dashed line. The voltage or sequence of voltages applied to achieve the current (210) may be sufficient to set the memristor (215) or memristors (215) to a resistive state representative of an analog signal to be saved.

[0029] In Fig. 2, all but one of the transistors in the parallel array (200) is turned off. For the remaining "on" serial 1T1 R (205) memory cell (the

"selected" cell), current flows through the transistor and memristor thereby connecting the single connect bit-cell to the top terminal voltage (V _T ) and bottom terminal voltage (V _B ) rails. By changing the voltage on either the top terminal voltage (V _T ) rail or bottom terminal voltage (V _B ) rail, either polarity voltage can be applied to the serial 1T1 R (205) memory cells to effect forming, setting, resetting, or reading of the selected memory cell.

[0030] The hardware used and the process of sequentially selecting the serial 1T1 R (205) memory cells in Fig. 2, is shown in Figs. 3 and 4. Fig. 3 is a circuit diagram of a number of serial 1T1 R (205) memory cells electrically coupled in parallel to form an array (200) that is electrically coupled to a shift register chain (305) according to one example of the principles described herein. Fig. 4, represents the method, using the clock shown in Fig. 3, of reading back an ordered sequence of values stored on the parallel array (200) of serial 1T1 R (205) memory cells.

[0031] Turing first to Fig. 3, a shift register chain (305) is electrically coupled to the serial 1T1 R (205) parallel array (200). To read back an ordered sequence of values from this parallel array (200) of serial 1T1 R (205) cells, each shift register (310) in the shift register chain (305) may drive a matching transistor gate of one of the serial 1T1 R (205) cells. By shifting a single "1" value through the shift register chain (305), with each cycle of a shift register (310) the "1" advances in the shift register chain (305) and activates the next select transistor in the sequence while a "0" rolls into the previously active shift register (310) deactivating that shift register's (310) select transistor.

[0032] This process is described in Fig. 4 which shows a number of circuit diagrams demonstrating the propagation of a signal through a parallel array (200) of serial 1T1 R (205) cells according to one example of the principles described herein. Although Figs. 3 and 4 show only 8 serial 1T1 R (205) electrically coupled together to form a parallel array (200), any number of serial 1T1 R (205) cells may be coupled together to form the array (200). Additionally, while only a single serial 1T1 R (205) cell is depicted in Figs. 3 and 4 as being selected, any number of the serial 1T1 R (205) cells may be selected according to the methods described herein.

[0033] In an example, an analog sequence of eight values may be programed into the serial 1T1 R (205) memory cells in parallel. Although Fig. 4 shows that a single analog value is set and, as it is read, is sequenced through the serial 1T1 R (205) memory cells, the present specification contemplates that each serial 1T1 R (205) memory cell may be accessed individually to set a resistance that correlates with a sampled analog value. In this way, an analog signal may be stored and read quickly. As will be described herein, the individual resistive values read from each of the serial 1T1 R (205) may be added together such that their values may compensate for any corrupted analog value.

[0034] Fig. 5 is a circuit diagram of a number of parallel 1T1 R (505) memory cells electrically coupled in series to form an array (500) according to one example of the principles described herein. In the example shown in Fig. 5, 8 parallel 1T1 R (505) memory cells are shown and labeled as R Rs. As described above, the parallel 1T1 R memory cells (505) are arranged in serial with the strand of the parallel 1T1 R memory cells (505) being connected to a left terminal voltage (V _L ) and a right terminal voltage (V _R ). Each parallel 1T1 R (505) memory cell may then have an analog value programmed to it by setting a discrete resistive state of the memristor in the parallel 1T1 R memory cell (505). Where a specific memristor (510) is to be accessed, that cell's transistor (515) may be left "off" by setting the gate of the transistor (515) in parallel with the memristor (510) to 0V. The rest of the parallel 1T1 R memory cells (505) may be placed "on" by applying some supply voltage (V _D D) to the transistors' gates (515). Each of the parallel 1T1 R memory cell (505) that is turned on is shorted through by the activated transistor, leaving the terminals of the selected parallel 1T1 R memory cell (505) connected to the terminals V _L and V _R . This allows each parallel 1T1 R memory cells (505) to be accessed individually such that each can be written to and read from.

[0035] The parallel 1T1 R memory cells (505) in series also provides for the summation of multiple stored resistances. Fig. 6 is a circuit diagram of a number of parallel 1T1 R memory cells electrically coupled in series according to another example of the principles described herein. In this example, the transistors (515) for a number of parallel 1T1 R memory cells (505) are selected simultaneously as described above. Specifically, three parallel 1T1 R memory cells (505) (Ri , R ₂ , R3) are simultaneously selected in this example, with the sum of their resistances appearing between terminals V _L and V _R . The memristors (510) may be programmed individually to have a combined and predetermined resistive value.

[0036] Fig. 7 is a number of circuit diagrams demonstrating the propagation of a signal through a serial array (500) of parallel 1T1 R cells according to one example of the principles described herein. As in figure 3 for the parallel chain of serial cells, a shift register chain (305) can be used here to shift a single Ό' along the length of the serial chain of parallel cells, with s in all other shift registers. As described above, an analog value may be stored in each of the memristive devices such that an ordered sequence of those analog values can be read later. In addition, because the resistive value on a number of these parallel 1T1 R memory cells (505) may be added together, low-pass filtering of the signal stream to recover the original analog sequence can be performed with a summation. Low-pass filtering may be useful when noise- shaping is used in writing the stored analog values.

[0037] As mentioned above, while more than one serial 1T1 R (205) memory cell or parallel 1T1 R (505) memory cell in their respective arrays (200, 500) may be selected at a time, the resulting resistance performed when multiple serial 1T1 R (205) memory cells or parallel 1T1 R (505) memory cells can be used as an advantage when dealing with quantized errors and noise- shaping.

[0038] Specifically, assume that w is a discrete-time analog signal with a known Signal-to-Noise ratio (SNR). An attempt may be made to store w in either the serial 1T1 R (205) memory cell array (200) or the parallel 1T1 R memory cell (505) array (500) - with one sample of w in each serial 1T1 R (205) memory cell or parallel 1T1 R memory cells (505) memory cell - with a level of accuracy such that wfs SNR is not degraded. However, due to the physical properties of the memristors or writing circuits involved, this may not be possible. Specifically, the programmability of memristors is very poor such that specific analog values may not be programed to any one memory cell with sufficient accuracy to properly represent the desired analog value.

[0039] The present specification, however, describes storing the sequence of discrete analog signals such that relatively little of the baseband signal is lost. With reference to Figs. 5-7, if the sequence x[n] is stored on the parallel 1T1 R memory cells (505) of the series array (500) such that x is an oversampled and noise-shaped sequence created from the discrete-time signal w, restoration of w from x may be accomplished by low-pass filtering. In one example, in addition to low-pass filtering, the low-passed result may be sub- sampled.

[0040] Oversampling increases the bandwidth of the discrete-time signal programmed into the arrays (200, 500). This may be accomplished by sampling the analog input signal at some higher rate than, for example, the Nyquist criteria to capture the base band. Noise-shaping pushes either representational errors or quantization noise up into the spectrum created by the oversampling and out of the base band. In one example, a first-order noise- shaping algorithm could include: y[n]=x[n]+(e[n]-e[n-1]) Equation 1

[0041] where y[n] is the error corrupted output sequence, x[n] is the error-free input sequence, e[n] is the current error, and e[n-1] is the error observed on the prior output.

[0042] In another example, a second-order noise-shaping algorithm could include: y[n]=x[n]+(e[n]-2e[n-1]+e[n-2]) Equation 2

[0043] Many other noise shaping algorithms are possible. At some later point in the signal processing flow, the original sequence can be restored by low-pass filtering the output from the arrays (200, 500).

[0044] The summation of neighboring values in a discrete-time sequence may be accomplished by implementing the following equation:

Y[0]=(x[0]+x[1] . . . +x[N-1])/N Equation 3

[0045] where x[n] is the discrete-time input, Y[n] is the discrete- frequency output such that Y[0] is the value at 'DC (i.e., the frequency of zero cycles/second point). The division by N in computing Y[0] can be considered a scaling or normalization of Y such that Y*N can be replaced with Z such that Z[0]=(x[0]+x[1] + . . . +x[N-1]). This scaling factor can be removed where appropriate using any number of circuits such as the output-stage voltage divider shown in Fig. 8 coupled to the array of parallel 1T1 R memory cells (505). In addition to the low-pass filter circuit shown in Fig. 8, sub-sampling may optionally be accomplished by either clock bursts that move the selection window M bit between outputs or by ignoring every L output samples (where M and L are integers determined by the specifics of the operation at hand).

[0046] In a serial array of parallel 1T1 R memory cells (505), because the resistance values are added for the parallel 1T1 R memory cells (505) of the selection window, such an array can be used to low-pass filter signals appropriately stored in them. This may provide for a relatively more accurate representation of the stored discrete-time analog signal despite any poor accuracy in storing the individual values of the sequence.

[0047] For the parallel array of serial 1T1 R memory cells described in connection with Fig. 4, other operations than the linear addition of Equation 3 can be performed by the simultaneous selection of multiple memory cells.

These other operations could be tailored to perform useful filtering for attenuating the noise-shaped writing error. In particular, the differences in neighboring cell values that would be characteristic of high frequency elements can be attenuated by the simultaneous selection of multiple memory cells.

[0048] Fig. 9 is a flowchart showing a method (900) of storing a discrete analog sequence according to one example of the principles described herein. The method (900) may begin with programming (905), in an ordered sequence, a set of targeted analog values in a number of memristive bit cells. The memristive bits cells may include a memristor and a transistor electrically coupled to the memristor either in serial or parallel as described above. The number of transistors and memristors serially coupled to each other may further be coupled to each other in parallel. Additionally, the number of transistors and memristors coupled together in parallel may further be coupled to each other in series.

[0049] With these configurations, writing or quantization errors may be attenuated (910) by noise shaping. The noise-shaping may be accomplished as described above in connection with Equations 1 or 2. The method may continue with restoring the discrete analog sequence by shifting a window of memristive bit cell selection signals sequentially along the number of memristive bit cells. In this example the array (200) described above in connection with Fig. 2 may use a shift register. The method may also be used in the array (500) described in connection with Fig. 5 by selectively turning on or off the transistors in the array (500) to read the values.

[0050] Aspects of the present system and method are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to examples of the principles described herein. Each block of the flowchart illustrations and block diagrams, and combinations of blocks in the flowchart illustrations and block diagrams, may be implemented by computer usable program code. The computer usable program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer usable program code, when executed via, for example, a processor of a computer or other programmable data processing apparatus, implement the functions or acts specified in the flowchart and/or block diagram block or blocks. In one example, the computer usable program code may be embodied within a computer readable storage medium; the computer readable storage medium being part of the computer program product. In one example, the computer readable storage medium is a non-transitory computer readable medium.

[0051] The specification and figures describe a resistive random access memory and a corresponding method of storing a discrete analog sequence. The method may take a discrete analog sequence and attenuate any writing or quantization error by noise-shaping. This method may have a number of advantages, including allowing for compact storage of an accurate discrete-time signal despite the poor control over memristor cell storage values. This resistive random access memory also provides for a rapid playback of the signal with a relatively small footprint. [0052] The preceding description has been presented to illustrate and describe examples of the principles described. This description is not intended to be exhaustive or to limit these principles to any precise form disclosed. Many modifications and variations are possible in light of the above teaching.