[0001] This relates generally to semiconductor devices, and more particularly to deep trench contacts in semiconductor devices.

BACKGROUND

[0002] A semiconductor device has a deep trench at least 10 microns deep, with a silicon dioxide liner on sidewalls and bottom of the deep trench. It is desirable to remove the silicon dioxide liner at the bottom of the trench without substantially reducing the silicon dioxide liner on the sidewalls of the deep trench, in order to make a contact to the substrate. A reactive ion etch (RIE) process used to remove the silicon dioxide liner at the bottom of the trench to make contact to the substrate has high ion energies which also remove dielectric material from the liner at the top of the deep trench, which undesirably widens a top portion of the deep trench. Widening the top portion necessitates a thicker layer of deposited silicon dioxide in the liner, which disadvantageously increases fabrication cost.

SUMMARY

[0003] In described examples, a semiconductor device is formed by etching a deep trench at least 10 microns deep in a substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A two-step process is used to remove the dielectric liner at the bottom of the deep trench. A pre-etch deposition step of the two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1A through FIG. II are cross sections of a semiconductor device, depicted in successive stages of an example fabrication sequence.

[0005] FIG. 2 is a cross section of an example semiconductor device. DETAILED DESCRIPTION OF EXAMPLE EMB ODEVIENT S

[0006] The figures are not drawn to scale. Some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with example embodiments.

[0007] FIG. 1A through FIG. II are cross sections of a semiconductor device, depicted in successive stages of an example fabrication sequence. Referring to FIG. 1 A, the semiconductor device 100 is formed in a substrate 102 such as a silicon wafer or a wafer of another semiconductor material. Other forms of the substrate 102, such as an epitaxial layer of semiconductor material, are within the scope of this example. In FIG. 1A through FIG. II, the substrate 102 is divided to show details of a subsequently-formed deep trench more clearly at both a top portion of the deep trench and at a bottom portion of the deep trench. A pad layer 104 is formed over a top surface 106 of the substrate 102. For example, the pad layer 104 may include a layer of thermal oxide at the top surface 106 and a layer of silicon nitride, formed by a low pressure chemical vapor deposition (LPCVD) process, on the layer of thermal oxide. A layer of hard mask oxide 108 is formed over the pad layer 104. For example, the layer of hard mask oxide 108 may be 1 micron to 2 microns thick, depending on a depth of the subsequently-formed deep trench. The layer of hard mask oxide 108 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate (TEOS), also referred to as tetraethoxysilane, or by using a high density plasma (HDP) process. A trench mask 110 is formed over the layer of hard mask oxide 108 so as to expose an area for the deep trench 112. The trench mask 110 includes photoresist formed by a photolithographic process, and may include an anti-reflection layer such as an organic bottom anti -reflection coat (BARC) and/or a hard mask layer of silicon nitride.

[0008] Referring to FIG. IB, the layer of hard mask oxide 108 and the pad layer 104 are removed in the area for the deep trench 112 exposed by the trench mask 110. The layer of hard mask oxide 108 may be removed by an RIE process. The pad layer 104 is subsequently removed, such as by the same RIE process or by another RIE process. The trench mask 110 may optionally be removed or left in place at this time.

[0009] Referring to FIG. 1C, the deep trench 112 is formed by removing material from the substrate 102 using the patterned layer of hard mask oxide 108 as an etch mask. The deep trench 112 is formed by a timed RIE process. The deep trench 112 has a depth 114 of at least 10 microns; the depth 114 may be 25 microns to 40 microns. The deep trench 112 has a width 116 of 0.5 microns to 3 microns. Any remaining portion of the trench mask 110 of FIG. IB is removed by the RIE process to form the deep trench 112. The deep trench 112 may be slightly tapered, as depicted in FIG. 1C.

[0010] Referring to FIG. ID, the layer of hard mask oxide 108 of FIG. 1C may optionally be removed after the deep trench 112 is formed, as depicted in FIG. ID. Alternatively, the layer of hard mask oxide 108 may be left in place during subsequent fabrication steps.

[0011] Referring to FIG. IE, a layer of thermal oxide 118 of a dielectric liner 120 is formed on sidewalls 122 and a bottom 124 of the deep trench 112. For example, the layer of thermal oxide 118 may be 200 nanometers to 300 nanometers thick. A layer of silicon dioxide 126 of the dielectric liner 120 is formed on the layer of thermal oxide 118, such as by a sub-atmospheric chemical vapor deposition (SACVD) process. For example, the layer of silicon dioxide 126 may be 300 nanometers to 700 nanometers thick. The layer of thermal oxide 118 combined with the layer of silicon dioxide 126 provide the dielectric liner 120. The dielectric liner 120 covers the bottom 124 of the deep trench 112 and has a space 128 of at least 300 nanometers proximate to the bottom 124, so that a thickness of the dielectric liner 120 at the bottom 124 is not more than a thickness of the dielectric liner 120 on the sidewalls 122.

[0012] For example, a total thickness of the dielectric liner 120 may be 500 nanometers to 1 micron, and is selected to provide a desired breakdown strength for operation of the semiconductor device at a particular voltage. In another version of this example, the relative thicknesses of the layer of thermal oxide 118 and the layer of silicon dioxide 126 may be varied to provide desired process latitude. In an alternative version of this example, the dielectric liner 120 may consist of the layer of thermal oxide 118 alone, without the layer of silicon dioxide 126.

[0013] Referring to FIG. IF, a preetch deposition process of a two step process is performed to form a protective polymer 136 on an existing top surface of the semiconductor device 100 over the top surface 106 of the substrate 102, extending onto the dielectric liner 120 in the deep trench 112 proximate to the top surface 106 of the substrate 102. For example, the protective polymer 136 may be 10 nanometers to 50 nanometers thick over the top surface of the semiconductor device 100 adjacent to the deep trench 112. Substantially no polymer is formed on the dielectric liner 120 at the bottom 124 of the deep trench 112. Substantially no dielectric material is removed from the dielectric liner 120 during the pre etch deposition process. One method for forming the protective polymer 136 will now be described. The semiconductor device 100 is placed in a first chamber 130, such as an etch chamber of a wafer processing tool. A substrate chuck, not shown, supporting the substrate 102 may be held at a temperature of 0 °C to 35 °C. A carrier gas such as argon is flowed into a first plasma region 132 of the first chamber 130 over the semiconductor device 100 at a rate of 125 standard cubic centimeters per minute (seem) to 1500 seem. A fluorinated hydrocarbon with a fluorine-to-carbon atomic ratio of at least 2 to 1, such as a perfluorinated hydrocarbon (e.g., octafluorocyclobutane (C ₄ F ₈ ) as depicted in FIG. IF) is flowed into the first plasma region 132 at a rate of 10 seem to 50 seem with the carrier gas. Fluoromethane (CH ₃ F) is flowed into the first plasma region 132 at a rate of 20 seem to 80 seem, with the fluorinated hydrocarbon. A pressure in the first plasma region 132 is maintained at 35 millitorr to 65 millitorr. Radio frequency (RF) power is applied to an electrode 134 over the first plasma region 132 at an average power level of 0.5 watts to 1 watt per square centimeter of the substrate 102, causing a plasma to be formed in the first plasma region 132. The plasma causes the fluorinated hydrocarbon and the fluoromethane to react to form the protective polymer 136 on the existing top surface of the semiconductor device 100, extending onto the dielectric liner 120 in the deep trench 112 proximate to the top surface 106 of the substrate 102. Substantially no polymer is formed on the dielectric liner 120 at the bottom 124 of the deep trench 112. Substantially no dielectric material is removed from the dielectric liner 120 during the pre-etch deposition process. In another version of this example, the fluorinated hydrocarbon may be hexafluorocyclobutane (C ₄ F ₆ ), octafluorocyclopentane (C ₅ F ₈ ), perfluorocyclohexane (C ₆ F ₁₂ ), perfluoropropane (C ₃ F ₈ ), perfluoroethane (C ₂ F ₆ ) or tetrafluorom ethane (CF ₄ ).

[0014] Referring to FIG. 1G, a main etch process of the two-step process is performed to remove the dielectric liner 120 at the bottom 124 of the deep trench 112. The main etch process causes no substantial degradation of the dielectric liner 120 on the sidewalls 122 of the deep trench 112. Concurrently, the main etch process reacts the fluorinated hydrocarbon and the fluoromethane to maintain and possibly increase the protective polymer 136. The protective polymer 136 may increase in thickness, such as by 100 nanometers to 500 nanometers on the top surface of the semiconductor device 100 adjacent to the deep trench 112. The protective polymer 136 advantageously prevents removal of dielectric material from the dielectric liner 120 during the main etch process. An example method of performing the main etch process will now be described. The semiconductor device 100 is placed in a second chamber 138, which may be the first chamber 130 of FIG. IF. A substrate chuck, not shown, supporting the substrate 102 may be held at a temperature of 0 °C to 35 °C. A carrier gas such as argon is flowed into a second plasma region 140 of the second chamber 138 over the semiconductor device 100 at a rate of 125 seem to 1500 seem. A fluorinated hydrocarbon with a fluorine-to-carbon atomic ratio of at least 2 to 1, designated as C ₄ F ₈ in FIG. 1G, is flowed into the second plasma region 140 at a rate of 20 seem to 80 seem with the carrier gas. Fluoromethane is flowed into the second plasma region 140 at a rate of 5 seem to 40 seem with the fluorinated hydrocarbon. A pressure in the second plasma region 140 is maintained at 20 millitorr to 30 millitorr. RF power is applied to an electrode 142 over the second plasma region 140 at an average power level of 3 watts to 5 watts per square centimeter of the substrate 102, causing a plasma to be formed in the second plasma region 140. The plasma generates fluorine radicals which remove the dielectric liner 120 at the bottom 124 of the deep trench 112.

[0015] The sidewalls 122 are substantially straight up to the top surface 106 of the substrate 102, and not flared, enabling the deep trench 112 to be located closer to components of the semiconductor device 100 and thus advantageously reducing a size of the semiconductor device 100. The dielectric liner 120 has a substantially uniform thickness up to the top surface 106 of the substrate 102, advantageously enabling a thinner layer of silicon dioxide 126, advantageously reducing a fabrication cost of the semiconductor device 100. In one version of this example, the pre-etch deposition process and the main etch process may be performed in the same chamber 130 and 138, the RF power may be continued from the pre-etch deposition process to the main etch process, and flows of the fluorinated hydrocarbon and the fluoromethane may be continued and adjusted from the pre-etch deposition process to the main etch process, so that a plasma is advantageously maintained from the pre-etch deposition process to the main etch process, eliminating the need to strike a plasma at the low pressure of the main etch process.

[0016] Referring to FIG. 1H, an ash process is performed to remove the protective polymer 136 of FIG. 1G. The ash process causes no substantial degradation of the dielectric liner 120 on the sidewalls 122 of the deep trench 112. An example ash process will now be described. The semiconductor device 100 is placed in a third chamber 144, which may be the first chamber 130 of FIG. IF and/or the second chamber 138 of FIG. 1G. A carrier gas such as argon is flowed into a plasma region 146 of the second chamber 138 at a rate of 500 seem to 1000 seem. Oxygen gas is flowed into the plasma region 146 at a rate of 125 seem to 500 seem. A pressure in the plasma region 146 is maintained at 150 millitorr to 300 millitorr. RF power is applied to an electrode 148 over the plasma region 146 at an average power level of 0.5 watts to 1 watt per square centimeter of the substrate 102, causing a plasma to be formed in the plasma region 146. The plasma generates oxygen radicals which remove the protective polymer 136 of FIG. 1G. In one version of this example, the ash process may be performed in the same chamber 138 as the main etch process, so that polymer deposited on surface of the chamber 138 during the main etch process is advantageously removed during the ash process, preventing buildup of polymer, and desirably increasing consistency of the main etch process.

[0017] Referring to FIG. II, an electrically conductive trench fill 150 is formed in the deep trench 112, contacting the substrate 102 at the bottom 124. For example, the trench fill 150 may include polycrystalline silicon, referred to as polysilicon, doped to have a same conductivity type as the substrate 102 at the bottom 124 of the deep trench 112. The trench fill 150 may be formed by forming one or more layers of polysilicon over an existing top surface of the semiconductor device 100, extending into the deep trench 112 and contacting the substrate 102 at the bottom 124. The polysilicon may be doped during formation of the layers, or may be doped by ion implantation. Polysilicon over the top surface 106 of the substrate 102 is subsequently removed, such as by a chemical mechanical polish (CMP) process and/or an etchback process.

[0018] FIG. 2 is a cross section of an example semiconductor device. The semiconductor device 200 is formed in a substrate 202 as described in reference to FIG. 1A. In this example, the substrate 202 includes an n-type buried layer 252; semiconductor material in the substrate 202 above, below and surrounding the n-type buried layer 252 is p-type.

[0019] A first deep trench 212, which is at least 10 microns deep, has a closed-loop configuration and surrounds and abuts the n-type buried layer 252. The first deep trench 212 has a first dielectric liner 220 abutting the substrate 202 and extending from proximate to a top surface 206 of the substrate 202 to proximate to a bottom 224 of the first deep trench 212. At least a portion of the bottom 224 of the first deep trench 212 is free of the first dielectric liner 220. A first trench fill 250 of p-type polysilicon is disposed in the first deep trench 212, extending to the bottom 224 and making contact to the p-type semiconductor material of the substrate 202. Sidewalls of the first deep trench 212 are substantially straight up to the top surface 206 of the substrate 202, accruing the advantages described in reference to FIG. 1G.

[0020] The semiconductor device 200 includes a second deep trench 254 which extends to the n-type buried layer 252. The second deep trench 254 is at least 10 microns deep and has a lateral aspect ratio less than 2, that is, a ratio of a lateral length to a lateral width is less than 2. The second deep trench 254 has a second dielectric liner 256 abutting the substrate 202 and extending from proximate to the top surface 206 of the substrate 202 to a bottom 258 of the second deep trench 254. At least a portion of the bottom 258 of the second deep trench 254 is free of the first dielectric liner 220. A second trench fill 260 of n-type polysilicon is disposed in the second deep trench 254, extending to the bottom 258 and making contact to the n-type semiconductor material of the n-type buried layer 252. Sidewalls of the second deep trench 254 are substantially straight up to the top surface 206 of the substrate 202, accruing the advantages described in reference to FIG. 1G.

[0021] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.