Title:
SUBSTRATE HAVING WIRING AND METHOD FOR FORMING WIRING
Document Type and Number:
WIPO Patent Application WO/2018/143037
Kind Code:
A1
Abstract:
Provided are a substrate having wiring and a method for forming wiring with which it is possible to easily control the length of wiring that links together face-up chips and to form wiring. Specifically, provided is a substrate 1 having wiring in which an electrode terminal 11a of a first chip 11 provided on a substrate and an electrode terminal 12a of a second chip 12 are connected by wiring 21, wherein: the substrate 1 having wiring has a first underlayer 31 provided between a substrate W and the first chip 11, a second underlayer 32 provided between the substrate W and the second chip 12, and a linking layer 41 that has a flat surface on the obverse surface thereof and links the first chip 11 and the second chip 12; a connection position between the wiring 21 and the electrode terminal 11a of the first chip 11 mounted on the first underlayer 31, a connection position between the wiring 21 and the electrode terminal 12a of the second chip 12 mounted on the second underlayer 32, and the flat surface of the linking layer 41 are located on the same plane; and the wiring 21 is formed through the flat surface of the linking layer 41.
Inventors:
TOMOEDA SATOSHI (JP)
ARAI YOSHIYUKI (JP)
SHISHINO KAZUYUKI (JP)
ARAI YOSHIYUKI (JP)
SHISHINO KAZUYUKI (JP)
Application Number:
PCT/JP2018/002196
Publication Date:
August 09, 2018
Filing Date:
January 25, 2018
Export Citation:
Assignee:
TORAY ENG CO LTD (JP)
International Classes:
H01L23/12; H05K1/11; H05K1/18
Foreign References:
| JP2012248694A | 2012-12-13 | |||
| JP2015195322A | 2015-11-05 | |||
| JP2013115070A | 2013-06-10 |
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