Title:
SUBSTRATE JOINING METHOD AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2013/129472
Kind Code:
A1
Abstract:
This substrate joining method, which joins a first substrate to which a plurality of semiconductor devices are formed and a second substrate to which a plurality of semiconductor devices are formed, has: a first step for, at to surface to which the plurality of semiconductor devices are formed of the first substrate, forming a semiconductor device region, which is higher than the region to become scribe lines between each semiconductor device, and, at the region to become scribe lines, forming a liquid supply region having the same height as adjacent semiconductor device regions and that connects adjacent semiconductor device regions; a second step for, in the second substrate, forming a liquid supply hole that is at a position corresponding to the liquid supply region and that penetrates in the thickness direction of the second substrate; a third step for overlapping the first substrate and the second substrate; and a fourth step for supplying processing liquid to the liquid supply region through the liquid supply hole, and joining the first substrate and the second substrate.
Inventors:
IWATSU HARUO (JP)
KITAHARA SHIGENORI (JP)
MATSUMOTO TOSHIYUKI (JP)
KITAHARA SHIGENORI (JP)
MATSUMOTO TOSHIYUKI (JP)
Application Number:
PCT/JP2013/055121
Publication Date:
September 06, 2013
Filing Date:
February 27, 2013
Export Citation:
Assignee:
TOKYO ELECTRON LTD (JP)
International Classes:
H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| WO2006077739A1 | 2006-07-27 |
Foreign References:
| JP2010225803A | 2010-10-07 | |||
| US20110008632A1 | 2011-01-13 | |||
| JP2007042904A | 2007-02-15 |
Attorney, Agent or Firm:
KANEMOTO, Tetsuo et al. (JP)
Tetsuo Kanamoto (JP)
Tetsuo Kanamoto (JP)
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Claims: