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Title:
SUBSTRATE PROCESSING SYSTEM AND OPERATION VERIFYING METHOD
Document Type and Number:
WIPO Patent Application WO/2007/148640
Kind Code:
A1
Abstract:
A substrate processing system not increasing the burden on the main controller of a semiconductor manufacturing apparatus and used for automatically verifying the operation of various components of the semiconductor manufacturing apparatus. In this substrate processing system, verifying data for an operating semiconductor manufacturing apparatus (1) is collected in a sharing way by a main controller (5), a data collection auxiliary computer (2), and a data collecting computer (3) on-line over a network (6), and a verifying computer (4) verifies the operation states all at a time.

Inventors:
YAMAGUCHI, Hideto (Yasuuchi 2-chome Yatsuo-machi, Toyama-sh, Toyama 93, 9392393, JP)
山口 英人 (〒93 富山県富山市八尾町保内二丁目1番地 株式会社日立国際電気内 Toyama, 9392393, JP)
JOHO, Yasuhiro (Yasuuchi 2-chome Yatsuo-machi, Toyama-sh, Toyama 93, 9392393, JP)
城宝 泰宏 (〒93 富山県富山市八尾町保内二丁目1番地 株式会社日立国際電気内 Toyama, 9392393, JP)
Application Number:
JP2007/062205
Publication Date:
December 27, 2007
Filing Date:
June 18, 2007
Export Citation:
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Assignee:
HITACHI KOKUSAI ELECTRIC INC. (14-1, Sotokanda 4-chome Chiyoda-k, Tokyo 80, 1018980, JP)
株式会社日立国際電気 (〒80 東京都千代田区外神田四丁目14番1号 Tokyo, 1018980, JP)
YAMAGUCHI, Hideto (Yasuuchi 2-chome Yatsuo-machi, Toyama-sh, Toyama 93, 9392393, JP)
山口 英人 (〒93 富山県富山市八尾町保内二丁目1番地 株式会社日立国際電気内 Toyama, 9392393, JP)
JOHO, Yasuhiro (Yasuuchi 2-chome Yatsuo-machi, Toyama-sh, Toyama 93, 9392393, JP)
International Classes:
H01L21/02; G05B19/418; H01L21/027
Domestic Patent References:
WO2006059625A1
Foreign References:
JPH10275842A
JP2001143981A
JP2002015969A
JP2005109437A
Attorney, Agent or Firm:
AKAZAWA, Hideo (Nakano KI Bldg. 4F, 5-1 Nakano 4-chome,Nakano-k, Tokyo 01, 1640001, JP)
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