Title:
SUBSTRATE TREATMENT METHOD AND SUBSTRATE TREATMENT JIG
Document Type and Number:
WIPO Patent Application WO/2015/137442
Kind Code:
A1
Abstract:
In the present invention, a substrate treatment method includes: supplying an alignment solution to the entire surface of a substrate on which a plurality of semiconductor chips have been formed; arranging a counter substrate, in which alignment solution discharge holes penetrating through the thickness direction have been formed, over the substrate with the alignment solution therebetween; discharging the alignment solution by capillary action to the upper surface side of the counter substrate via the alignment solution discharge holes from scribe lines between the semiconductor chips, and in the area between the counter substrate and the substrate, supplying air to spaces formed on the scribe lines to form a gas-liquid interface between margins of the semiconductor chips and the counter substrate; and adjusting the position of the counter substrate relative to the substrate, by the surface tension of the alignment solution at the gas-liquid interface.
Inventors:
IWATSU HARUO (JP)
Application Number:
PCT/JP2015/057290
Publication Date:
September 17, 2015
Filing Date:
March 12, 2015
Export Citation:
Assignee:
TOKYO ELECTRON LTD (JP)
International Classes:
C25D5/02; C25D7/12; H01L21/3205; H01L21/768; H01L23/522
Foreign References:
| JP2013108111A | 2013-06-06 | |||
| JP2008280558A | 2008-11-20 |
Attorney, Agent or Firm:
KANEMOTO, Tetsuo et al. (JP)
Tetsuo Kanamoto (JP)
Tetsuo Kanamoto (JP)
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