Title:
SUCCESSIVE-APPROXIMATION-REGISTER-TYPE ANALOG-TO-DIGITAL CONVERTER, RELATED CHIP AND ELECTRONIC APPARATUS
Document Type and Number:
WIPO Patent Application WO/2022/120559
Kind Code:
A1
Abstract:
A successive-approximation-register-type analog-to-digital converter, which converts an analog input voltage into a digital signal according to a positive reference voltage and a negative reference voltage, wherein the analog input voltage comprises a positive-terminal input voltage and a negative-terminal input voltage. During operation, the successive-approximation-register-type analog-to-digital converter sequentially enters a sampling phase, a charge reallocation phase and a conversion phase. The successive-approximation-register-type analog-to-digital converter comprises a most-significant-bit capacitor bank, a non-most-significant-bit capacitor bank, a comparator and a controller, wherein in the sampling phase, the controller controls the voltage difference between an upper polar plate and a lower polar plate of each capacitor in the most-significant-bit capacitor bank to be zero, and controls the absolute value of the voltage difference between an upper polar plate and a lower polar plate of each capacitor in the non-most-significant-bit capacitor bank to be the absolute value of the voltage difference between the positive-terminal input voltage and the negative-terminal input voltage; in the charge reallocation phase, the controller controls each capacitor in the most-significant-bit capacitor bank and in the non-most-significant-bit capacitor bank to be disconnected from the analog input voltage, and controls the upper polar plate of each capacitor in the most-significant-bit capacitor bank and in the non-most-significant-bit capacitor bank to be coupled to the comparator, such that charges accumulated by each capacitor in the non-most-significant-bit capacitor bank during the sampling phase are reallocated in each capacitor in the most-significant-bit capacitor bank and in the non-most-significant-bit capacitor bank; and the comparator outputs a first comparison result, the first comparison result corresponding to the most significant bit of the digital signal.
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Inventors:
CHEN JUN XI (CN)
Application Number:
PCT/CN2020/134459
Publication Date:
June 16, 2022
Filing Date:
December 08, 2020
Export Citation:
Assignee:
SHENZHEN GOODIX TECH CO LTD (CN)
International Classes:
H03M1/38
Foreign References:
| CN102801422A | 2012-11-28 | |||
| CN109474278A | 2019-03-15 | |||
| CN110995269A | 2020-04-10 | |||
| CN108055037A | 2018-05-18 | |||
| US20190140654A1 | 2019-05-09 |
Attorney, Agent or Firm:
TIANTAI LAW FIRM (CN)
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