TECHNICAL FIELD

The present disclosure relates to superconducting via interconnects in a printed circuit board.

BACKGROUND

Quantum computing is a relatively new computing method that takes advantage of quantum effects, such as superposition of basis states and entanglement to perform certain computations more efficiently than a classical digital computer. In contrast to a digital computer, which stores and manipulates information in the form of bits (e.g., a "1" or "0"), quantum computing systems can manipulate information using qubits. A qubit can refer to a quantum device that enables the superposition of multiple states (e.g., data in both the "0" and "1" state) and/or to the superposition of data, itself, in the multiple states. In accordance with conventional terminology, the superposition of a "0" and "1 " state in a quantum system may be represented, e.g., as a | 0> + β | 1 >. The "0" and "1 " states of a digital computer are analogous to the | 0> and | 1> basis states, respectively of a qubit. The value | a \ ² represents the probability that a qubit is in I 0> state, whereas the value | β \ ² represents the probability that a qubit is in the I 1 > basis state.

SUMMARY

In general, in a first aspect, the subject matter of the present disclosure may be embodied in a system that includes both a chip having a superconducting quantum circuit element and a printed circuit board. The printed circuit board includes a laminate sheet (e.g., an electrically insulating laminate sheet) and a first superconductor layer on a first side of the laminate sheet, in which the first superconductor layer includes a first superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature. A superconductor coupling element electrically couples the chip to the first superconductor layer of the printed circuit board. Implementations of the system can optionally include one or more of the following features, alone or in combination. For example, in some implementations, the superconductor coupling element includes a superconductor wire bond.

In some implementations, the printed circuit board further includes: a second superconductor layer on a second side of the laminate sheet, the second side opposing the first side, and the second superconductor layer includes a second superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature; a via extending from the first superconductor layer through the laminate sheet to the second superconductor layer; a third

superconductor material in the via, in which the third superconductor material physically and electrically connects the first superconductor layer to the second superconductor layer, and in which the third superconductor material exhibits superconducting properties at or below a corresponding superconducting critical temperature.

The first superconductor material, the second superconductor material and the third superconductor material may be the same superconductor material.

In some implementations, the first superconductor material is aluminum.

In some implementations, the first superconductor layer includes a first base layer in contact with the first side of the laminate sheet, in which the first

superconductor material is on the first base layer, and the second superconductor layer includes a second base layer in contact with the second side of the laminate sheet, in which the second superconductor material is on the second base layer.

In some implementations, the via includes a third base layer in contact with a sidewall of the laminate sheet, in which the third superconductor material is on the third base layer. The first, second and third base layer may be copper. The superconductor quantum computing circuit element may include a qubit.

In some implementations, the first superconductor layer includes a wiring pattern. The wiring pattern may include a ground plane. The wiring pattern may include a power supply plane.

In some implementations, the first, superconductor material, the second superconductor material, or the third superconductor material is titanium nitride or niobium. In some implementations, the base layer may line a sidewall in the via between the laminate sheet and the third conductive material. The first base layer and the first electrically conductive layer may have the same wiring partem. The second base layer and the second electrically conductive layer may have the same wiring pattern.

In some implementations, the laminate sheet includes an FR-4 epoxy laminate sheet.

In some implementations, the device further includes: a second laminate sheet (e.g., a second electrically insulating laminate sheet), in which the second

superconductor layer is on a first side of the second laminate sheet and is between the first laminate sheet and the second laminate sheet; a third superconductor layer on a second side of the second laminate sheet that opposes the first side of the second laminate sheet; a second via extending from the second superconductor layer through the second laminate sheet to the third superconductor layer; and a fourth

superconductor material in the second via, in which the fourth superconductor material physically and electrically connects the second superconductor layer to the third superconductor layer.

In general, in another aspect, the subject matter of the present disclosure can be embodied in devices that include a printed circuit board, the printed circuit board including: a laminate sheet; a first superconductor layer on a first side of the laminate sheet, in which the first superconductor layer includes a first superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature; a second superconductor layer on a second side of the laminate sheet, the second side opposing the first side, in which the second superconductor layer includes a second superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature; and a via extending from the first superconductor layer through the laminate sheet to the second superconductor layer, in which the via includes a third superconductor material that electrically connects the first superconductor layer to the second superconductor layer.

Implementations of the devices may include one or more of the following features. For example, in some implementations, the first superconductor layer includes a first base layer in contact with the first side of the laminate sheet, the first superconductor material is on the first base layer, the second superconductor layer includes a second base layer in contact with the second side of the laminate sheet, and the second superconductor material is on the second base layer.

In some implementations, the via includes a third base layer in contact with a sidewall of the laminate sheet, in which the third superconductor material is on the third base layer.

In some implementations, the laminate sheet is electrically insulating.

In some implementations, the first electrically conductive layer includes a wiring partem.

In some implementations, the wiring pattern comprises a ground plane or a power supply plane.

In some implementations, the second superconductor material is different from the first superconductor material.

In some implementations, each of the first superconductor material, the second superconductor material and the third superconductor material is aluminum.

In some implementations, each of the first base layer, the second base layer, and the third base layer comprises copper.

In some implementations, the first base layer and the first superconductor layer have the same wiring partem.

In some implementations, the first superconductor material or the second superconductor material includes niobium or titanium nitride

In some implementations, the laminate sheet is an FR-4 epoxy laminate sheet. Various embodiments and implementations can include one or more of the following advantages. For example, in some implementations, the devices, systems and/or methods disclosed herein may mitigate qubit decoherence. Furthermore, the devices, systems, and/or methods disclosed herein may, in some implementations, remove resistance on the signal path between the signal source, quantum circuit elements, and ground return paths. For example, in some implementations, by using a superconductor material as the conductor for the ground lines and/or the via interconnect, settling times of control signals sent to qubit devices can be substantially reduced when the printed circuit board is operated below the critical temperature of the superconductor material. In some implementations, a substantial reduction in settling time constant, down to approximately 1 ns or less, may be achieved. For the purposes of this disclosure, a superconductor (or superconducting) material includes a material that exhibits superconducting properties at or below a corresponding superconducting critical temperature.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 A is a schematic illustrating a top view of an example of a chip including superconducting quantum circuit elements that is electrically connected to a printed circuit board.

FIG. IB is a schematic illustrating a cross-section of the example chip and printed circuit board of FIG. 1 A taken at section A- A.

FIG. 2 is a schematic illustrating a cross-section of an example of a multi-layer printed circuit board.

FIG. 3 is a schematic illustrating a cross-section of an example of a

superconducting via in a printed circuit board.

FIG. 4 is a flow diagram of an example process for forming a device according to the present disclosure.

DETAILED DESCRIPTION

During operation of a quantum processor, such as a superconductor quantum annealer or a digital quantum computer, the frequency of a qubit may be dynamically adjusted by supplying a control signal to the qubit. Typically, the control signal may be provided in the form of a square wave or square pulse and the frequencies are tunable over a relatively large range, such as, e.g., 1 GHz. To mitigate decoherence and complete high fidelity quantum computations of the qubits, it may be desirable for the control signal to reach a steady state in a relatively short amount of time. In the case of a square pulse, this means the control signal should reach a steady-state flatness relatively quickly. The amount of time that it takes a signal to reach steady-state may be characterized by a time constant, which can be expressed as L/R, wherein L is the total distributed inductance and R is the total distributed resistance the return currents see from signal to ground. The control signal may be provided using a classical signal source available on a printed circuit board. Traditionally, metals such as copper are used as the conductor for printed circuit boards. However, such metals retain a low resistance when cooled to the superconductor critical temperatures at which a superconductor quantum annealer may be operated. Indeed, copper retains a low resistance even down to temperatures in the milliKelvin range. This small but residual resistance increases the L/R settling time constant, resulting in time constants that may be greater than 10 microseconds. The present disclosure covers devices for quantum processors in which the settling time may be reduced by providing a signal path among the signal source, quantum circuit elements, and ground return paths, in which the signal path has been replaced by a superconductor with no resistance. As explained herein, the removal of resistance may be achieved by providing a superconducting signal retum path between a chip having superconducting quantum circuit elements and superconducting ground connections on a printed circuit board. The superconducting signal path can, in some implementations, allow a substantial reduction in settling time constants down to approximately 1 ns or less.

FIG. 1 A is a schematic illustrating a top view of an example of a chip 100 that is coupled to a printed circuit board 102. For ease of viewing, only a portion of chip 100 and printed circuit board 102 are illustrated. Chip 100 includes a substrate 108 on which one or more electrically conductive layers are formed. In the example shown in FIG. 1 A, an electrically conductive layer formed on substrate includes one or more signal lines 104 and one or more ground lines 106. Substrate 108 includes a dielectric substrate, such as, e.g., single crystal silicon or sapphire. The signal line 104 and ground line 106 are formed on the substrate 108 from a thin film superconductor material (or materials) that exhibits superconducting properties when cooled at or below a corresponding superconductor critical temperature. For example, the signal line 104 and ground line 106 may be formed from aluminum, titanium nitride or niobium, among others. The electrically conductive layer may be formed in a thin film such as, e.g., between several nanometers in thickness to several microns in thickness. In some implementations, the signal line 104 and ground line 106 are formed from a single thin film layer of superconductor material that may be in direct contact with a surface of the substrate 108 (see, e.g., FIG. IB). Although the signal line 104 is shown as a single integral component in the figures, the signal line 104 may be constructed, e.g., as a co- planar waveguide having a center trace line separated in a single plane on either side by a ground plane/line.

The printed circuit board 102 includes a substrate 114 on which are formed one or more electrically conductive layers. The one or more electrically conductive layers may include wiring patterns. The wiring patterns may include, e.g. ground planes, control line wiring, and/or power supply planes. In the present example shown in FIG. 1 A, a first electrically conductive layer includes wire traces such as one or more signal lines 110 and one or more ground lines 112 formed on a top surface of substrate 114. In some implementations, the substrate 114 includes an insulating laminate sheet.

Examples of insulating laminate sheets that may be used as substrate 114 include, but are not limited to, paper or cloths impregnated with resin/epoxy, such as FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, G-l l, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5, ARLON AD- 1000, 45Nk, 55NK, or 85NK. Other example laminate sheets that may be used as the substrate 114 include polytetrafiuoroethylene (PTFE), RF-35 and polyimide. The insulating laminate sheet may have different thicknesses. For example, the insulating laminate sheet may have a thickness between about 1-2 mils to about several hundred mils. The signal line 110 and ground line 112 may be formed from a single layer of, e.g., superconducting material (see, e.g., FIG. IB). Alternatively, in some implementations, just the ground line 112 is formed from a superconductor material, whereas the signal line is formed from an electrically conductive, but non- superconducting capable material. Alternatively, the signal line 110 and ground line 112 may be formed from multiple layers of material that include a base layer for adhesion to the surface of the substrate 114 and at least one layer of superconducting material that exhibits superconducting properties at or below a corresponding superconducting critical temperature. In some implementations, the layer of superconducting material is formed in contact with the base layer. The layer or layers of material forming the signal lines may have various different thicknesses. For instance, the layer or layers of material may have a thickness ranging from, e.g., about 5 microns to about 50 microns, such as thickness of about 25 microns or about 35 microns. Although the signal line 110 is shown as a single integral component in the figures, the signal line 110 may be constructed, e.g., as a co-planar waveguide having a center trace line separated in a single plane on either side by a ground plane.

The signal line 104 and ground line 106 from chip 100 are coupled to the signal line 110 and ground line 112, respectively, on printed circuit board 102. In some implementations, the signal and ground lines 104, 106 are coupled to signal and ground lines 110, 112, respectively, using coupling elements 116 (e.g., wire bonds). For example, signal line 104 may be electrically coupled to signal line 110 using wire bond 116a, whereas ground line 106 may be electrically coupled to ground line 112 using wire bond 116b. The signal lines 116 allow electrical signals, such as control pulses, to be communicated between the circuit elements 118 on chip 100 and circuit elements 120 on chip 102. The coupling elements 116 may be formed from superconducting materials, such as aluminum wire bonds. In some implementations, ultrasonic wire bonding may be used to remove oxides (e.g., native oxides) present on the signal lines, ground lines and/or wire bond material to improve the electrical connection.

Chip 100 includes one or more superconductor circuit elements 118 formed on or within a substrate 108. For ease of viewing, the superconductor circuit elements 118 are illustrated separately from substrate 108 but are understood as being formed on or within substrate 108. The signal line 104 and the ground line 106 may be electrically, capacitively and/or inductively coupled to one or more of the superconductor circuits elements 118 of chip 100. The superconductor circuit elements 118 and the signal and/or ground lines 104, 106 may be part of the same electrically conductive layer formed on the surface of substrate 108.

The superconductor circuit elements 118 may include superconductor quantum computing circuit elements. Superconductor quantum computing circuit elements include circuit elements that are configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. In contrast, classical circuit elements generally process data in a deterministic manner. Superconductor quantum computing circuit elements include quantum computing circuit elements formed using superconductor materials that exhibit superconducting properties at or below a corresponding superconductor critical temperature. For example, the superconductor quantum computing circuit elements may include titanium nitride, aluminum, or niobium, among others. Certain quantum computing circuit elements, such as qubits, may be configured to represent and operate on information in more than one state simultaneously. In some implementations, quantum computing circuit elements include circuit elements such as superconducting co-planar waveguides, quantum LC oscillators, flux qubits, charge qubits,

superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC- SQUID), among others.

In some implementations, the superconductor circuit elements 118 include superconductor classical circuit elements. As explained herein, classical circuit elements generally process data in a deterministic manner. The superconductor classical circuit elements may be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, the superconductor classical circuit elements on the chip 100 may be used to transmit data to and/or receive data from the quantum circuit elements on the chip 100 through electrical or electromagnetic connections. Superconductor classical circuit elements include classical circuit elements formed using superconductor materials that exhibit superconducting properties at or below a corresponding superconductor critical temperature, such as aluminum, titanium nitride, or niobium, among others. Examples of superconductor classical circuit elements include rapid single flux quantum (RSFQ) devices. RSFQ is a digital electronics technology that uses superconductor devices, namely Josephson junctions, to process digital signals. In RSFQ logic, information is stored in the form of magnetic flux quanta and transferred in the form of Single Flux Quantum (SFQ) voltage pulses. Josephson junctions are the active elements for RSFQ electronics, just as transistors are the active elements for semiconductor CMOS electronics. RSFQ is one family of superconductor or SFQ logic. Others include, e.g., Reciprocal Quantum Logic (RQL) and ERSFQ, which is an energy-efficient version of RSFQ that does not use bias resistors.

Printed circuit board 102 may include one or more circuit elements 120 formed on or within substrate 114. For ease of viewing, the circuit elements 120 are illustrated separately from substrate 114 but are understood as being formed on or within substrate 114. The signal line 110 and the ground line 112 may be electrically, capacitively and/or inductively coupled to one or more of the circuit elements 120 of chip 102. Circuit elements 120 may include classical circuit elements such as, e.g., CMOS based digital and analog circuit elements, resistors, inductors, and capacitors. Some classical circuit elements may be in the form of integrated circuit (IC) chips and surface mount devices (SMDs) communicatively coupled to the printed circuit board, e.g., through an electrical connection. The circuit elements 120 may include a source generator circuit element that is operable to provide the control signals, such as square wave pulses, to qubits on the chip 100

In some implementations, the printed circuit board 102 includes a second or more electrically conductive layers. For example, as shown in FIG. IB, the printed circuit board 102 includes a second electrically conductive layer 122 formed on a backside of the substrate 1 14 opposite to that of the first electrically conductive layer that includes signal line 110 and ground line 1 12. The first electrically conductive layer may be physically and electrically connected to the second electrically conductive layer 122 through a conductive via interconnect 124 formed within a via 126 in the substrate 114. For example, as shown in FIG. IB, the ground line 1 12 may be electrically connected to the second conductive layer 122 by a via interconnect 124. In the case of an insulating laminate sheet as the substrate 114, the via interconnect 124 and via 126 may be formed, e.g., by drilling a hole through the laminate sheet and then filling the via 126 with an electrically conductive material. The wire traces and wire bonds of the printed circuit board 102 may be designed to exhibit a predetermined characteristic impedance (e.g., a 50 ohm impedance) that is suitable to achieve an acceptable signal loss and power handling.

To achieve substantially flat and fast settling times for signals (e.g., control pulses) transmitted between chip 100 and chip 102, the signal path between the circuit elements 118 of chip 100 and the circuit elements 120 of chip 102 may be configured and arranged to be superconducting. For example, in some implementations, the signal path between circuit elements 1 18 of chip 100 and the circuit elements 120 of chip 102 are configured and arranged to be provide an entirely superconducting path. That is, each component/element of the signal path may be formed from a superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature. When the chip 100, printed circuit board 102 and wire bonds 1 16 are cooled below the critical temperature of the superconducting material (or materials) that form the components of the signal path, the signal path will exhibit no electrical resistance. For example, each of the signal line 104, the ground line 106, the wire bonds 116, first electrically conductive layer (which includes the signal line 1 10 and the ground line 112), the via interconnect 124 and the second electrically conductive layer 122 may be formed from a superconductor material. In some implementations, just the ground lines 1 12, just the ground lines 1 12 and wire bonds 1 16, or just the ground lines 112, wires bonds and via interconnects 124 coupled to the ground lines 112) are formed from a superconductor material, In some implementations, the ground lines 106 and wire bonds 1 16 may be formed from a superconductor material whereas the signal line 110 may be formed from an electrically conductive material that cannot achieve superconductivity. In some implementations, the ground lines 106 are formed from a superconductor material whereas the signal line 110 and wire bonds 1 16 are formed from an electrically conductive material that cannot achieve superconductivity. The different components of the signal path may be formed from the same or different superconductor material. For example, the second electrically conductive layer on printed circuit board 102 may be formed from the same superconductor material as the first electrically conductive layer or from a different superconductor material. The via interconnects 124 of the printed circuit board may be formed from the same superconductor material as the first electrically conductive layer and/or as the second electrically conductive layer. Alternatively, the via interconnects 124 of the printed circuit board may be formed from a different superconductor material than the first and/or second electrically conductive layer.

By using superconducting materials to form the components of the signal path between circuit elements (e.g., the wire traces, as well as the via interconnects 124), it is possible to decrease the settling time constants of signals transmitted between the chip 100 and the printed circuit board 102 and provide control signals to circuit elements that more closely represent the shape of the desired signal, such as a square pulse. For example, the settling time constants may be decreased to within several hundreds of nanoseconds or less, including less than or equal to 100 ns, less than or equal to 50 ns, less than or equal to 25 ns, less than or equal to 10 ns, less than or equal to 5 ns, less than or equal to 4 ns, less than or equal to 3 ns, less than or equal to 2 ns, or less than or equal to 1 ns. The superconductor material used to form the electrically conductive layers of the printed circuit board 102 and the via interconnects 124 may include, e.g., aluminum, titanium nitride, or niobium, among others.

The printed circuit board 102 shown in FIG. 1 includes a single insulating laminate sheet that separates two electrically conductive layers formed from a superconductor material. However, the printed circuit board may include multiple insulating laminate sheets, each of which may be separated from an adjacent insulating laminate sheet by a corresponding electrically conductive layer formed from a superconductor material. The different electrically conductive layers may be electrically connected by via interconnects formed from a superconductor material in the different insulating laminate sheets.

FIG. 2 is a schematic illustrating a cross-section of an example of a multi-layer printed circuit board 200 that has multiple electrically conductive layers formed from superconductor material, in which the different layers are separated by insulating laminate sheets. Printed circuit board 200 includes: a first electrically conductive layer

201 formed from superconductor material that is located on a top surface of an insulating laminate sheet 202; a second electrically conductive layer 203 formed from superconductor material that is located on a bottom surface of insulating laminate sheet

202 and on a top surface of insulating laminate sheet 204; and third electrically conductive layer 205 formed from superconductor material that is located on a bottom surface of insulating laminate sheet 204 and on a top surface of insulating laminate sheet 206; and a fourth electrically conductive layer 207 that is located on a bottom surface of insulating laminate sheet 206. The laminate sheets having the electrically conductive layers formed thereon are stacked together. To maintain adhesion to one another, the laminate sheets may, e.g., be placed in a press where they are subjected to heating and pressure that fully cures the resin and tightly bonds the sheets together.

Multiple via interconnects 208 are formed in the different insulating laminate sheets 202, 204, 206 and provide electrical connections between the different electrically conductive layers 201, 203, 205, 207. As in the example of FIG. 1 , the different electrically conductive layers 201, 203, 205, 207 may include wire traces that form circuit elements such as signal lines and ground lines. As in the example of FIG. 1, the electrically conductive layers 201, 203, 205, 207 may be communicatively coupled (e.g., electrically coupled) to circuit elements on the printed circuit board 200 including, e.g., CMOS based digital and analog circuit elements, resistors, inductors, and capacitors. In some implementations, the circuit elements are in the form of integrated circuit (IC) chips and/or surface mount devices (SMDs). The device 200 may be electrically coupled to a chip containing quantum circuit elements, such as chip 100 in FIG. 1 using one or more wire bonds.

To aid the adhesion of the superconductor material to the insulating laminate sheets of the printed circuit board, a base layer may be deposited on the board and within the vias followed by deposition of the superconductor material layer on the surface of and in contact with the base layer. FIG. 3 is a schematic illustrating a cross- section of an example of a printed circuit board 300. The printed circuit board includes an insulating laminate sheet 302 such as the sheet 114 shown in FIG. 1 or the sheets 202, 204, 206 shown in FIG. 2. A first electrically conductive layer 304 formed of a superconductor material may be located on a top side of the sheet 302 and a second electrically conductive layer 306 formed of a superconductor material may be located on a bottom side of the sheet 302. The first and second electrically conductive layers 304, 306 may be formed from the same or different superconductor material, such as aluminum, titanium nitride, or niobium, among others. The first and second electrically conductive layers 304, 306 may include trace wiring such as signal lines and ground lines and may be communicatively coupled (e.g., electrically coupled) to circuit elements as explained with respect to FIGS. 1 and 2. The first and second electrically conductive layers 304, 306 are electrically connected together by a via interconnect 308 that extends through a via in the insulating laminate sheet 302.

In the example shown in FIG. 3, the first and second electrically conductive layers 304, 306, as well as the via interconnect 308 are formed on and in contact with the surface of a base layer 310. The base layer 310 may include, e.g., an electrically conductive metal that provides adhesion for the superconductor material of the first and second electrically conductive layers 304, 306 as well as for the superconductor material that forms the via interconnect 308. For example, in some implementations, the base layer 310 may be formed from copper. The copper may be deposited, e.g., by electroplating and then patterned to match the outline/geometric pattern of the trace wires (e.g., signal lines and ground lines) to be formed on the printed circuit board 300. That is, the base layer 310 may have the same trace/wiring pattern as the superconductor layers that form the signal, ground and/or power lines. The thickness of the base layer 310 may vary and includes thicknesses between approximately 5 microns to approximately 50 microns (e.g., approximately 25 microns or approximately 35 microns). Following plating and patterning of the copper, the superconductor material that forms the layers 304, 306 and via interconnect 308 may be formed on the surface of and in contact with base layer 310. For example, in some implementations, aluminum may be electroplated on the surface of the base layer 310 and then patterned to match the outline of the trace wires (e.g., signal lines and ground lines). In some implementations, the electroplating of the base layer 310 fills the space remaining in the vias that is not filled by the base layer 310.

FIG. 4 is a flow diagram of an example process 400 for forming a device according to the present disclosure. The process 400 may include, for example, first providing (402) an electrically insulating laminate sheet. The electrically insulating laminate sheet may include, e.g., any of the laminate sheets described herein such as FR-4. The process 400 may further include depositing (404) a base layer on a surface of the insulating laminate sheet. The base layer may include a metal, e.g. copper, that is deposited using techniques such as electrodeposition (electro-plating or electroless plating). The process 400 may further include depositing (406) a superconductor layer, e.g., aluminum, niobium or titanium nitride, on a surface of the base layer. The superconductor layer may be deposited using techniques such as electrodeposition. Other deposition techniques, such as physical vapor deposition, may be used instead to deposit the base layer and the superconductor layer. The base layer and the

superconductor layer may be patterned (408) to form a trace pattern, such as a ground line, a signal line, and/or a power supply line. Patterning of the base layer and the superconductor layer may include, e.g., using subtractive methods (e.g., where material is removed to form the pattern) or additive methods (e.g., where material is added to form the pattern). For example, in some implementations, the entire board may be pre- coated with a base layer of copper (and/or the superconductor layer). In a subtractive method, portions of the copper (and/or superconductor) may be removed by etching to form the desired pattern. The insulating laminate sheet containing the base layer and superconductor layer traces then may be coupled (410) to a quantum circuit element on a separate chip. For example, a wire bond may be formed that electrically connects the quantum circuit element on the chip to one or more of the trace lines on the printed circuit board.

Optionally, in some implementations, the process may include forming a second base layer and a second superconductor layer on a second opposite side of the insulating laminate sheet. The process further may optionally include forming a via within the insulating laminate sheet and filling the via with an electrically conductive material (e.g., a base layer as described herein and a superconductor material on the base layer) that electrically couples the first superconductor layer to the second superconductor layer.

Implementations of the quantum subject matter and quantum operations described in this specification can be implemented in suitable quantum circuitry or, more generally, quantum computational systems, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computational systems" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, e.g., a system that defines the unit of quantum information. It is understood that the term "qubit" encompasses all quantum systems that may be suitably approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible. It is understood that quantum memories are devices that can store quantum data for a long time with high fidelity and efficiency, e.g., light-matter interfaces where light is used for transmission and matter for storing and preserving the quantum features of quantum data such as superposition or quantum coherence.

Quantum computing circuit elements may be used to perform quantum processing operations. That is, the quantum computing circuit elements may be configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain quantum computing circuit elements, such as qubits, may be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum computing circuit elements that may be formed with the processes disclosed herein include circuit elements such as co-planar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), inductors, capacitors, transmission lines, ground planes, among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements may be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements may be used to transmit data to and/or receive data from the quantum circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements that may be formed with the processes disclosed herein include rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors. Other classical circuit elements may be formed with the processes disclosed herein as well.

During operation of a quantum computational system that uses superconducting quantum computing circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate

implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single

implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various components in the implementations described above should not be understood as requiring such separation in all implementations.

A number of implementations of the invention have been described.

Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other

implementations are within the scope of the following claims.