Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to Josephson Junctions for use in superconducting qubit devices and methods of fabrication thereof.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0004] FIG. 1A provides a schematic illustration of a superconducting quantum circuit, according to some embodiments of the present disclosure.

[0005] FIG. IB provides a schematic illustration of an exemplary physical layout of a

superconducting quantum circuit, according to some embodiments of the present disclosure.

[0006] FIG. 1C provides a schematic illustration of an exemplary transmon, according to some embodiments of the present disclosure.

[0007] FIGS. 2A-2C provide a schematic illustration of a photoresist mask provided over a substrate for fabricating a Josephson Junction using a double-angle shadow evaporation approach.

[0008] FIGS. 3A-3C provide a schematic illustration of fabricating Josephson Junctions using a conventional double-angle shadow evaporation approach.

[0009] FIG. 4 provides a flow chart of an exemplary method for fabricating an hBN Josephson Junction using partially subtractive fabrication, according to some embodiments of the present disclosure.

[0010] FIGS. 5A-5J provide a schematic illustration of fabricating an hBN Josephson Junction according to the exemplary method of FIG. 4, according to some embodiments of the present disclosure.

[0011] FIG. 6 provides a flow chart of an exemplary method for fabricating an hBN Josephson Junction using Damascene fabrication, according to some embodiments of the present disclosure. [0012] FIGS. 7A-7G provide a schematic illustration of fabricating an hBN Josephson Junction according to the exemplary method of FIG. 6, according to some embodiments of the present disclosure.

[0013] FIGS. 8A and 8B provide schematic illustration of exemplary TE /SEM images of hBN Josephson Junction fabricated using partially subtractive fabrication and Damascene fabrication, respectively, according to some embodiments of the present disclosure.

[0014] FIGS. 9A and 9B are top views of a wafer and dies that may include one or more of hBN Josephson Junctions disclosed herein.

[0015] FIG. 10 is a cross-sectional side view of a device assembly that may include one or more of hBN Josephson Junctions disclosed herein.

[0016] FIG. 11 is a block diagram of an example quantum computing device that may include one or more of hBN Josephson Junctions disclosed herein, in accordance with various embodiments.

Detailed Description

Overview

[0017] As previously described herein, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse'' because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0018] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Classical computers encode data into binary values, commonly referred to as bits. At any given time, a bit is always in only one of two states - it is either 0 or 1. Quantum computers use so-called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.

[0019] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results. For this reason, materials, structures, and fabrication methods used for building quantum circuits continuously focus on reducing spurious (i.e. unintentional and undesirable) two-level systems (TLS's), thought to be one of the dominant sources of qubit decoherence. In general, as used in quantum mechanics, a two-level (also referred to as "two- state") system is a system that can exist in any quantum superposition of two independent and physically distinguishable quantum states. Another challenge that is unique to quantum computing is the ability to provide substantially lossless connectivity between qubits at very low powers, e.g. as low as a power of a single photon that may be present in a particular resonator interconnecting two qubits.

[0020] As the foregoing illustrates, ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g. superconducting qubits, quantum dot qubits (e.g. Silicon (Si) quantum dot qubits), single trapped ion qubits, photon polarization qubits, etc.

[0021] Out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer. [0022] All of superconducting qubits operate based on the Josephson Effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction. Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.

[0023] In general, a Josephson Junction (JJ) includes two superconductors coupled by a so-called "weak link" that weakens the superconductivity between the two superconductors. One type of Josephson Junctions, referred to as a "superconductor-insulator-superconductor" (SIS) Josephson Junctions, are realized by providing a thin layer of an insulating material (typically referred to as a "barrier" or a "tunnel barrier") sandwiched, in a stack-like arrangement, between two layers of superconductors. The thin layer of an insulating material acts as the weak link between the two layers of superconductors which are referred to as a "base electrode layer" and a "top electrode layer" of a Josephson Junction to indicate that one of the superconductors is provided below the insulator and the other one is provided above the insulator.

[0024] In quantum circuits, a method typically employed to fabricate SIS Josephson Junctions is known as a "double-angle shadow evaporation" method (also sometimes referred to as "double- angle shadow deposition" or "hanging resist" method). The name "double-angle shadow

evaporation/deposition" reflects the fact that the method involves metal deposition, typically carried out by metal evaporation, at two different angles of incidence with respect to the substrate (hence, double-angle). The name further reflects the fact that metal deposition is performed through a hanging photoresist mask which casts a shadow on at least a part of the substrate, obscuring metal deposition on that part (hence, shadow evaporation/deposition). The tunnel barrier is fabricated by oxidizing a portion of the metal forming a base electrode layer (i.e. the tunnel barrier is an oxide, typically aluminum oxide).

[0025] Such a conventional double-angle shadow evaporation method has several drawbacks.

[0026] One drawback is that controlling oxide growth is challenging. In particular, controlling the thickness of an oxide with a sub-nanometer accuracy, is very difficult. As a result, overall, the double-angle shadow evaporation method is highly susceptible to unintentional variations from one Josephson Junction to another, resulting in non-negligible variability in performance of individual final Josephson Junctions.

[0027] Another drawback is that oxide is prone to forming pinholes and other defects which degrade performance of superconducting qubit devices. [0028] Yet another drawback is that the specific fabrication steps of the double-angle shadow evaporation method limit the choice of materials which may be used to form Josephson Junctions in superconducting qubit devices. For example, the fact that the choice of a tunnel barrier in a double- angle shadow evaporation method is constrained to an oxide of the base electrode layer limits the choice of the materials used for that layer in that the conductive/superconductive material must be such that a controlled layer of oxide may be created on it. In practice, aluminum oxide is the only controlled oxide that may be formed from a metal. Therefore, currently aluminum is the only superconducting metal that is used for the base electrode of Josephson Junctions fabricated using the double-angle shadow evaporation technique. This may be problematic because interconnects in quantum circuits are typically made from other superconducting materials such as e.g. niobium (Nb), titanium nitride (TiN) and niobium titanium nitride (NbTiN), and interfaces between the different superconducting materials used for Josephson Junctions and interconnects present yet another source of losses. Any losses are especially significant in context of quantum circuits where, sometimes, energy as small as that of a single photon is to be transmitted, making loss tolerance very low.

[0029] Still another drawback is that the double-angle shadow evaporation method includes fabrications steps, such as e.g. lift-off and shadow-angle evaporation, which are not suitable for large-scale manufacturing.

[0030] Improvements with respect to at least some of the limitations of conventional Josephson Junctions used in superconducting qubit devices would be desirable.

[0031] Embodiments of the present disclosure propose a novel superconducting qubit device for use as a quantum circuit component. Fabrication techniques for forming such a device are also disclosed.

[0032] In one aspect of the present disclosure, a proposed superconducting qubit device includes a substrate and a plurality of superconducting qubits provided on the substrate, where each superconducting qubit includes one or more Josephson Junctions which include hexagonal boron nitride (hBN) as a tunnel barrier layer provided between a base electrode layer and a top electrode layer of each Josephson Junction (such Josephson Junctions are referred to herein as "hBN

Josephson Junctions").

[0033] Using hBN as a tunnel barrier of Josephson Junctions in superconducting qubits has several advantages. Because hBN is a two-dimensional (2D) material (i.e. a crystalline material which may be grown to be just a single layer of atoms due to all of the chemical bonding being directed in the plane of the atoms), tunnel barrier thickness can be accurately and reliably controlled down to a single atom thickness (for a single-layer hBN) or quantized by increments equal to the inter-planar spacing of hBN, which is about 3.3 Angstroms for an n-layer-thick hBN, resulting in less variations between different Josephson Junctions. Due to the 2D nature of hBN, all bonds may be directed in the plane of the tunnel barrier layer and no dangling bonds may be left to interact and degrade the neighboring base and top electrodes. Furthermore, hBN can act as a diffusion batter and is a non- reactive material, thus enabling increased stability of the junction to thermal processing that would otherwise degrade a typical junction. The breakdown current density of hBN may be orders of magnitude greater than that of a tunnel barrier layer made using a thin oxide layer.

[0034] Still further advantages of hBN Josephson Junctions relate to eliminating the need to use an oxide as a tunnel barrier, e.g. defects such as vacancies and pinholes typically present in oxides may be reduced or eliminated. Compared to the double-angle shadow evaporation method described above, choices of materials used for the base and top layer electrodes of hBN Josephson Junctions described herein are expanded because a tunnel barrier layer is no longer limited to an oxide of the base electrode layer.

[0035] In order to provide substantially lossless connectivity to, from, and between the qubits, some or all of the electrically conductive portions of qubit devices/assemblies proposed herein, i.e. signal lines, ground planes, electrodes, etc., may be made from one or more superconducting materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconducting. In the following, unless specified otherwise, reference to an electrically conductive material implies that a superconducting material can be used. Furthermore, materials described herein as "superconducting materials" may refer to materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate, but which may not exhibit such behavior at e.g. room temperatures).

[0036] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0037] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0038] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0039] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0040] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.

Furthermore, as used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious two-level systems (TLS's) may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher losses, all of which are within the scope of the present disclosure.

[0041] Still further, while the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 gigahertz (GHz) range, e.g. 5-8 GHz range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.

Basics ofJoseohson Junctions

[0042] As previously briefly explained above, quantum computing refers to the use of quantum mechanical properties to perform calculations. Some of these properties include superposition and entanglement. Just as classical computers are composed of bits that can either be in a 1 or a 0 state, a quantum computer is composed of quantum bits (i.e., qubits) which have states of |0) and |1). Quantum mechanics allows for superpositions of the |0) and | 1) states with a general form of α|0) + ϋ|1) where a and b are complex numbers. When a qubit state is measured, it collapses to either state |0) with a probability of that happening being or to state |1) with a probability of the latter being | b | ² . Taking into account the fact that (since the total probability must

sum to unity) and ignoring an overall phase factor which does not have any observable effects, the general state can be re-written as c where φ is the phase difference between

the two states.

[0043] Entanglement occurs when the interaction between two particles (e.g. two qubits) is such that the states of the two cannot be specified independently, but rather can only be specified for the whole system. This causes the states of the two qubits to be linked together such that measurement of one of the qubits, causes the state of the other qubit to collapse.

[0044] In order to realize a quantum computer, a physical system that can act as a qubit is needed. Such a system needs to have at least two states to act as 0 and 1 states. Note that it is not necessary to have a system with exactly only two states if the spacing between each energy level is different, such that each level can be addressed individually. As previously described herein, one type of physical system that could be used to implement qubits is based on use of superconducting materials (superconducting/superconductive qubits).

[0045] In some implementations, namely when superconducting qubits are implemented as transmon qubits, two basic elements of superconducting quantum circuits are inductors and capacitors. However, circuits made using only these two elements cannot make a system with two energy levels because, due to the even spacing between the system's energy levels, such circuits will produce harmonic oscillators with a ladder of equivalent states. A nonlinear element is needed to have an effective two-level quantum state system, or qubit. Josephson Junction is an example of such non-linear, non-dissipative circuit element. Therefore, Josephson Junctions may form the central circuit elements of a superconducting quantum computer.

[0046] In general, a Josephson Junction acts as a superconducting tunnel junction. Cooper pairs tunnel across the barrier from one superconducting layer to the other. The electrical characteristics of this tunneling are governed by so-called Josephson relations which provide the basic equations governing the dynamics of the Josephson effect:

[0047] In these equations, φ is the phase difference in the superconducting wave function across the junction, l _c (the critical current) is the maximum current that can tunnel through the junction, which depends on the barrier thickness and the area of the junction, V is the voltage across the Josephson Junction, I is the current flowing through the Josephson Junction, ft is the reduced Planck's constant, and e is electron's charge. Equations (1) and (2) can be combined to give an equation (3):

[0048] Equation (3) looks like the equation for an inductor with inductance L:

[0049] Since inductance is a function of φ, which itself is a function of I, the inductance of a Josephson Junction is non-linear, which makes an LC circuit formed using a Josephson Junction as the inductor have uneven spacing between its energy states.

Exemplary quantum circuits

[0050] The foregoing provides an illustration of using a Josephson Junction in a transmon, which is one type of superconducting qubits. In other classes of superconducting qubits, Josephson Junctions combined with other circuit elements have similar functionality of providing the non-linearity necessary for forming an effective two-level quantum state, or qubit. In other words, when implemented in combination with other circuit elements (e.g. capacitors in transmons or superconducting loops in flux qubits), one or more Josephson Junctions allow realizing a quantum circuit element which has uneven spacing between its energy levels resulting in a unique ground and excited state system for the qubit. This is illustrated in FIG. 1A, providing a schematic illustration of a superconducting quantum circuit 100, according to some embodiments of the present disclosure. As shown in FIG. 1A, an exemplary superconducting quantum circuit 100 includes two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element). Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear circuit providing a unique two-level quantum state for the qubit. The circuit elements 106 could be e.g. capacitors in transmons or superconducting loops in flux qubits.

[0051] As also shown in FIG. 1A, an exemplary superconducting quantum circuit 100 typically includes means 108 for providing external control of qubits 102 and means 110 for providing internal control of qubits 102. In this context, "external control" refers to controlling the qubits 102 from outside of, e.g., an integrated circuit (IC) chip comprising the qubits, including control by a user of a quantum computer, while "internal control" refers to controlling the qubits 102 within the IC chip. For example, if qubits 102 are transmon qubits, external control may be implemented by means of flux bias lines (also known as "flux lines" and "flux coil lines") and by means of readout and drive lines (also known as "microwave lines" since qubits are typically designed to operate with microwave signals), described in greater detail below. On the other hand, internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.

[0052] Any one of the qubits 102, the external control means 108, and the external control means 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1A).

[0053] As previously described herein, within superconducting qubit implementations, three classes are typically distinguished: charge qubits, flux qubits, and phase qubits. Transmons, a type of charge qubits with the name being an abbreviation of "transmission line shunted plasma oscillation qubits", are particularly encouraging because they exhibit reduced sensitivity to charge noise. FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit 100B where qubits are implemented as transmons, according to some embodiments of the present disclosure.

[0054] Similar to FIG. 1A, FIG. IB illustrates two qubits 102. In addition, FIG. IB illustrates flux bias lines 112, microwave lines 114, a coupling resonator 116, a readout resonator 118, and connectors to external circuitry, connectors being e.g. wirebonding pads, 120 and 122. The flux bias lines 112 and the microwave lines may be viewed as examples of the external control means 108 shown in FIG. 1A. The coupling resonator 116 and the readout resonator 118 may be viewed as examples of the internal control means 110 shown in FIG. 1A.

[0055] Running a current through the flux bias lines 112, provided from the wirebonding pads 120, allows tuning (i.e. changing) the frequency of the corresponding qubits 102 to which each line 112 is connected. In general, it operates in the following manner. As a result of running the current in a particular flux bias line 112, magnetic field is created around the line. If such a magnetic field is in sufficient proximity to the qubit 102, e.g. by a portion of the flux bias line 112 being provided next to the qubit 102, the magnetic field couples to the qubit, thereby changing the spacing between the energy levels of the qubit. This, in turn, changes the frequency of the qubit since the frequency is directly related to the spacing between the energy levels via Planck's equation. The Planck's equation is E=hv, where E is the energy (in this case the energy difference between energy levels of a qubit), h is the Planck's constant and v is the frequency (in this case the frequency of the qubit). As this equation illustrates, if E changes, then v changes. Provided there is sufficient multiplexing, different currents can be sent down each of the flux lines allowing for independent tuning of the various qubits.

[0056] The state(s) of each qubit 102 may be read by way of its corresponding readout resonator 118. As explained below, the qubit 102 induces a resonant frequency in the readout resonator 118. This resonant frequency is then passed to the microwave lines 114 and communicated to the pads 122.

[0057] To that end, a readout resonator 118 may be provided for each qubit. The readout resonator 118 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance), with the resonant frequency of the oscillations being close to the frequency of the qubit. The readout resonator 118 is coupled to the qubit by being in sufficient proximity to the qubit 102, more specifically in sufficient proximity to the capacitor of the qubit 102, when the qubit is implemented as a transmon, either through capacitive or inductive coupling. Due to a coupling between the readout resonator 118 and the qubit 102, changes in the state of the qubit 102 result in changes of the resonant frequency of the readout resonator 118. In turn, because the readout resonator 118 is in sufficient proximity to the microwave line 114, changes in the resonant frequency of the readout resonator 118 induce changes in the current in the microwave line 114, and that current can be read externally via the wire bonding pads 122. [0058] The coupling resonator 116 allows coupling different qubits together in order to realize quantum logic gates. The coupling resonator 116 is similar to the readout resonator 118 in that it is a transmission line that includes capacitive connections to ground on both sides (i.e. a half wavelength resonator), which also results in oscillations within the coupling resonator 116. Each side of the coupling resonator 116 is coupled (again, either capacitively or inductively) to a respective qubit by being in sufficient proximity to the qubit, namely in sufficient proximity to the capacitor of the qubit, when the qubit is implemented as a transmon. Because each side of the coupling resonator 116 has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator 116. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit.

[0059] In some implementations, the microwave line 114 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits. When a single microwave line is used for this purpose, the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits. In other implementations, microwave lines such as the line 114 shown in FIG. IB may be used to only readout the state of the qubits as described above, while separate drive lines such as e.g. drive lines 124 shown in FIG. IB, may be used to control the state of the qubits. In such implementations, the microwave lines used for readout may be referred to as readout lines (e.g. readout line 114), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g. drive lines 124). The drive lines 124 may control the state of their respective qubits 102 by providing, using e.g. wirebonding pads 126 as shown in FIG. IB, a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the 0 and 1 state of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the 0 and 1 states of the qubit.

[0060] Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators, such as e.g. those described above, together form interconnects for supporting propagation of microwave signals. Further, any other connections for providing direct electrical interconnection between different quantum circuit elements and components, such as e.g. connections from electrodes of Josephson Junctions to plates of the capacitors or to superconducting loops of superconducting quantum interference devices (SQUIDS) or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non-quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.

[0061] In various embodiments, the interconnects as shown in FIG. IB could have different shapes and layouts. For example, some interconnects may comprise more curves and turns while other interconnects may comprise less curves and turns, and some interconnects may comprise substantially straight lines. In some embodiments, various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other. As long as these interconnects operate in accordance with use of these interconnects as known in the art for which some exemplary principles were described above, quantum circuits with different shapes and layouts of the interconnects than those illustrated in FIG. IB are all within the scope of the present disclosure.

[0062] Coupling resonators and readout resonators may be configured for capacitive or inductive coupling to other circuit elements at one or both ends in order to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines. Each one of these interconnects may be implemented as any suitable architecture of a microwave transmission line, such as e.g. a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. Typical materials to make the interconnects include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN), all of which are particular types of superconductors.

However, in various embodiments, other suitable superconductors and alloys of superconductors may be used as well.

[0063] FIG. 1C illustrates an exemplary transmon 128 which could be used as any one of the qubits 102, according to some embodiments of the present disclosure. Presence of a capacitor 130 of such a size that capacitive energy is significantly larger than the Josephson energy in a qubit of FIG. 1C indicates that the qubit is a transmon. The capacitor 130 is configured to store energy in an electrical field as charges between the plates of the capacitor.

[0064] The capacitor 130 is depicted as an interdigitated capacitor, a particular shape of capacitor that provides a large capacitance with a small area, however, in various embodiments, other shapes and types of capacitors may be used as well. For example, such a capacitor could be implemented simply as two parallel plates with vacuum in between. Furthermore, in various embodiments, the capacitor 130 may be arranged in any direction with respect to the SQUID or a single Josephson Junction, not necessarily as shown in FIG. 1C.

[0065] In addition, the transmon illustrated in FIG. 1C includes two Josephson Junctions 132 incorporated into a superconducting loop 134. The two Josephson Junctions 132 and the superconducting loop 134 together form a superconducting quantum interference device (SQUID). Magnetic fields generated by the flux bias line 112 connected to the qubit extend to the SQUID (i.e. current in the flux bias line 112 create magnetic fields around the SQUID), which, in turn, tunes the frequency of the qubit.

[0066] In other embodiments, a SQUID could include only one Josephson Junction, or a transmon could be implemented with a single Josephson Junction without the superconducting loop. A single Josephson Junction without the SQUID is insensitive to magnetic fields, and thus, in such an implementation, flux bias lines 112 may not be used to control the frequency of the transmon.

[0067] While FIGS. 1A and IB illustrate examples of quantum circuits comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure. At least some of the one or more qubits 102 shown in FIGS. 1A-1C may include hBN Josephson Junctions as described herein.

[0068] While FIGS. IB and 1C illustrate embodiments specific to transmons, subject matter disclosed herein is not limited in this regard and may include other embodiments of quantum circuits implementing other types of superconducting qubits that would also utilize Josephson Junctions as described herein, all of which are within the scope of the present disclosure.

Furthermore, fabrication methods and resulting hBN Josephson Junctions disclosed herein may be used in quantum circuits implementing qubits other than superconducting qubits as well as in non- quantum circuit components (such as e.g. Rapid single flux quantum (RSFQ) log, low voltage RSFQ (LV-RSFQ), reciprocal quantum logic (RQL), all of which are also within the scope of the present disclosure.

[0069] In various embodiments, circuits employing hBN Josephson Junctions described herein, e.g. quantum circuits such as the one shown in FIGS. 1A-1C as well as non-quantum (i.e. classical) circuits as known in the art, may be used to implement components associated with an integrated circuit (IC). Such components may include those that are mounted on or embedded in an IC, or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., as well as in a number of applications within or associated with non-quantum systems, depending on the components associated with the integrated circuit. The integrated circuit may be employed as part of a chipset for executing one or more related functions in a system.

Detailed description of proposed structures and methods of fabrication thereof

[0070] In order to highlight the advantages offered by the hBN Josephson Junction structures as proposed herein, it would be helpful to first explain how conventional Josephson Junctions are fabricated using a double-angle shadow evaporation method.

[0071] FIGS. 2A-2C provide a schematic illustration of one example of a photoresist mask 200 provided over a substrate 202 for fabricating Josephson Junctions using a double-angle shadow evaporation approach. Each of FIGS. 2A-2C provides a view of the same photoresist mask 200 over the substrate 202, but perspectives of these views are different. FIG. 2A provides a top-down view (i.e. a view from a point above the substrate 202). FIG. 2B provides a cross-sectional view with a cross-section of the structure of FIG. 2A taken along a horizontal dashed line shown in FIG. 2A. Finally, FIG. 2C provides a cross-sectional view with a cross-section of the structure of FIG. 2A taken along a vertical dashed line shown in FIG. 2A. A legend provided within a dashed box at the bottom of FIGS. 2A-2C illustrates patterns used to indicate different elements shown in FIGS. 2A-2C, so that the FIGs are not cluttered by many reference numerals.

[0072] Josephson Junctions may be created by a double-angle shadow evaporation approach using a two-layer photoresist mask 200 that includes a bottom photoresist layer 204 and a top photoresist layer 206 as shown in FIGS. 2A-2C. The bottom layer 206 is undercut from the top layer 204 in that some portions of the top layer 204 hang, or are suspended, over the bottom layer 206. The bottom layer 206 is undercut in such a manner that the top layer 204 of photoresist forms a suspended bridge 208, known as a Dolan bridge, over a section of the substrate 202. Ways for fabricating such undercuts in photoresist are well-known in the art of photolithographic processing and, therefore, are not described here in detail.

[0073] In order to form a Josephson Junction, metals are then deposited through the photoresist mask 200 with the suspended bridge. Conventionally, this is done as illustrated in FIGS. 3A-3C. Each of FIGS. 3A-3C illustrates a result of different subsequent fabrication steps. FIG. 3C provides two views of the same structure. The view on the right side of FIG. 3C is a top-down view (i.e. a view similar to that shown in FIG. 2A). The view on the left side of FIG. 3C is a cross-sectional view with a cross-section of the structure of FIG. 3C taken along a horizontal dashed line shown in FIG. 3C (i.e. a view similar to that shown in FIG. 2B). Each of FIGS. 3A and 3B only provide a cross-sectional view similar to that of the left side of FIG. 3C but at an earlier fabrication step. Similar to FIGS. 2A-2C, a legend provided within a dashed box at the bottom of FIGS. 3A-3C illustrates patterns used in the figures to indicate different elements shown in FIGS. 3A-3C. Moreover, similar reference numerals in FIGS. 2A-2C and FIGS. 3A-3C are used to illustrate analogous elements in the figures. For example, reference numerals 202 and 302, shown, respectively, in FIGS. 2 and 3 refer to a substrate, reference numerals 204 and 304 - to a bottom mask layer, and so on. When provided with reference to one of the FIGS. 2A-2C and FIGS. 3A-3C, discussions of these elements are applicable to other figures, unless stated otherwise. Thus, in the interests of brevity, discussions of similar elements are not repeated for each of the figures but, rather, the differences between the figures are described.

[0074] As previously described herein, according to the double-angle shadow evaporation approach, a Josephson Junction is fabricated by, first, depositing a layer of a first superconductor 310 on the substrate 302, as shown in FIG. 3A, through the two-layer mask such as e.g. the one shown in FIGS. 2A-2C. The first superconductor is deposited at an angle with respect to the substrate 302, as shown in FIG. 3A with an angle Θ1. Slanted dotted-dashed lines in FIG. 3A illustrate the direction of deposition of the first superconductor 310. A layer of the first superconductor 310 may have a thickness between e.g. 10 and 200 nanometers (nm), e.g. between 40 and 100 nm. The first superconductor 310 forms a base electrode of the future Josephson Junction.

[0075] A layer of insulator 311 (also referred to herein as a "dielectric layer 311" or a "dielectric 311"), shown in FIGS. 3B and 3C, is then provided over the first superconductor 310 to form a tunnel barrier of the future Josephson Junction. The tunnel barrier is formed by oxidizing the first superconductor 310, thus creating a layer of first superconductor oxide on its surface. Such an oxide may have a thickness between e.g. 1 and 5 nm, typically for qubit applications between 1 and 2 nm.

[0076] The fact that the choice of a tunnel barrier in a double-angle shadow evaporation method is constrained to an oxide of the base electrode superconductor limits the choice of the

superconductor used as the first superconductor 310 in that the superconductor must be such that a controlled layer of oxide may be created on it. In practice, aluminum oxide is the only controlled oxide that may be formed from a metal. Therefore, currently aluminum is the only superconducting metal that is used for the base electrode of Josephson Junctions fabricated using the double-angle shadow evaporation technique.

[0077] After the layer of dielectric 311 is provided on the first superconductor 310, a second superconductor 312 is deposited through the mask but at a different angle with respect to the substrate 302 than Θ1. FIG. 3B illustrates the second angle as an angle Θ2 and slanted dotted- dashed lines in FIG. 3B illustrate the direction of deposition of the second superconductor 312. In some embodiments, the first and the second superconductors 310, 312 are deposited at the opposite angles, if measured with respect to a normal to the substrate 302. Conventionally, the second superconductor 320 has been aluminum because the first superconductor must be aluminum, as described above (using the same metal for evaporation is easier for fabrication). A layer of the second superconductor 312 may have a thickness between e.g. 10 and 200 nm, typically between 40 and 100 nm. The second superconductor 312 forms a counter electrode (i.e. counter to the base electrode formed by the first superconductor 310) of the future Josephson Junction. The first and second superconductors 310, 312 are usually deposited using a non-conformal process, such as e.g. evaporative deposition. After deposition of the second superconductor 312, the deposition mask is removed, removing with it any first and/or second superconductor 310, 312 deposited on top of it.

[0078] In general, the above-described process of creating patterned structures of one or more target materials (in this case, structures made of the first and second superconductors 310, 312) on the surface of a substrate using a sacrificial material such as photoresist is referred to as a lift-off method. Lift-off is a type of an additive technique, as opposed to subtractive techniques like etching, and may be applied in cases where a direct etching of structural material would have undesirable effects on one or more layers below.

[0079] After the deposition mask is removed, the resulting Josephson Junction is left on the substrate 302 as shown in FIG. 3C as a Junction 314. The Junction 314 is formed by the small region of overlap under the photoresist bridge 308 (i.e. the area under the bridge 308 where the first superconductor 310, covered with a layer of a thin insulating material is overlapped by the second superconductor 312). Dimensions of the Junction 314 along x-axis and y-axis, shown in FIG. 3C as d _x and dy, respectively, are typically between 50 and 1000 nm for any of d _x and d _y .

[0080] Furthermore, as a result of performing the double-angle shadow evaporation as described above, junctions of the first and second superconductors may also form on each side of the

Josephson Junction 314, such junctions shown in FIGS. 3B and 3C as Junctions 316. However, because these junctions are of much larger dimensions than the Josephson Junction 314, e.g.

measured several thousands of nm in the x-direction and hundreds of nm or more in the y-direction, they are essentially infinite for the Josephson effect to take place and, therefore, act as

superconductors rather than Josephson Junctions.

[0081] As described above, drawbacks of the double-angle shadow evaporation method include difficulties in controlling oxide growth and thickness, formation of pinholes and other defects in the oxide layer, and limited choice of materials which could be used in this method.

[0082] Incorporating hBN as a tunnel barrier material of a Josephson Junction allows improving on some of the challenges of the existing Josephson Junction fabrication approaches.

[0083] Hexagonal boron nitride is an insulating 2D material with a bandgap of about 5-6 electron

Volts (eV). When used as a substrate for graphene, which is another 2D material, it improves the electronic properties of graphene due to its 2D nature and the reduced interaction between the neighboring sheets. Inventors of the present disclosure realized that hBN can, advantageously, be used as a tunnel barrier in Josephson Junctions without using graphene.

[0084] hBN is a 2D crystal having alternating boron and nitrogen atoms arranged in a honeycomb lattice. The honeycomb network of atoms give hBN it exceptional mechanical properties (stronger than diamond in the plane) and the alternating B and N atoms in the lattice make it an exceptional insulator with a large bandgap of 5-6 eV. In addition, hBN, even when provided as a single layer, is expected to be an excellent diffusion barrier (if the hBN is defect free), and, therefore, it has the potential to make very robust junctions.

[0085] According to some embodiments of the present disclosure, hBN Josephson Junctions may be fabricated by forming a multilayer structure having a base electrode layer, an hBN tunnel barrier layer, and a top electrode layer, patterned to have dimensions appropriate for a Josephson Junction with desired characteristics. An example of such fabrication is described below with reference to FIG. 4 and FIGS. 5A-5J, showing an example of partially subtractive fabrication. According to other embodiments of the present disclosure, hBN Josephson Junctions may be fabricated using

Damascene fabrication approach, an example of which is described below with reference to FIG. 6 and FIGS. 7A-7G. In other embodiments, other fabrication techniques suitable for forming hBN Josephson Junctions as described herein may be used, all of which being within the scope of the present disclosure. For example, in some further embodiments, surface modification techniques may be employed to promote/enable growth of hBN on some surfaces of a substrate but not others (e.g. first, base electrode layer may be patterned, and then the surface of the substrate with such a base electrode may be processed to ensure that hBN would grow on the base electrode layer but not on other surfaces of the substrate; after that hBN would be grown, e.g. using one of the direct growth processes described below, and then top electrode would be deposited on the hBN).

[0086] FIG. 4 provides a flow chart of an exemplary method 400 for fabricating an hBN Josephson Junction using partially subtractive fabrication, according to some embodiments of the present disclosure. The exemplary method 400 is referred to as a "partially subtractive fabrication" approach to reflect the fact that it involves subtractive patterning in combination with addition of sacrificial material. Besides the advantages allowed due to the use of hBN as a tunnel barrier in Josephson Junctions (e.g. less pinholes and defects and greater control over tunnel barrier thickness), the partially subtractive fabrication approach of the method 400 may improve on some other challenges of existing Josephson Junction fabrication approaches described above. For one, a partially subtractive fabrication process as described herein may be more suitable for large-scale manufacturing at least in that it does not require angled evaporation and lift-off. In addition, employing such a fabrication process allows fabricating Josephson Junctions with no dielectric around them, thus reducing the amount of spurious TLS's in the vicinity of Josephson Junctions. Still further, using a partially subtractive fabrication process as described herein advantageously extends the arsenal of superconducting materials which may be employed as base and top electrodes of Josephson Junctions to include those besides aluminum.

[0087] FIGS. 5A-5J provide a schematic illustration of fabricating an hBN Josephson Junction according to the exemplary method 400 shown in FIG.4, according to some embodiments of the present disclosure. A legend provided within a dashed box at the bottom of FIGS. 5A-5J illustrates patterns used to indicate different elements shown in FIGS. 5A-5J, so that the FIGs are not cluttered by many reference numerals. FIGS. 5A-5J correspond to and are described with reference to processes shown in the flow chart of the method 400 of FIG.4. In particular, FIGS. 5A-5I illustrate a sequence of structures 502, 504, 506, 508, and so on until structure 518, each of which illustrates an exemplary result of a corresponding one of different subsequent fabrication processes 402, 404, 406, 408, and so on until process 418 shown in FIG.4. Thus, each structure 5XX corresponds to a respective process box 4XX of the method 400, e.g. a structure 502 illustrates an exemplary result of a fabrication process 402, a structure 504 illustrates an exemplary result of a fabrication process 404, a structure 506 illustrates an exemplary result of a fabrication process 406, and so on.

Furthermore, each of FIGS. 5A-5I provides two views of the same structure. Namely, the view on the left side of each of FIGS. 5A-5I is a cross-sectional view with a cross-section of the structures taken along a y-z plane, e.g. along a plane indicated with a dashed line AA in FIGS. 5A and 5B (FIGS. 5C-5I illustrate the same cross-sections, but the plane AA is not shown there specifically in order to not clutter the drawings), while the view on the right side of each of FIGS. 5A-5I is a top-down view of an x-y plane. FIG. 5J illustrates a magnified view of a cross-section of the structure 516 shown in FIG. 51.

[0088] Although the operations discussed below with reference to the method 400 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 400 may be illustrated with reference to one or more of the embodiments discussed above, but the method 400 may be used to manufacture any suitable quantum circuit element comprising one or more Josephson Junctions according to any

embodiments disclosed herein.

[0089] The method 500 may begin with providing a stack 535 of various layers over a substrate 522 (process 402 of FIG. 4, result of which is illustrated with a structure 502 of FIG. 5A).

[0090] The substrate 522 may comprise any substrate suitable for realizing quantum circuit components described herein. In one implementation, the substrate 522 may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.

[0091] In some embodiments, the substrate 522 may be cleaned to remove surface-bound organic and metallic contaminants, as well as subsurface contamination, prior to deposition of the stack in process 402. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).

[0092] Josephson Junctions may be realized in what may be referred to as a "trilayer" architecture, or in what may be referred to as a "bilayer" architecture. Trilayer architecture implies that a Josephson Junction includes three layers - namely, the base electrode layer, the tunnel barrier layer, and the top electrode layer, in addition to two wireup superconductors providing electrical connectivity to the base electrode and the top electrodes of the Josephson Junction. Thus, when a trilayer Josephson Junction is implemented over a substrate, there are at least five layers present over the substrate: the first wireup superconductor (also referred to as a "base superconductor (SC) wire layer"), the base electrode of the Josephson Junction, the tunnel barrier of the Josephson Junction, the top electrode of the Josephson Junction, and the second wireup superconductor (also referred to as a "top SC wire layer"), the layers listed in order in which they are provided over the substrate stating from the layer closest to the substrate. On the other hand, bilayer architecture implies that the top wireup superconductor also acts as the top electrode of the Josephson Junction. Thus, when a bilayer Josephson Junction is implemented over a substrate, there are four layers present over the substrate: the base SC wire layer, the base electrode of the Josephson Junction, the tunnel barrier of the Josephson Junction, and the top SC wire layer which also happens to be the top electrode of the Josephson Junction. FIGS. 5A-5J illustrate examples of a trilayer Josephson Junction. However, the method 400 is applicable to both the trilayer and the bilayer architecture, the differences between which are identified in the description below. Therefore, both trilayer and bilayer hBN Josephson Junctions as described herein, and methods of fabrication thereof as described herein, are within the scope of the present disclosure.

[0093] In case a hBN Josephson Junction being fabricated is a trilayer junction, the stack 535 of various layers provided over the substrate 522 includes four layers: a base wireup superconductor layer 524 (indicated in FIG.4 as a "base SC wire layer") for providing electrical connectivity to a base electrode of the Josephson Junction, a base electrode layer 526 (indicated in FIG. 4 as a "JJ base SC) for forming the base electrode of the Junction, a top electrode layer 530 (not indicated in FIG. 4 because FIG.4 is general enough to also be applicable to bilayer JJs) for forming the top electrode of the Junction, and a tunnel barrier layer 528 (indicated in FIG. 4 as a "hBN tunnel barrier") provided between the base electrode layer 526 and the top electrode layer 530.

[0094] The base SC wire 524 layer may comprise any conducting or superconducting material suitable for serving as an interconnect in a quantum circuit, such as e.g. aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (MoRe), etc., or any alloy of two or more superconducting/conducting materials. Similarly, each of the JJ base SC 526 and the JJ top SC 530 layers may comprise any conducting or

superconducting material suitable for serving as base and top electrodes of a Josephson Junction, respectively. Each of the base SC wire 524, the JJ base SC 526 and the JJ top SC 530 layers may be deposited over the substrate 442 using any known techniques for depositing

conducting/superconducting materials, such as e.g. atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating.

[0095] In various embodiments, the thickness of the layer of the base SC wire 524 may be between 20 and 500 nm including all values and ranges therein, e.g. between 40 and 200 nm, e.g. 50 nm. In various embodiments, the thickness of each of the JJ base SC 526 and the JJ top SC 530 may be between 10 and 300 nm including all values and ranges therein, e.g. between 40 and 100 nm.

[0096] As used herein, the term "thickness" refers to a dimension of a certain element or layer as measured along the z-axis as illustrated in FIGS. 5A-5J, while the term "width" refers to a dimension of a certain element or layer as measured along the y-axis as illustrated in FIGS. 5A-5J.

[0097] The tunnel barrier 528 is a layer having one or more 2D layers of hBN. The thickness of the hBN layer(s) will determine the perpendicular resistance through the tunnel barrier layer 528 and, therefore, the thickness can be selected to set the desired resistance of a Josephson Junction, which will also depend on parameters such as e.g. the area of the junction and the superconducting materials that are being used in the junction. A single 2D layer of hBN typically has a thickness between 0.1 and 1.0 nm including all values and ranges therein, e.g. between 0.2 and 0.4 nm. As known in the art, what is considered to be a "thickness" of a 2D layer depends on how the thickness of a single layer is defined. What is typically done for 2D materials is that the inter-planar spacing of the bulk 2D material is used as a thickness of one layer, in which case a thickness of one layer of hBN would be about 3.3 Angstroms. However, when the neighboring material is something other than another layer of hBN, such as e.g. at an interface of hBN and a 3D material or another 2D material, then the spacing can be something different. Furthermore, the spacing may be reduced if there is some interaction between the two materials besides the Van der Waals interactions typical between layers of the bulk layered material, or may be about the same if there are only Van der Waals interactions between the materials, as is the case for individual layers in the bulk hBN.

[0098] In various embodiments, 2-15 of such 2D hBN layers may be used, resulting in the total thickness of the tunnel barrier 528 being between about 0.4 and 6 nm including all values and ranges therein, e.g. between 1 and 5 nm, e.g. 2-3 nm.

[0099] In various embodiments, the tunnel barrier 528 may be provided either by a direct growth approach (i.e. by growing the hBN of the tunnel barrier 528 directly on the base SC 526) or by a growth on a separate substrate followed by a mechanical transfer to the target wafer containing the base SC 526.

[0100] In a direct growth approach, a process flow taking advantage of direct growth/deposition of hBN on the superconductor of one side of the SIS junction (the base superconductor) is utilized in order to make a high-quality interface between the superconducting base material 526 and the insulating hBN tunnel barrier 528. The other electrode of the Josepshon Junction (i.e. the top SC layer 530) would then be deposited on top of the directly grown hBN layer. As a consequence this would typically result in a vertical SIS Josephson Junction, as shown in FIGS. 5A-5J.

[0101] The hBN growth/deposition technique directly determines hBN layer thickness and quality by its growth parameters, e.g. pressure, temperature, growth time, precursors, gas flow rate, ratio of gas flow rates, etc., and can be carried out by a variety of known deposition techniques, including e.g. chemical vapor deposition (CVD) and atomic level deposition (ALD).

[0102] In general, CVD or ALD is a chemical process in which one or more reactive precursor gases are introduced into a reaction chamber and directed towards a substrate in order to induce controlled chemical reactions that result in growth of a desired material on the substrate. The one or more reactive gases may be provided to the chamber at a flow rate of e.g. 1 standard cubic centimeter per minute (seem) to 500 seem, including all values and ranges therein. The reactive gas may be provided with a carrier gas, such as an inert gas, which may include, for example, argon (Ar) or nitrogen (e.g. N2). In some embodiments, the chamber may be maintained at a pressure in the range of 1 milliTorr to 100 milliTorr, including all values and ranges therein, and a temperature in the range of 100" C to 1000° C, including all values and ranges therein. The substrate itself may also be heated. In some embodiments, the process may be plasma assisted where electrodes are provided within the process chamber and are used to ionize the gases. Alternatively, plasma may be formed outside of the chamber and then supplied into the chamber. In the chamber, a layer of solid thin film material is deposited on the surface of the substrate due to reaction of the gas/gasses.

[0103] In order to grow hBN on a substrate (in the example of direct growth - on the base SC electrode 526 provided over the substrate) using CVD or ALD, boron and nitrogen-containing precursors may be used, such as e.g., but not limited to, ammonia borane (BH3-NH3) or borazine (BH)3(NH)3. An inert carrier gas, such as e.g. Ar or N2, in correct proportion to hydrogen, may be provided and may serve several purposes, including, but not limited to, reduction of the metal surface of the substrate, control of hBN nucleation rate on the substrate, and mediation of the diffusivity of precursors and radicals on the substrate.

[0104] In some embodiments, hBN may be grown on a surface of a suitable catalyst that would lower the energy required to decompose the precursor gases into B- and N-containing radicals that are able to nucleate and grow into the first stable hBN layer. In some such embodiments, the material of the base electrode layer 526 may serve as a suitable catalyst for the deposition of the hBN layer 528, but, in general, any superconducting metals such as Nb, NbN, NbTiN, TiN, Al, and any other superconducting metals with high enough melting point to sustain the required growth temperatures are expected to be a suitable catalytic metal for promoting hBN growth. In other embodiments, the base SC 526 may be capped with a thin catalytic metal layer that would be a different conductive or superconductive metal than the bulk of the base SC 526 and which would be better suited to catalyze the decomposition of hBN precursors during the deposition step of the hBN tunnel barrier. Such a catalytic metal layer (not specifically shown in FIG. 5A and the subsequent FIGS) may have a thickness between 5 and 500 nm, including all values and ranges therein.

[0105] As described above, the number of hBN atomic layers determines the resistance of the resulting Josephson Junction and may be chosen in conjunction with the size of the junction, which may be determined by subsequent lithography processes, in order for the resulting Josephson Junction to meet the requirements of a particular application, which could be different for

Josephson Junctions included e.g. in superconducting qubits, cryogenic logic, SQUIDs, etc., all of which are within the scope of the present disclosure. The hBN growth/deposition technique directly determines hBN layer thickness and quality by its growth parameters, such as e.g. pressure, temperature, growth time, precursors, gas flow rates, ratio of gas flow rates, etc., and can be carried out by a variety of known deposition techniques, including CVD and ALD. In various embodiments, hBN growth/deposition may include all or some of the following: boron and nitrogen containing precursors, e.g. (but not limited to) ammonia borane (BH3-NH3) or borazine (BH)3(NH)3; a catalytic metal, e.g. the metal of the base electrode of a Josephson Junction or a different metal provided thereon; an inert gas, e.g. Ar or N2; and hydrogen (H2) gas. In cases where H2 gas is present, it may serve to reduce the metal catalyst surface and remove surface oxide (if present), control hBN nucleation rate on the substrate, and mediate the diffusivity of precursors and radicals on the substrate surface. The B and N solubility of a substrate can also be used to tune the hBN layer thickness and quality.

[0106] The deposition of the top electrode 530 on the previously deposited hBN is preferably carried out with a deposition technique that does not damage the already deposited hBN, e.g. e- beam evaporation, thermal evaporation, molecular beam epitaxy (MBE), or long-throw direct current (DC) sputtering or long-throw ion-beam sputtering. In cases where an energetic plasma is involved, e.g. standard DC sputtering or radio frequency (RF) sputtering, a thin, e.g. a few nanometers thick, protective top metal can first be deposited, e.g. e-beam evaporated, to protect the hBN 528 from damage by the more energetic plasma used during the deposition of the bulk of the top electrode 530 (said protective layer not specifically shown in FIG. 5A and the subsequent FIGS). The thin e-beam evaporated protective layer, e.g. a few nanometers of aluminum or any other suitable superconducting material, would then act as a thin protective layer for the hBN during the deposition of the thicker bulk of the top superconducting metal, which could be the same metal or a different metal from the thin protective metal layer. By the proximity effect, such a thin protective metal layer would take on the superconducting properties, e.g. critical temperature (Tc), superconducting gap, etc. of the bulk superconducting metal and thus the properties of the resulting Josephson Junction would still be determined by the material of the base electrode 526, the hBN tunnel barrier 528, and the top bulk superconducting metal of the top electrode 530. In some embodiments, such a thin protective top metal layer may include a non-superconductive metal that, nevertheless, takes on the superconducting properties of the bulk top superconductor selected for the top electrode 530.

[0107] Providing hBN by, first, growing hBN on a separate substrate followed by a mechanical transfer to the SC 526, may be a suitable alternative process to the direct growth described above in that it may relax the requirements for the growth of the hBN layer(s) as it can now be grown on bulk non-superconducting metal with fewer requirements on growth temperature and other processing parameters as for the direct growth case, where the presence of the base superconducting metal may limit some growth parameters. For example, in some embodiments, hBN may be grown on rolled copper (Cu) foils of ~25-50 micrometers (urn) thickness, which are then subsequently etched away and the hBN layers are mechanically transferred to a target substrate, i.e.to the base electrode of a future Josephson Junction, by known methods.

[0108] An exemplary transfer method may include providing a mechanical support layer, e.g. by depositing (e.g. by spin-coating) a protective polymer layer, e.g. poly(methyl methacrylate) (PMMA), on top of the grown hBN and may include an additional, possibly much sturdier and thicker, mechanical support layer (e.g. transfer tape) on top of the protective polymer layer which is directly in contact with the grown hBN. Together, the polymer layer with the additional mechanical support layer such as a transfer tape would serve as a protective and mechanical support layer during the transfer of the hBN layer that is typically accomplished by chemical etching of the underlying catalytic metal, e.g. if the catalytic metal used to catalyze growth of hBN is Cu, then Cu can be etched using e.g. ferric chloride (FeCI3), which would release the hBN and the protective and mechanical support layer deposited thereon, thereby allowing these layers to be mechanically transferred to the target substrate, e.g. to the base SC 526, with the hBN layer facing the target substrate. After the transfer, the polymer layer and the additional mechanical support layer on top of the hBN layer is removed, e.g. by mechanically removing additional mechanical support layer, if such a layer was present, and by removing the protective polymer layer by chemically dissolving it using a suitable solvent, or by gently ashing it off.

[0109] In order to optimize the interface between the base SC 526 and the hBN tunnel barrier 528, growth of hBN could be carried out on a thin film of a catalytic metal, e.g. 500 nm Cu film, for better flatness, control, and reproducibility, and the transfer could be carried out by a wafer-scale dry process that releases the hBN and the mechanical support layer provided thereon (e.g. PMMA and the transfer tape or other mechanical support layer) by a variety of methods, including

electrochemical bubbling/release or chemical etching. The released hBN and the mechanical support layer are then brought to the target substrate in a controlled, dry environment utilizing wafer-scale techniques, e.g. industrial wafer bonder, as known in the art.

[0110] In some embodiments, the surface of the base SC 526 could undergo a reduction step prior to the dry transfer step which could be carried out in an inert gas or vacuum environment in order to inhibit the growth of a surface oxide between the base SC 526 and the hBN layer(s) and improve the interface by eliminating or reducing adsorbed water, adventitious carbon, and other adsorbates. In some embodiments, such a reduction step could include a buffered oxide etch, an HF etch, or reduction by annealing in a forming gas.

[0111] In case the Josephson Junction being fabricated is a bilayer junction, the stack 535 of various layers provided over the substrate 522 in process 402 would include three of the four layers described above for the trilayer architecture, with the missing layer being the top superconductor layer 530.

[0112] The method 400 may then proceed with forming an opening 536 in the stack 535 deposited in the process 402 (process 404 of FIG.4, result of which is illustrated with a structure 504 of FIG. 5B). As shown with the line AA shown on the top view of FIG. 5B, in order to properly illustrate the opening, the side view of FIG. 5B and subsequent figures is shown as a cross-section along a line that goes through the openings 536.

[0113] Dimensions and a shape of the opening 536 could depend on e.g. the sacrificial material later used to fill the opening, dimensions and shape of the top SC wire layer 534 to be deposited later on, dimensions of the Josephson Junction to be formed, and the etching process used to form the opening 536. For example, in some embodiments, the opening may be rectangular in shape in the x-y plane, as shown in the top view in FIG. 5B. However, in other embodiments, any other openings 536, arranged in any suitable location and in any suitable shape/geometry may be used, all of which being within the scope of the present disclosure.

[0114] The opening 536 extends from the surface of the stack (i.e. from the surface of the JJ top SC 530 in case of a trilayer JJ, or from the surface of the tunnel barrier 528 in case of a bilayer JJ) to the bottom of the stack (i.e. to the bottom of the JJ base SC 526), e.g. to the substrate 522 in case the JJ base SC 526 is provided on the substrate 522.

[0115] In various embodiments, the width of the opening 536 could be between 10 and 500 nm, including all values and ranges therein, e.g. between 20 and 200 nm.

[0116] In various embodiments, any kind of etching techniques in combination with patterning may be used to form the opening 536.

[0117] For example, a patterning technique employing photoresist or other masks defining the dimensions and location of the opening 536 in the stack may be used. An exemplary photoresist patterning technique could include depositing a photoresist over the layer of interest, in this case - over the surface of the stack deposited in the process 402. The photoresist may be a positive or negative resist and may include for example, poly(methyl methacrylate), poly(methyl glutarimide), DNQ/novolac, or SU-8 (an expoxy based negative resist). The photoresist may be chemically amplified containing a photoacid generator and may be based on polymers or co-polymers which contain aromatic rings or alicyclic norbornene derivatives (e.g. for etch resistance), and have protecting groups such as t-butvl. The polymers may include polystyrene or acrylate polymers. The photoresist may be deposited by a casting process such as, for example, spin-coating. The photoresist may then be patterned by optically projecting an image of a desired pattern onto the photoresist using photolithography, such as optical photolithography, immersion photolithography, deep UV lithography, extreme UV lithography, or other techniques. A developer, such as tetramethylammonium hydroxide TMAH (with or without surfactant) at a concentration of in the range of 0.1 N to 0.3 N, may be applied to the photoresist, such as by spin-coating, and portions of the photoresist are removed to expose regions of the underlying layer correlating to the desired pattern. In some embodiments, baking of the substrate may occur before or after any of the above actions. For example, the substrate may be prebaked to remove surface water. After application of the photoresist, a post application bake may occur, wherein at least a portion of the solvents in the photoresist are driven off. After exposure to light, a post-exposure bake may occur to induce chemical reactions, such as de-protecting the photoresist. After patterning, the resist may be hard baked.

[0118] Once patterning has been done to expose portions of the underlying surface of the stack 535 in a patterned mask that defines location and arrangement of the future opening 536, exposed portions of the underlying stack are then chemically etched. During the etch, the exposed portions of the stack are removed until a desired depth is achieved, forming the opening 536 in the stack 535. If photoresist patterning is used for creating a mask for forming the opening 536, the remaining photoresist may then optionally removed via e.g. a process such as ashing, where the photoresist is exposed to oxygen or fluorine, which combines with the photoresist to form ash.

[0119] Next, the opening 536 is filled with an insulating sacrificial material 532 (process 406 of FIG. 4, result of which is illustrated with a structure 506 of FIG. 5C). Since the sacrificial material 532 will need to later be etched to achieve undercutting of the sacrificial material under the bridge over a Josephson Junction to provide a gap between at least a portion of the Josephson Junction and an interconnect for providing the current to the Josephson Junction, e.g. using isotropic etching, etching properties of potential candidate materials are to be considered when selecting a suitable material to be used as the sacrificial material 532. Again, besides appropriate etching characteristics, some other considerations in selecting a suitable material for the sacrificial material 532 may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability). Examples of dielectric materials that may be used as the sacrificial material 532 include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane, polytetrafluoroethylene or poly(methyl methacrylate) (PMMA), fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

[0120] In some embodiments, the sacrificial material 532 may be deposited over the surface of the stack 535 and into the opening 536 using e.g. chemical vapor deposition or/and plasma-enhanced chemical vapor deposition, as typically done in conventional processing. In still other embodiments, the sacrificial material 532 may include a dielectric material formed over the surface of the stack 535 and in the opening 536 using coating techniques involving cross-linking of liquid precursors into solid dielectric materials.

[0121] The method 400 may then proceed with performing a planarization of the sacrificial material 532 to the surface of the stack 535 (process 408 of FIG. 4, result of which is illustrated with a structure 508 of FIG. 5D). During this process, the sacrificial material 532 is removed in order to expose surfaces 538 of the top layer of the stack 535 which may be covered with the sacrificial material 532 as a result of depositing that material into the openings 536. Thus, during

planarization, the sacrificial material 532 is removed to expose the surface 538 of the JJ top SC 530 in case of a trilayer JJ, or to expose the surface 538 of the tunnel barrier 528 in case of a bilayer JJ.

[0122] In various embodiments, planarization may be performed using either wet or dry planarization processes. In one embodiment, planarization may be performed using chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

[0123] Next, a layer of a top SC wire material 534 is provided on the surface 538 of the stack 535 with the opening 536 filled with the sacrificial material 532 (process 410 of FIG. 4, result of which is illustrated with a structure 510 of FIG. 5E). Considerations described above with reference to the base SC wire material 524 are applicable to the top SC wire material 534 and deposition thereof and, therefore, in the interest of brevity, are not repeated here. In some embodiments, the top SC wire material 534 may be the same as the material of the base SC wire material 524 or/and as the material JJ base SC 526. In some embodiments, the top SC wire material 534 may be the same as the material of the JJ top SC 530 in case of a trilayer JJ.

[0124] In some embodiments, the surface of the stack 535 may be cleaned or treated prior to applying the top SC wire material 534 to reduce surface contamination and minimize interface traps and/or promote adhesion, for example using a chemical or plasma clean, or applying heat in a controlled environment. In some embodiments, an adhesion promoter or adhesion layer may be applied prior to application of the top SC wire material 534.

[0125] In various embodiments, the thickness of the top SC wire material 534 may be between 20 and 500 nm including all values and ranges therein, e.g. between 40 and 200 nm, e.g. 50 nm.

[0126] The method 400 may then proceed with patterning the layer of the top SC wire material 534 to form a structure that will serve as a top SC wire bridge over the opening 536 and will provide at least one etch window (process 412 of FIG. 4, result of which is illustrated with a structure 512 of FIG. 5F). An example of such structure is shown as a rectangular structure 540 shown in FIG. 5F. However, in other embodiments, the top SC wire bridge structure 540 could have any other shapes/geometries suitable for forming a bridge over the opening and one or more windows over the opening, the window(s) configured to allow removal of the sacrificial material under the bridge, all of which shapes/geometries being within the scope of the present disclosure. With the rectangular structure 540 shown in FIG. 5F, portion 542 indicated with a dotted line "bridges" the portion of the stack to the left of the opening 536 and the portion of the stack 535 to the right of the opening, while 544-1 and 544-2 indicates two etch windows.

[0127] The dimension of the structure 540 in the y-direction is to be such as to allow formation of a Josephson Junction on one side of the opening 536 and formation of what may be considered as bulk superconductor on the other side of the opening. Example shown in FIG. 5F illustrates the portion of the stack 535 on the right side of the opening 536 as the portion where a Josephson Junction is to be formed, while the portion on the left side of the opening will serve as a bulk superconductor of an interconnect to be formed. In various embodiments, the structure 540 may be between 100 nm and 10 micrometers (micron) in the y-direction, including all values and ranges therein.

[0128] The dimension of the structure 540 in the x-direction is also to be such as to allow formation of a Josephson Junction on one side of the opening 536 and formation of what may be considered as bulk superconductor on the other side of the opening. In various embodiments, the structure 540 may be between 50 nm and 5 micron in the x-direction, including all values and ranges therein.

[0129] In various embodiments, any kind of conventional patterning techniques may be used to form the bridge structure 540 at the desired location on the surface of the stack 535, over the opening 536, such as e.g. patterning techniques employing photoresist or other masks as described above.

[0130] The method 400 may then proceed with patterning the stack 535 to form a future Josephson Junction 546 and a future interconnect portion 548, the Josephson Junction and the interconnect portion separated from one another by the opening 536 and electrically connected by the bridge 542 (process 414 of FIG. 4, result of which is illustrated with a structure 514 of FIG. 5G). Patterning of the stack 535 may involve patterning the stack so that the shape of the stack in each x-y plane down to the upper surface 550 of the base SC layer 524 is the same as that of the top wire bridge structure 540 patterned from the top SC wire layer in the process 412, as shown in FIG. 5G. To that end, patterning techniques as those used to form the opening 536 through the stack may be used, as described above. Unlike the patterning of the opening 536 where the layers of the stack were removed until the layer underlying the base SC wire 524, e.g. the substrate 522, was exposed, removal of the layers of the stack in the process 414 proceeds only until surface 550 of the base SC wire layer 524 is exposed. FIG. 5G illustrates surfaces 550 of the base SC wire layer 524 being exposed as a result of the patterning of the process 414. The boundaries of the future Josephson Junction 546 and the future interconnect portion 548 are indicated in FIG. 5G with dotted lines.

[0131] The method 400 may then proceed with patterning the stack 535 to electrically isolate the Josephson Junction 546 from the interconnect portion 548 except for the electrical connection by the bridge 542 (process 416 of FIG. 4, result of which is illustrated with a structure 516 of FIG. 5H). To that end, conventional patterning techniques, such as e.g. those described above, may be used to remove portions of the base SC wire 524 until the Josephson Junction 546 and the interconnect portion 548 are electrically separated except for the electrical connection by the bridge 542. An example of that shown in FIG. 5H illustrates that the stack 535 may be removed down to the layer underlying the base SC wire layer 524, e.g. down to the substrate 522, so that a portion of the stack 535 on one side of the opening 536 where a Josephson Junction is to be formed (shown as a portion 552 on the right side of the stack in the example of FIG. 5H) is electrically separated from a portion on the other side of the opening that is to serve as a bulk superconductor of the interconnect 548 (shown as a portion 554 on the left side of the stack in the example of FIG. 5H).

[0132] The method 400 may end with removing the sacrificial material 532 through the window 544 to provide a gap between at least a portion of the Josephson Junction and the interconnect portion (process 418 of FIG. 4, result of which is illustrated with a structure 518 of FIG. 51). In some embodiments, removal of the sacrificial material 532 may be carried out by an etching process, such as e.g. an isotropic etch, where the sacrificial material 532 in the opening 536 under the bridge 542 is also etched even though it is not exposed via the window 544 (i.e. at least a portion of the sacrificial material 532 under the bridge 542 is undercut). Isotropic etching etches in multiple directions (both vertically and horizontally), unlike e.g. dry etching which only etches in a single direction, and, therefore, can be used to achieve undercutting of the sacrificial material 532 under the bridge 542, thereby providing a void or a gap between at least a portion of the Josephson Junction 546 and the interconnect portion 548.

[0133] In some embodiments, the gap 536 may comprise vacuum since fabrication and operation of the quantum systems is typically carried out under vacuum. In this context, it is understood that "vacuum" is an idealized term in that a perfect vacuum (i.e. zero pressure) can never be achieved in practical situations. Therefore, the term "vacuum" is used to cover non-zero pressures as long as they are sufficiently low to be considered nearly vacuum. In other embodiments, the gap 536 could contain air or any other gas or a mixture of gasses.

[0134] Any substance suitable for isotropically etching the sacrificial material 532 may be used in the process 418. In various embodiments, an etchant may be e.g. corrosive liquid, such as e.g. hydrofluoric acid (HF) or a chemically active ionized gas (i.e. plasma). As a result of the isotropic etching, a gap is formed between the portions 552 and 554 of the stack 535 so that the stack is electrically connected only via the bridge 542 of the top SC wire 534. Consequences of this are explained in greater detail with reference to FIG. 5J which provides a magnified version of the cross- section structure 518 illustrated in FIG. 51. [0135] As shown in FIG. 5J, as a result of the fabrication method 400 as described above, portions of the stack 535 down to the surface 550 of the base SC wire 524 are provided both on the right side 552 and on the left side 554 of the opening 536. The opening 536 does not show any of the sacrificial material 532 in the example of FIG. 5J because the sacrificial material 536 has been completely etched out, which may be particularly advantageous because the sacrificial material 536 may be prone to having spurious TLS's which are undesirable for quantum circuits. In other embodiments, some of the sacrificial material 526 may remain, as long as the Josephson Junction 546 is still electrically isolated from the interconnect portion 548 as described herein.

[0136] A width of the gap between the Josephson Junction 546 and the interconnect portion 548 may be equal to that of the opening 536.

[0137] Because the opening 536 was formed in the stack 535 and because other parts of the stack 535 were etched to form the Josephson Junction 546, the edges 558 of the tunnel barrier layer 558 portion (indicated in FIG. 5J with a solid thick line) of the Josephson Junction 546 are aligned with edges 556 of the base electrode layer 556 portion (indicated in FIG. 5J with a dotted thick line) of the Josephson Junction 546, both for the bilayer and trilayer junctions. In case the Josephson Junction is a trilayer Junction, as is shown in FIG. 5J, the edges 558 of the tunnel barrier layer portion are further aligned with edges 560 of the top electrode layer 530 portion of the Josephson Junction 546. Therefore, in case the Josephson Junction is a trilayer Junction, the edges 556 of the base electrode layer 556 portion are also aligned with the edges 560 of the top electrode layer 530 portion.

[0138] Both for the bilayer and trilayer junctions, the edges 558 of the tunnel barrier layer and the edges 556 of the base electrode layer are exposed to a gas or a vacuum. In other words, the edges 558 of the tunnel barrier layer and the edges 556 of the base electrode layer are not surrounded by any solid dielectric material, which is advantageous in that eliminating such dielectric material around the Josephson Junction 546 reduces potential sources of spurious TLS's, as described above. In case the Josephson Junction is a trilayer Junction, as is shown in FIG. 5J, the edges 560 of the top electrode layer 530 portion are also exposed to a gas or a vacuum, i.e. not surrounded by any solid dielectric material.

[0139] The interconnect portion 548 together with the top SC wire bridge structure 540 formed in the top SC wire layer 534 form an interconnect for providing electrical interconnection between the top electrode layer of the Josephson Junction (which could be the top electrode layer 530 in case of a trilayer JJ or which could be a portion of the top SC wire layer 534 itself in case of a bilayer JJ) and further components of a quantum circuit, such as e.g. a SQUID loop or a capacitor of a

superconducting qubit. [0140] As shown in FIG. 5J, the interconnect portion 548 is substantially perpendicular to the substrate 552, both for the bilayer and the trilayer architectures.

[0141] For a bilayer JJ, the interconnect portion 548 is substantially parallel to a stack of a portion 562 of the base electrode layer 526 and a portion 564 of the tunnel barrier layer 528 of the

Josephson Junction 546. In particular, the interconnect portion 548 includes a portion 568 of the base conductive layer 526 in a single plane with the portion 556 of the base electrode layer of the Josephson Junction 546 and a portion 570 of the dielectric tunnel barrier layer 530 in a single plane with the portion 558 of the tunnel barrier layer of the Josephson Junction 546. For a bilayer JJ, the top SC wire bridge structure 540 formed in the top SC wire layer 534 may be considered to be a second portion of the interconnect, which portion is provided in a plane substantially parallel to a plane of the substrate 522, and which portion acts as the top electrode of the Josephson Junction 546.

[0142] For a trilayer JJ, the interconnect portion 548 is substantially parallel to a stack of the portion 562 of the base electrode layer 526, the portion 564 of the tunnel barrier layer 528, and a portion 566 of the top electrode layer 530 of the Josephson Junction 546. In particular, the interconnect portion 548 includes the portion 568 of the base conductive layer 526 in a single plane with the portion 562 of the base electrode layer of the Josephson Junction 546, the portion 570 of the dielectric tunnel barrier layer 530 in a single plane with the portion 564 of the tunnel barrier layer of the Josephson Junction 546, and a portion 572 of the top conductive layer 530 in a single plane with the portion 566 of the top electrode layer of the Josephson Junction 546. For a trilayer JJ, the top SC wire bridge structure 540 formed in the top SC wire layer 534 may be considered to be a second portion of the interconnect, which portion is provided in a plane substantially parallel to a plane of the substrate 522, and which portion is in electrical contact with the top electrode of the Josephson Junction 546.

[0143] It should be noted that, as can be seen in FIG. 5J, as a result of carrying out the fabrication method as described above, the interconnect portion 548 also includes a stack of layers formed as a junction of the base electrode layer 526, the tunnel barrier layer 528, and the top electrode layer (which could be the layer 530 for the trilayer architecture or the layer 534 for the bilayer architecture), similar to the layers of the Josephson Junction 546. However, because the dimensions of the interconnect portion 548 are of much larger dimensions than the Josephson Junction 546, e.g. measured several thousands of nm in the x-direction and hundreds of nm or more in the y-direction, the interconnect portion 548 is essentially infinite for the Josephson effect to take place and, therefore, acts as a superconductor rather than a Josephson Junction. That is why the interconnect portion 548 may serve as an interconnect configured to support provision of current to the Josephson Junction 546. This also defines the size of the top SC wire bridge structure 540 formed in the top SC wire layer 534 and explains the asymmetry in the top SC wire bridge structure 540 having a larger part on the side 554 of the interconnect than on the side 552 of the Josephson Junction.

[0144] FIG. 6 provides a flow chart of an exemplary method 600 for fabricating an hBN Josephson Junction using Damascene fabrication, according to some embodiments of the present disclosure. The exemplary method 600 is referred to as a "Damascene fabrication" approach to reflect the fact that it involves an additive process for creating features, as opposed to subtractive patterning (e.g. as described with reference to FIG. 4 and FIGS. 5A-5J). Besides the advantages allowed due to the use of hBN as a tunnel barrier in Josephson Junctions (e.g. less pinholes and defects and greater control over tunnel barrier thickness), the Damascene fabrication approach of the method 600 may improve on some other challenges of existing Josephson Junction fabrication approaches described above. For one, the Damascene fabrication process described herein is manufacturable. In addition, employing such a fabrication process allows encapsulating some of the defects in areas that are further from Josephson Junctions compared to Junctions fabricated using the double-angle shadow evaporation approach, thus reducing the amount of spurious TLS's in the vicinity of Josephson Junctions. Still further, using the Damascene fabrication process as described herein advantageously extends the arsenal of superconducting materials that may be employed as base and top electrodes of Josephson Junctions to include those besides aluminum.

[0145] FIGS. 7A-7G provide a schematic illustration of fabricating an hBN Josephson Junction according to the exemplary Damascene fabrication method 600 shown in FIG. 6, according to some embodiments of the present disclosure. A legend provided within a dashed box at the bottom of FIGS. 7A-7G illustrates patterns used to indicate different elements shown in FIGS. 7A-7G, so that the FIGs are not cluttered by many reference numerals. FIGS. 7A-7G correspond to and are described with reference to processes shown in the flow chart of the method 600 of FIG. 6. In particular, FIGS. 7A-7G illustrate a sequence of structures 702, 704, 706, 708, and so on until structure 714, each of which illustrates an exemplary result of a corresponding one of different subsequent fabrication processes 602, 604, 606, 608, and so on until process 614 shown in FIG. 6. Thus, each structure 7XX corresponds to a respective process box 6XX of the method 600, e.g. a structure 702 illustrates an exemplary result of a fabrication process 602, a structure 704 illustrates an exemplary result of a fabrication process 604, a structure 706 illustrates an exemplary result of a fabrication process 606, and so on. Each of FIGS. 7A-7G provides a cross-sectional view with a cross-section of the structures taken along a y-z plane, similar to the cross-sectional views on the left side of each of FIGS. 5A-5I.

[0146] FIG. 6 and FIGS. 7A-7G covering the Damascene fabrication have some similarities to FIG. 4 and FIGS. 5A-5J covering the partially subtractive fabrication. For example, some similar reference numerals refer to analogous elements, or discussions provided above with reference to trilayer and bilayer Josepshon Junctions of FIG. 4 and FIGS. 5A-5J are also applicable to the Damascene fabrication shown in FIG. 6 and FIGS. 7A-7G, including that FIGS. 7A-7G illustrate examples of a trilayer Josephson Junction while the method 600 is applicable to both the trilayer and the bilayer architectures. In the interests of brevity, in the below detailed description of FIG. 6 and FIGS. 7A-7G, earlier discussions indicated to be applicable to FIG. 6 and FIGS. 7A-7G are not repeated in detail.

[0147] Although the operations discussed below with reference to the method 600 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 600 may be illustrated with reference to one or more of the embodiments discussed above, but the method 600 may be used to manufacture any suitable quantum circuit element comprising one or more Josephson Junctions according to any

embodiments disclosed herein.

[0148] The method 600 may begin with providing a patterned base SC wire layer 724 over a substrate 722 (process 602 in FIG. 6, result of which is illustrated with a structure 702 of FIG. 7A). In FIG. 7A, reference numerals 736 indicate different portions/patterns of the patterned base SC layer 724. Some portions of the patterned base SC wire layer 724 may later be used for e.g. resonators. Other portions will form one or more base wireup superconductors for providing electrical connectivity to base electrodes of Josephson Junctions.

[0149] Discussions provided above with reference to the substrate 522, including optional cleaning thereof prior to providing any structures thereon, are applicable to the substrate 722. Furthermore, discussions provided above with reference to the base SC wire 524, including the materials which could be used to form this element, are applicable to the base SC wire layer 724 except that the latter is shown to be already patterned into patterns 736 prior to deposition of the stack of layers forming a future Josephson Junction. In various embodiments, any kind of photoresist patterning techniques as known in the art may be used for creating the patterned base SC wire layer 724 as shown in FIG. 7A.

[0150] Once the patterned base SC wire layer 724 is formed, dielectric 725 is deposited over the patterned base SC wire layer (process 604 in FIG. 6, result of which is illustrated with a structure 704 of FIG. 7B). Since this dielectric surrounds the patterns of the base SC wire layer, it is referred to herein as a "surrounding dielectric" in order to differentiate it from the dielectric material hBN which will form the tunnel barrier of the Josephson Junction fabricated by the method 600.

[0151] Since the surrounding dielectric 725 will need to later be etched to form a via opening, etching properties of potential candidate materials are to be considered when selecting a suitable material to be used as the surrounding dielectric 725. Besides appropriate etching characteristics, some other considerations in selecting a suitable material may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability). Examples of dielectric materials that may be used as the surrounding dielectric 725 include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

[0152] In some embodiments, the surrounding dielectric 725 may be provided as an oxide deposited over the patterned base SC wire layer 724 using e.g. chemical vapor deposition, spin-on, or atomic layer deposition techniques as known in the art. In some embodiments, the surrounding dielectric 725 may include a dielectric material formed by coating techniques involving cross-linking of liquid precursors into solid dielectric materials.

[0153] Next, the surrounding dielectric 725 is etched to form at least one first via opening 738, defining a location of the future Josephson Junction (process 606 in FIG. 6, result of which is illustrated with a structure 706 of FIG. 7C). To that end, a patterning technique such as e.g.

described above may be used in order to define location of the first via opening(s) in the surrounding dielectric layer 725. In particular, the first via opening is to be formed over one portion of the patterned base SC wire layer 724 (in FIG. 7C - over the middle portion out of the three portions 736 of the patterned base SC wire layer 724 shown), with the via opening extending all the way to and exposing the patterned base SC wire layer 724.

[0154] As a part of the process 606, once an appropriate mask has been provided, e.g. a photoresist mask, defining the location of the future first via opening 738 by exposing a portion of the surrounding dielectric 725 where the first via opening 738 should begin, the exposed portion of the surrounding dielectric 725 is then chemically etched, where the exposed portions of the surface are removed until a desired depth is achieved, forming an opening (or multiple such openings) in the surrounding dielectric 725. In this manner, a first via opening 738 may be formed that is e.g. about 20 nm in the dimensions in the x-y plane shown in FIGS. 7A-7G and has a depth (i.e. dimension in the z-axis) of 50 nm or greater, possibly much greater. In principle, any dimensions are possible and are within the scope of the present disclosure. The remaining photoresist may then be removed, e.g. using the ashing process as known in the art.

[0155] Next, a stack of a JJ base SC and a JJ tunnel barrier material is formed within the first via opening (process 608 in FIG. 6, result of which is illustrated with a structure 708 of FIG. 7D). In case a hBN Josephson Junction being fabricated is a trilayer junction, the stack formed within the first via opening 738 includes three layers: a base electrode layer 726 (indicated in FIG. 6 as a "JJ base SC") for forming the base electrode of the Junction, a top superconductor layer 730 (not indicated in FIG. 6 because FIG. 6 is general enough to also be applicable to bilayer JJs) for forming the top electrode of the Junction, and a tunnel barrier layer 728 (indicated in FIG. 6 as a "hBN tunnel barrier") provided between the base electrode layer 726 and the top electrode layer 730.

[0156] Discussions provided above with reference to providing the base electrode layer 526, the hBN tunnel barrier 528, and the top electrode layer 530 are applicable to depositing the base electrode layer 726, the hBN tunnel barrier 728, and the top electrode layer 730 into the first via opening 738. In some embodiments, employing atomic level growth to form the base electrode layer 726 and the top electrode layer 730, e.g. epitaxial growth, may be particularly advantageous as it could allow providing controlled layers (e.g. with tightly controlled thicknesses) of specific materials that do not intermix. Another advantage of atomic level growth is that it allows forming Josephson Junctions using refractory or noble metals as base and top electrodes 726 and 730.

[0157] In general, any suitable superconducting materials that may be grown using atomic level growth, such as e.g. Nb, NbN, NbTiN, TiN, MoRe, may be used for base and/or top JJ electrodes 726, 730 of the Damascene fabrication of the method 600. One advantage of having an increased arsenal of superconducting materials to choose from for the base and top electrodes of a Josephson Junction is that it give the possibility to form electrodes of Josephson Junctions from the same material as one or more interconnects providing electrical connections to these electrodes. This was not possible before when the double-angle shadow evaporation method of forming Josephson Junctions was used because only aluminum could be deposited using that method.

[0158] Yet another advantage of atomic level growth is that forming the barrier dielectric in this manner provides an improved control over trap states and thus, may reduce the total amount of spurious TLS's present in a Josephson Junction and improve on the problem of qubits' decoherence.

[0159] The Damascene fabrication process as described above also provides another measure for improving on the problem of qubits' decoherence: the JJ base SC 726 may be grown very thin, less than 5 nm thick, preferably between 2 and 3 nm thick, providing a fresh in-situ surface for the Josephson Junction and encapsulating any defects between the patterned base SC wire layer 724 and the base electrode superconductor. Thickness of the top electrode JJ top SC 730 may be between e.g. 10 and 300 nm, e.g. between 40 and 100 nm.

[0160] In case the Josephson Junction being fabricated in the method 600 is a bilayer junction, the stack of various layers provided in the first via opening 738 in process 608 would include two of the three layers described above for the trilayer architecture, with the missing layer being the top superconductor layer 730. The stack of layers provided in the first via opening form a Josephson Junction 740, as labeled in FIG. 7D.

[0161] After the process 608, the method 600 may then proceed with planarizing/polishing the wafer down to the surface of the surrounding dielectric 725 to provide a flat surface (process 610 in FIG. 6, result of which is illustrated with a structure 710 of FIG. 7E). FIG. 7E illustrates that the structure 710 has a flat surface such that a top surface 742 of the top electrode of the Josephson Junction 740 is aligned with a top surface 744 of the surrounding dielectric 725. In various embodiments, such polishing may be carried out using any of the known planarization techniques as known in the art, e.g. using either wet or dry planarization processes. In one embodiment, planarization is performed using chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface of the top electrode of the Josephson Junction 740 and the surrounding dielectric 725.

[0162] Processes 612 and 614 of the method 600, results of which are illustrated with structures 712 and 714 of FIGS. 7F and 7G, illustrate optional formation of an interconnect configured to provide electrical interconnection between the top electrode of the Josephson Junction 740 and a further component of the quantum circuit.

[0163] FIG. 7F illustrates that, in the process 612, a via opening 746 may be formed for providing an electrical connection to a certain quantum circuit component, such as e.g. a SQUID loop or a capacitor in case the qubit is a transmon. The via opening 746 may be formed using patterning and etching techniques similar to those described above for the formation of the via opening 738. A top SC wire layer 734 may then be deposited and patterned to the desired shape and form, in the process 614, as shown in FIG. 7G. To that end, deposition and patterning techniques similar to those described above may be used. In various embodiments, the top wire layer 734 may be formed from any of the superconducting materials described above. Such a top wire layer 734 forms one of the interconnects of the quantum circuit by providing electrical interconnection between the top electrode and a further component of the quantum circuit. Discussions provided above with reference to the top SC wire material 534 are applicable to depositing the top SC wire material 734.

[0164] While FIGS. 5A-5J and FIGS. 7A-7G show features drawn with precise right angles and straight lines, this is not necessarily how features would look in real life.

[0165] FIGS. 8A and 8B provide schematic illustrations of cross-sectional structures 800A and 800B comprising, respectively, a Josephson Junction 546 fabricated using the partially subtractive fabrication method described with reference to FIG. 4 and FIGS. 5A-5J and a Josephson Junction 740 fabricated using the Damascene fabrication method described with reference to FIG. 6 and FIGS. 7A- 7G, according to some embodiments of the present disclosure. As can be seen, FIGS. 8A and 8B are drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines. As shown, FIG. 8A represents a cross-section view similar to that shown in FIG. 5J and FIG. 8B represents a cross-section view similar to that shown in FIG. 7E, but now with real world process limitations shown explicitly, as could be visible in e.g. a scanning electron microscopy (SEM) image or a transmission electron microscope (TEM) image of structures. In such images of real structures, possible processing defects could also be visible. FIG. 8A uses the same reference numerals as those labeled in FIG. 5J to illustrate element analogous to those shown in FIG. 5J and FIG. 8B uses the same reference numerals as those labeled in FIG. 7E to illustrate element analogous to those shown in FIG. 7E.

[0166] The hBN tunnel barriers of any of the Josephson Junctions described herein can be detected by cross-sectional TEM (as e.g. shown with FIGS. 8A and 8B), possibly in conjunction with Raman spectroscopy. A TEM can be used to determine the number of hBN layers in the tunnel barrier of a Josephson Junction by simply counting the atomic layers between the base and top JJ electrodes, where the different atomic layers of hBN will be clearly distinguishable from the surrounding metal electrodes of the Josephson Junction.

[0167] Raman spectroscopy can be used to unambiguously determine the presence of hBN, as opposed to some other 2D material. As is well known, Raman spectroscopy refers to

a spectroscopic technique used to observe vibrational, rotational, and other low-frequency modes in a system, and is commonly used to provide a fingerprint by which molecules can be identified.

[0168] While hBN Josephson Junctions have been described with reference to conducting or superconducting materials to form base and top electrodes, in other embodiments, hBN Josephson Junctions as described herein may include base and/or top electrodes which include refractory and/or from noble metals, both in their single element form as well as their nitrodes or carbides. Examples of such materials include TiN, NbTiN, ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au). In general, the term "refractory metal" refers to metals that exhibit resistance to changing under high temperatures, while the term "noble metal" refers to metals that do not easily oxidize or corrode. There is a large overlap between refractory and noble metals in the periodic table of elements, i.e. some metals are both noble and refractory.

[0169] In various embodiments, Josephson Junctions as described herein, e.g. the hBN Josephson Junction 546, could be a part of a superconducting qubit, e.g. a part of a charge qubit, in particular a part of a transmon, or a part of a flux qubit. In other embodiments, hBN Josephson Junction 546 may be used in quantum circuits implementing qubits other than superconducting qubits as well as in non-quantum circuit components such as e.g. RSFQ log, low voltage RSFQ, and RQL.

[0170] FIGS. 9A-9B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure. The dies 1102 may include any of the quantum circuits/devices disclosed herein, e.g., the quantum circuit 100, and may include any of the hBN Josephson Junctions described herein, or any combinations of these Junctions. The wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device. After the fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product. A die 1102 may include one or more quantum circuits 100 and/or supporting circuitry to route electrical signals to the quantum circuits 100 (e.g., interconnects connected to the conductive contacts of the quantum circuits described herein, and other conductive vias and lines), as well as any other IC components. In some embodiments, the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0171] FIG. 10 is a cross-sectional side view of a device assembly 1300 that may include any of the embodiments of the quantum circuits employing hBN Josephson Junctions disclosed herein. The device assembly 1300 includes a number of components disposed on a circuit board 1302. The device assembly 1300 may include components disposed on a first face 1340 of the circuit board 1302 and an opposing second face 1342 of the circuit board 1302; generally, components may be disposed on one or both faces 1340 and 1342.

[0172] In some embodiments, the circuit board 1302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1302. In other embodiments, the circuit board 1302 may be a package substrate or flexible board. [0173] The IC device assembly 1300 illustrated in FIG. 10 includes a package-on-interposer structure 1336 coupled to the first face 1340 of the circuit board 1302 by coupling components 1316. The coupling components 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302, and may include solder balls (as shown in FIG. 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0174] The package-on-interposer structure 1336 may include a package 1320 coupled to an interposer 1304 by coupling components 1318. The coupling components 1318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1316. Although a single package 1320 is shown in FIG. 10, multiple packages may be coupled to the interposer 1304; indeed, additional interposers may be coupled to the interposer 1304. The interposer 1304 may provide an intervening substrate used to bridge the circuit board 1302 and the package 1320. The package 1320 may be a quantum circuit device package as described herein, e.g. a package including the quantum circuit 100 with any of the hBN Josephson Junctions described herein, or a combination thereof, or may be a conventional IC package, for example. Generally, the interposer 1304 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1304 may couple the package 1320 (e.g., a die) to a ball grid array (BGA) of the coupling components 1316 for coupling to the circuit board 1302. In the embodiment illustrated in FIG. 10, the package 1320 and the circuit board 1302 are attached to opposing sides of the interposer 1304; in other embodiments, the package 1320 and the circuit board 1302 may be attached to a same side of the interposer 1304. In some embodiments, three or more components may be interconnected by way of the interposer 1304.

[0175] The interposer 1304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1306. The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1304. The package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art.

[0176] The device assembly 1300 may include a package 1324 coupled to the first face 1340 of the circuit board 1302 by coupling components 1322. The coupling components 1322 may take the form of any of the embodiments discussed above with reference to the coupling components 1316, and the package 1324 may take the form of any of the embodiments discussed above with reference to the package 1320. The package 1324 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional IC package, for example. In some embodiments, the package 1324 may take the form of any of the embodiments of the quantum circuit 100 with any of the hBN Josephson Junctions described herein.

[0177] The device assembly 1300 illustrated in FIG. 10 includes a package-on-package structure 1334 coupled to the second face 1342 of the circuit board 1302 by coupling components 1328. The package-on-package structure 1334 may include a package 1326 and a package 1332 coupled together by coupling components 1330 such that the package 1326 is disposed between the circuit board 1302 and the package 1332. The coupling components 1328 and 1330 may take the form of any of the embodiments of the coupling components 1316 discussed above, and the packages 1326 and 1332 may take the form of any of the embodiments of the package 1320 discussed above. Each of the packages 1326 and 1332 may be a qubit device package as described herein or may be a conventional IC package, for example. In some embodiments, one or both of the packages 1326 and 1332 may take the form of any of the embodiments of the quantum circuit 100 with any of the hBN Josephson Junctions described herein, or a combination thereof.

[0178] FIG. 11 is a block diagram of an example quantum computing device 2000 that may include any of the quantum circuits with hBN Josephson Junctions disclosed herein. A number of components are illustrated in FIG. 11 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with hBN Josephson Junctions described herein. In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 11, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.

[0179] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum circuits 100 with hBN Josephson Junctions disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read. The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to- digital converters.

[0180] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0181] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0182] The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0183] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0184] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless

communications (such as AM or FM radio transmissions).

[0185] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0186] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0187] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0188] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0189] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0190] The quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0191] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0192] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0193] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0194] The following paragraphs provide examples of various ones of the embodiments disclosed herein.

[0195] Example 1 provides a qubit device, including a substrate and a plurality of qubits, e.g.

superconducting qubits, on the substrate. Each qubit includes at least one Josephson Junction including a base electrode layer, a top electrode layer, and a tunnel barrier layer provided between the base electrode layer and the top electrode layer, where the tunnel barrier layer includes a hexagonal boron nitride (hBN).

[0196] Example 2 provides the qubit device according to Example 1, where a thickness of the hBN is between 0.2 and 5 nanometers.

[0197] Example 3 provides the qubit device according to Examples 1 or 2, where the at least one Josephson Junction does not include graphene.

[0198] Example 4 provides the qubit device according to any one of the preceding Examples, where the each qubit includes two Josephson Junctions included within a superconducting quantum interference device (SQUID) loop.

[0199] Example 5 provides the qubit device according to Example 4, further including a flux bias line associated with the SQUID loop.

[0200] Example 6 provides the qubit device according to any one of the preceding Examples, where each of the base electrode layer and the top electrode layer includes one or more superconductive materials.

[0201] Example 7 provides the qubit device according to Example 6, where the one or more superconductive materials include one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), or niobium titanium nitride (NbTiN).

[0202] Example 8 provides the qubit device according to any of Examples 1-5, where each of the base electrode layer and the top electrode layer includes one or more refractory and/or noble metals.

[0203] Example 9 provides the qubit device according to Example 8, where the one or more refractory and/or noble metals include one or more of ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), Zirconium (Zr), Hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), Chromium (Cr), Molybdenum (Mo), tungsten (W), or/and nitrides and/or carbides of the refractory and/or noble metals.

[0204] Example 10 provides the qubit device according to any of Examples 1-9, where the plurality of qubits include transmon qubits.

[0205] Example 11 provides the qubit device according to any of Examples 1-9, where the plurality of qubits include charge qubits.

[0206] Example 12 provides the qubit device according to any of Examples 1-9, where the plurality of qubits include flux qubits.

[0207] Example 13 provides the qubit device according to any one of the preceding Examples, where the base electrode layer has a thickness less than 10 nanometers. [0208] Example 14 provides the qubit device according to any one of the preceding Examples, where the base electrode layer has a thickness less than 5 nanometers.

[0209] Example 15 provides the qubit device according to Examples 13 or 14, where the Josephson Junction is in an opening provided over the substrate and the opening is surrounded by a dielectric.

[0210] Example 16 provides the qubit device according to Example 15, where an upper surface of the dielectric is aligned with an upper surface of the top electrode layer.

[0211] Example 17 provides the qubit device according to Example 15, where the opening is substantially perpendicular to the substrate.

[0212] Example 18 provides the qubit device according to any one of Examples 13-17, where the base electrode layer is provided on a patterned superconductor layer provided over the substrate, and where dimensions of the base electrode layer in a plane of the base electrode layer and the patterned superconductor layer are smaller than dimensions of the patterned superconductor layer.

[0213] Example 19 provides a method of manufacturing a qubit device. The method includes providing a base electrode layer on a substrate; providing a tunnel barrier layer over the base electrode layer, where the tunnel barrier layer includes a hexagonal boron nitride (hBN); providing a top electrode layer over the tunnel barrier layer; and providing a plurality of qubits on the substrate.

[0214] Example 20 provides the method according to Example 19, where providing the tunnel barrier layer includes directly growing the hBN on the base electrode layer.

[0215] Example 21 provides the method according to Example 19, where said substrate is a first substrate and where providing the tunnel barrier layer includes growing the hBN on a second substrate and transferring the hBN from the second substrate to the base electrode layer on the first substrate.

[0216] Example 22 provides a quantum circuit component including a substrate and a Josephson Junction on the substrate. The Josephson Junction includes a base electrode layer, a top electrode layer, and a tunnel barrier layer between the base electrode layer and the top electrode layer. Edges of the tunnel barrier layer are aligned with edges of the base electrode layer and the tunnel barrier layer includes a hexagonal boron nitride (hBN).

[0217] Example 23 provides the quantum circuit component according to Example 22, where the edges of the tunnel barrier layer and the edges of the base electrode layer are exposed to a gas or a vacuum.

[0218] Example 24 provides the quantum circuit component according to Example 22, further including an interconnect configured to provide electrical interconnection between the top electrode layer and a further component of the quantum circuit. [0219] Example 25 provides the quantum circuit component according to Example 24, where the further component of the quantum circuit includes a superconducting quantum interference device (SQUID).

[0220] Example 26 provides the quantum circuit component according to Example 24, where the further component of the quantum circuit includes a capacitor of a qubit.

[0221] Example 27 provides the quantum circuit component according to any one of Examples 24- 26, where the interconnect includes a first portion substantially perpendicular to the substrate and separated from the Josephson Junction by a gap.

[0222] Example 28 provides the quantum circuit component according to Example 27, where a width (d) of the gap is between 10 and 500 nanometers.

[0223] Example 29 provides the quantum circuit component according to Example 27, where the first portion is substantially parallel to a stack of the base electrode layer and the tunnel barrier layer of the Josephson Junction.

[0224] Example 30 provides the quantum circuit component according to Example 27, where the first portion includes a base conductive layer in a single plane with the base electrode layer of the Josephson Junction and a dielectric layer in a single plane with the tunnel barrier layer of the Josephson Junction.

[0225] Example 31 provides the quantum circuit component according to any one of Examples 24- 26, where the interconnect includes a second portion in a plane substantially parallel to a plane of the substrate, and where the second portion includes the top electrode of the Josephson Junction.

[0226] Example 32 provides the quantum circuit component according to any one of Examples 22- 31, where each of the base electrode layer and the top electrode layer includes one or more superconductive materials.

[0227] Example 33 provides the quantum circuit component according to Example 32, where the one or more superconductive materials include one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TIN), or niobium titanium nitride (NbTiN).

[0228] Example 34 provides the quantum circuit component according to any of Examples 22-31, where each of the base electrode layer and the top electrode layer includes one or more refractory and/or noble metals.

[0229] Example 35 provides the quantum circuit component according to Example 24, where the one or more refractory and/or noble metals include one or more of ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), Zirconium (Zr), Hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), Chromium (Cr), Molybdenum (Mo), tungsten (W), or/and nitrides and/or carbides of the refractory and/or noble metals.

[0230] Example 36 provides a method for fabricating at least a Josephson Junction of a quantum circuit component. The method includes providing, over a substrate, a stack of a base wire layer, a junction base layer, and a junction tunnel barrier layer, where the junction tunnel barrier layer includes a hexagonal boron nitride (hBN); providing an opening through the stack; filling the opening with a sacrificial material; providing a top wire layer over the stack and the sacrificial material in the opening; patterning the top wire layer to form a bridge over the opening and a window over the opening, the window configured to allow removal of the sacrificial material under the bridge;

patterning the stack to form the Josephson Junction and an interconnect portion, the Josephson Junction and the interconnect portion separated from one another by the opening and electrically connected by the bridge; further patterning the stack to electrically isolate the Josephson Junction from the interconnect portion except for the electrical connection by the bridge; and removing the sacrificial material through the window to provide a gap between at least a portion of the Josephson Junction and the interconnect portion.

[0231] Example 37 provides the method according to Example 36, where filling the opening with the sacrificial material includes depositing a layer of the sacrificial material over the stack with the opening and polishing the layer of the sacrificial material until an upper surface of the sacrificial material in the opening is aligned with an upper surface of the stack.

[0232] Example 38 provides the method according to Example 36, where patterning the stack to form the Josephson Junction includes patterning the junction base layer to form a base electrode layer of the Josephson Junction and patterning the junction tunnel barrier layer to form a tunnel barrier layer of the Josephson Junction.

[0233] Example 39 provides the method according to any one of Examples 36-38, where the stack further includes a junction top layer, and where patterning the stack to form the Josephson Junction includes patterning the junction top layer to form a top electrode layer of the Josephson Junction.

[0234] Example 40 provides the method according to any one of Examples 36-39, where removing the sacrificial material includes performing an isotropic etch of the sacrificial material.

[0235] Example 41 provides the method according to any one of Examples 36-40, where a width of the gap is between 10 and 500 nanometers.

[0236] Example 42 provides a method for fabricating at least a Josephson Junction of a qubit, the method including providing a patterned superconductor layer over a substrate; providing a layer of surrounding dielectric over the patterned superconductor layer; providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer; depositing a first layer of superconductor in the via opening to form a base electrode of the Josephson Junction; providing a layer of barrier dielectric in the via opening, on the first layer of superconductor in the via opening, to form a tunnel barrier layer of the Josephson Junction, where the layer of barrier dielectric includes a hexagonal boron nitride (hBN); and depositing a second layer of superconductor in the via opening, on the layer of barrier dielectric in the via opening, to form a top electrode of the Josephson Junction.

[0237] Example 43 provides the method according to Example 42, where a thickness of the first layer of superconductor is less than 5 nm.

[0238] Example 44 provides the method according to Example 42, further including polishing the second layer of superconductor until an upper surface of the second layer of superconductor is aligned with an upper surface of the layer of surrounding dielectric.

[0239] Example 45 provides the method according to any one of Examples 42-44, further including providing a further via opening in the layer of surrounding dielectric over a second portion of the patterned superconductor layer, the second portion being electrically disconnected from the first portion; and depositing a wireup superconductor in the further via opening and over the second layer of superconductor in the via opening.

[0240] Example 46 provides the method according to Example 45, patterning the wireup superconductor to form an interconnect configured to provide electrical interconnection between the top electrode and the second portion of the patterned superconductor layer.

[0241] Example 47 provides the method according to Example 45, where the further via opening is provided after the top electrode of the Josephson Junction is formed.

[0242] Example 48 provides the method according to any one of Examples 42-47, where depositing the first layer of superconductor and/or the first layer of superconductor includes deposition by atomic level growth.

[0243] Example 49 provides a quantum computing device, including a quantum processing device, where the quantum processing device includes the qubit device according to any one of Examples 1- 18 or the quantum circuit component according to any one of Examples 22-35; a non-quantum processing device coupled to the quantum processing device; and a memory device to store data generated by the plurality of qubits during operation of the quantum processing device.

[0244] Example 50 provides the quantum computing device according to Example 49, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin. [0245] Example 51 provides the quantum computing device according to Examples 49 or 50, where the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0246] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0247] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.