CROSS-REFERENCE TO RELATED APPLICATION

[001] The present application claims filing benefit of United States Provisional Patent Application Serial No. 63/295,070 having a filing date of December 30, 2021 and which is incorporated herein by reference in its entirety.

BACKGROUND OF THE SUBJECT MATTER

[002] Multilayer coupling capacitors are generally constructed having a plurality of dielectric layers and internal electrode layers arranged in a stack. During manufacture, the stacked dielectric layers and internal electrode layers are pressed and sintered to achieve a substantially unitary capacitor body. In an attempt to improve upon the performance of these capacitors, various configurations and designs have been employed for the dielectric layers and the internal electrode layers.

[003] However, as rapid changes occur in the electronics industry requiring new performance criteria, these configurations are commonly manipulated. In particular, various application design considerations have created a need to redefine the capacitor parameters and its performance in high-speed environments, especially in light of faster and denser integrated circuits. For instance, larger currents, denser circuit boards and spiraling costs have all served to focus upon the need for better and more efficient capacitors. Additionally, the design of various electronic components has been driven by a general industry trend toward miniaturization, as well as increased functionality.

[004] In such regard, a need exists for providing a ceramic capacitor with improved operational characteristics. Additionally, some applications would also benefit from providing a coupling capacitor that may have a smaller footprint on a circuit board.

SUMMARY OF THE SUBJECT MATTER

[005] In accordance with one embodiment of the present invention, a surface mount coupling capacitor is disclosed. The coupling capacitor comprises a main body containing a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set of alternating dielectric layers and internal electrode layers contains a first internal electrode layer and a second internal electrode layer. Each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer. The coupling capacitor includes external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the coupling capacitor and a bottom surface of the coupling capacitor opposing the top surface of the coupling capacitor. The capacitor includes one or more dielectric regions including one or more air voids.

[006] Other features and aspects of the present invention are set forth in greater detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

[007] A full and enabling disclosure of the present invention, including the best mode thereof to one skilled in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying figures, in which:

[008] Figure 1 A illustrates a generally top and sides external perspective view of one embodiment of a 1 by 2 package coupling capacitor in accordance with the present invention;

[009] Figure 1 B illustrates a side external perspective view of the coupling capacitor of Figure 1 A;

[0010] Figure 1 C illustrates a front external perspective view of the coupling capacitor of Figures 1 A and 1 B;

[0011] Figure 2 illustrates side view of a circuit board and integrated circuit package containing a packaged coupling capacitor of the present invention; and [0012] Figure 3 illustrates a side view of a circuit board and integrated circuit package containing a coupling capacitor of the prior art. DETAILED DESCRIPTION OF THE SUBJECT MATTER

[0013] It is to be understood by one of ordinary skill in the art that the present discussion is a description of exemplary embodiments only, and is not intended as limiting the broader aspects of the present invention.

[0014] Generally speaking, the present invention is directed to a surface mount multilayer coupling capacitor, for example for mounting onto a circuit board. The surface mount multilayer coupling capacitor contains a plurality of capacitive elements within a main body. That is, the multilayer coupling capacitor contains the plurality of capacitive elements within a single, unitary package. In this regard, the multilayer coupling capacitor contains a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set of alternating dielectric layers and internal electrode layers defines a capacitive element. The capacitor also includes dielectric regions including air voids.

[0015] The particular arrangement of the capacitive elements within a single, unitary package (i.e., single body) and the inclusion of air voids can provide several advantages. For instance, by utilizing air voids as disclosed herein, in particular between external terminals, cross-talk and interference can be minimized and/or eliminated especially when the capacitors are utilized in various electronic devices. In addition, as discussed further below, the coupling capacitor of the present invention may be mounted onto a circuit board as a surface mount capacitor and may provide a smaller footprint on the circuit board. This may in turn also allow for a reduction in size of a circuit board.

[0016] Turning to Figure 2, the coupling capacitors 408 can be mounted (e.g., surface mounted) onto a circuit board 406 that contains a substrate (e.g., insulating layer) having an upper surface and a lower surface. The circuit board 406 has a plurality of electrical current paths (not shown) defined therein. The external terminals of the coupling capacitors 408 are in respective electrical communication with the predetermined current paths of the circuit board 406. In addition, the external terminals of the coupling capacitors 408 can be physically connected to the circuit board 406 using any method generally known in the art, such as general soldering techniques. [0017] As illustrated in Figure 2, an integrated circuit package 402 may also be provided on the circuit board 406. The integrated circuit package 402 may be connected to the circuit board 406 using a ball grid array 404. The circuit board may further comprise a processor 400. The processor 400 may be connected to the integrated circuit package 402 also using a ball grid array 412.

[0018] In general, the ball grid array 404 may be configured to have a certain pitch. As generally known in the art, a pitch refers to a nominal distance between the centers (also referred to as center-to-center spacing). The pitch of the ball grid array 404 and the external terminals of the coupling capacitor 408 may be dictated by the particular circuit board configuration. The pitch between external terminals in one direction (i.e., x or y direction) may be the same as the pitch between adjacent external terminals in the other direction (i.e., y orx direction, respectively). That is, the pitch between any two adjacent external terminals may be substantially the same as the pitch between any other two adjacent external terminals.

[0019] The pitch may be about 0.1 mm or greater, such as about 0.2 mm or greater, such as about 0.3 mm or greater, such as about 0.4 mm or greater, such as about 0.5 mm or greater, such as about 0.6 mm or greater, such as about 0.7 mm or greater, such as about 0.8 mm or greater, such as about 0.9 mm or greater, such as about 1 .0 m or greater. The pitch may be about 2.0 mm or less, such as about 1 .5 mm or less, such as about 1 .4 mm or less, such as about 1 .3 mm or less, such as about 1 .2 mm or less, such as about 1.1 mm or less, such as about 1 .0 mm or less. For instance, the pitch may be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1 .0 mm, about 1 .2 mm, etc. In particular, the pitch may be 0.6 mm, 0.8 mm, or 1 .0 mm. In one embodiment, the pitch may be about 0.6 mm, such as 0.6 mm +/- 10%, such as +/- 5%, such as +/- 2%, such as +/- 1 %. In another embodiment, the pitch may be about 0.8 mm, such as 0.8 mm +/- 10%, such as +/- 5%, such as +/- 2%, such as +/- 1 %. In a further embodiment, the pitch may be about 1 mm, such as 1 mm +/- 10%, such as +/- 5%, such as +/- 2%, such as +/- 1 %.

[0020] In a similar manner, the pitch of the external terminals of the coupling capacitors 408 may also be the same as that of the ball grid array 404. For instance, the external terminals may be provided to make contacts as typically employed by a ball-grid array, in particular a surrounding ball-grid array. In this regard, the pitch of the external terminals may be the same as the pitch of a surrounding ball-grid array. That is, the pitch may be within 10%, such as within 5%, such as within 2%, such as within 1 %, such as within 0.5%, such as within 0.1 % of the pitch of a surrounding ball-grid array.

[0021] In addition, like a ball-grid array, the external terminals may be provided in rows and/or columns. That is, the external terminals may be provided such that they exist in at least one row and at least two columns. For instance, the external terminals may be presented in at least two rows, such as at least three rows, such as at least four rows. In addition, the external terminals may be presented in at least two columns, such as at least three columns, such as at least four columns. The number of rows and columns can be dictated by the number of different sets of alternating dielectric layers and internal electrode layers.

[0022] In addition, the ball grid array 412 will have a pitch as mentioned above regarding ball grid array 404. In one embodiment, the pitch of the ball grid array 412 may be less than the pitch of the ball grid array 404 and the external terminals of the coupling capacitors 408. Some common pitches for the ball grid array 412 include 0.1 mm and 0.2 mm.

[0023] In addition, the integrated circuit package 402 may also be connected to the circuit board 406 using coupling capacitors 408 as defined herein. In this regard, the internal electrode layers of the coupling capacitors 408 may be positioned such that they are orthogonal to a horizontal plane of the circuit board 406 and integrated circuit package 402. In other words, the internal electrode layers of the coupling capacitors 408 may be positioned such that they are substantially nonparallel with the circuit board 406. For instance, the coupling capacitors 408 may be positioned between the integrated circuit package 402 and the circuit board 406 such that the coupling capacitors 408 are “sandwiched” between the two components. In this regard, the coupling capacitors 408 are directly connected to the integrated circuit package 402 and the circuit board 406. For instance, the coupling capacitors 408 can be physically connected to the circuit board 406 and/or circuit package 402 using any method generally known in the art, such as general soldering techniques. [0024] By employing the coupling capacitor in the aforementioned arrangement, the coupling capacitors 408 may allow for removal of some of the original ball grid array 404. However, the coupling capacitors 408 may still be surrounded by a ball grid array 404 as illustrated in Figure 2.

[0025] Meanwhile, a prior art circuit board 506 is illustrated in Figure 3. The circuit board 506 includes a processor 500, an integrated circuit package 502, and ball grid arrays 504 and 512. However, rather than employing a single, unitary capacitor package like coupling capacitors 408 in Figure 2, the circuit board 506 of Figure 3 employs an individual multilayer ceramic capacitor 508. In addition, the multilayer ceramic capacitor 508 is positioned elsewhere on the circuit board 506 and is connected to the processor 500 and the integrated circuit package 502 through vias 514.

[0026] However, for the reasons mentioned herein, the present configuration employing a single, unitary capacitor can allow for various advantages and benefits in comparison to a circuit board that employs individual multilayer ceramic capacitors.

[0027] In general, the coupling capacitors can be employed to allow for an AC signal to pass through or be transmitted while generally blocking a DC signal. That is, it may be employed to block low frequency signals and transmit high frequency signals. In general, the coupling capacitors may have a generally high impedance/resistance at low frequencies that allows for the blocking of the DC signal. In contrast, the coupling capacitors may have a generally low impedance/resistance at high frequencies that allows for the transmission of the AC signal.

[0028] One distinct advantage of the coupling capacitors and configuration of the present invention is that when employed within a circuit board as explained herein, the electrical length from the processor to the coupling capacitor is substantially reduced. For instance, as illustrated in Figure 2, the distance from the processor 400 to the coupling capacitors 408 is substantially less than the distance between the processor 500 and the capacitor 508 in Figure 3. By placing the coupling capacitors in such a manner, it also allows for elimination of the vias 514 as illustrated in Figure 3. In addition, by placing the capacitors in such manner, the capacitor can be within an equalizer window, which is desired to be as low as possible. In this regard, by allowing for the capacitor to be within the window, it can allow for the signal to be cleaned up for transmission.

[0029] In addition, another distinct advantage of the coupling capacitors and configuration of the present invention is the ability to tailor the capacitor in order to obtain an impedance differential of close to 100 Q as possible. In this regard, the impedance differential may be ±25%, such as ±15%, such as ±10%, such as ±5%, such as ±2%, such as ±1 %, such as ±0.5% of 100 Q. It should be understood that the aforementioned 100 Q impedance differential is simply one embodiment of the present invention and that the coupling capacitors can be configured to obtain any desired impedance differential. Such impedance differential can be calculated using any method generally known in the art.

[0030] Further, another distinct advantage of the coupling capacitors and configuration of the present invention is the ability to minimize the insertion loss. Such minimal insertion loss may be attributed to the ability to minimize the impedance differential. In this regard, the insertion loss may be 0.5 dB or less, such as 0.25 dB or less, such as 0.15 dB or less, such as 0.1 dB or less, such as 0.05 dB or less. Such insertion loss can be calculated using any method generally known in the art.

[0031] In addition the capacitance values may not necessarily be limited. For instance, the capacitance of the coupling capacitors may be in the picoFarad or nanoFarad range. In particular, the capacitance may be 1 ,000 pF or less, such as 750 pF or less, such as 500 pF or less, such as 250 pF or less, such as 100 pF or less, such as 50 pF or less, such as 25 pF or less, such as 10 pF or less, such as 5 pF or less, such as 2.5 pF or less, such as 1 pF or less, such as 750 nanoFarad or less, such as 500 nanoFarad or less, such as 250 nanoFarad or less, such as 100 nanoFarad or less. The capacitance may be 1 picoFarad or more, such as 10 picoFarad or more, such as 25 picoFarad or more, such as 50 picoFarad or more, such as 100 picoFarad or more, such as 250 picoFarad or more, such as 500 picoFarad or more, such as 750 picoFarad or more, such as 1 nanoFarad or more, such as 10 nanoFarad or more. The capacitance may be measured using general techniques as known in the art.

[0032] Furthermore, the resistance of the capacitor may not be necessarily limited. For instance, the resistance of the coupling capacitors may be 100 mOhm or less, such as 75 mOhm or less, such as 50 mOhm or less, such as 40 mOhm or less, such as 30 mOhm or less, such as 25 mOhm or less, such as 20 mOhm or less, such as 15 mOhm or less, such as 10 mOhm or less, such as 5 mOhm or less. The resistance may be 0.01 mOhm or more, such as 0.1 mOhm or more, such as 0.25 mOhm or more, such as 0.5 mOhm or more, such as 1 mOhm or more, such as 1 .5 mOhm or more, such as 2 mOhm or more, such as 5 mOhm or more, such as 10 mOhm or more. The resistance may be measured using general techniques as known in the art.

[0033] Additionally, the inductance of the capacitor may not be necessarily limited. For instance, the inductance of the coupling capacitors may be less than 1 nanohenry. In particular, the inductance may be 900 picohenries or less, such as 750 picohenries or less, such as 500 picohenries or less, such as 400 picohenries or less, such as 250 picohenries or less, such as 100 picohenries or less, such as 50 picohenries or less, such as 25 picohenries or less, such as 15 picohenries or less, such as 10 picohenries or less. The inductance may be 1 femtohenry or more, such as 25 femtohenries or more, such as 50 femtohenries or more, such as 100 femtohenries or more, such as 250 femtohenries or more, such as 500 femtohenries or more, such as 750 femtohenries or more.

[0034] The present inventors have discovered that the aforementioned advantages can be obtained by controlling the width of the internal electrode layers. Such control also allows for control of the spacing between the internal electrode layers in the first set and the internal electrode layers in the second set. In this regard, the shape of the internal electrode layers is not necessarily limited by the present invention so long as the specific operational characteristics and properties can be achieved. In one embodiment, the coupling capacitor may have a certain internal electrode layer width to spacing ratio. In general, the spacing is referred to as the spacing “s” as illustrated in Figure 1C between the lateral edges of the internal electrode layers of the first set and the second set.

[0035] As indicated above, the present invention includes a multilayer coupling capacitor that contains a plurality of capacitive elements within a single, unitary package. The capacitor includes a top surface and a bottom surface opposite the top surface. The capacitor also includes at least one side surface that extends between the top surface and the bottom surface. The capacitor may include at least three side surfaces, such as at least four side surfaces. In one embodiment, the capacitor includes at least six total surfaces (e.g., one top, one bottom, four sides). For instance, the capacitor may have a parallelepiped shape, such as a rectangular parallelepiped shape.

[0036] In addition, the capacitor may have a desired height. For instance, the height may be 10 microns or more, such as 25 microns or more, such as 50 microns or more, such as 100 microns or more, such as 200 microns or more, such as 250 microns or more, such as 300 microns or more, such as 350 microns or more, such as 500 microns or more, such as 1 ,000 microns or more, such as 2,000 microns or more. The height may be 5,000 microns or less, such as 4,000 microns or less, such as 2,500 microns or less, such as 2,000 microns or less, such as 1 ,000 microns or less, such as 750 microns or less, such as 500 microns or less, such as 450 microns or less. When surrounded by a ball grid array, the height of the capacitor may be within 10%, such as within 7%, such as within 5%, such as within 3%, such as within 2%, such as within 1 % the height (or diameter) of the balls of the ball grid array. For instance, such height may be the original height prior to any reflow.

[0037] In one embodiment, the height of the capacitor may be 10% or more, such as 20% or more, such as 30% or more, such as 40% or more, such as 45% or more of the pitch. The height may be less than 100%, such as 90% or less, such as 80% or less, such as 70% or less, such as 60% or less, such as 55% or less of the pitch.

[0038] In general, the multilayer coupling capacitor contains a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. The capacitor also includes external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposing the top surface of the capacitor.

[0039] In general, the capacitor includes at least two sets of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention may include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited. For instance, the capacitor may include at least three, such as at least four sets of alternating dielectric layers and internal electrode layers.

[0040] The first set of alternating dielectric layers and internal electrode layers and the second set of alternating dielectric layers and internal electrode layers may form at least part of the main body of the capacitor. By arranging the dielectric layers and the internal electrode layers in a stacked or laminated configuration, the capacitor may be referred to as a multilayer coupling capacitor and in particular a multilayer ceramic capacitor, for instance when the dielectric layers comprise a ceramic.

[0041] Each set of alternating dielectric layers and internal electrode layers comprises dielectric layers alternately arranged with internal electrode layers. In particular, the internal electrode layers include first internal electrode layers and second internal electrode layers interleaved in an opposed and spaced apart relation with a dielectric layer located between each internal electrode layer. In this regard, the respective internal electrode layers are distinct and separate internal electrode layers. However, in one embodiment, the dielectric layers that separate the internal electrode layers may not be distinct. For instance, the dielectric layer separating the internal electrode layers of the first set and the internal electrode layers of the second set may be the same such that it extends along the width of the coupling capacitor. For instance, within a single dielectric layer, two internal electrodes may be provided such that one will be present in the aforementioned first set while one will be present in the aforementioned second set. Accordingly, such layers may then be laminated to form the capacitor as disclosed herein.

[0042] In general, the thickness of the dielectric layers and internal electrode layers is not limited and can be any thickness as desired depending on the performance characteristics. For instance, the thickness of the internal electrode layers can be, but is not limited to, being about 500 nm or greater, such as about 1 pm or greater, such as about 2 pm or greater to about 10 pm or less, such as about 5 pm or less, such as about 4 pm or less, such as about 3 pm or less, such as about 2 pm or less. For instance, the internal electrode layers may have a thickness of from about 1 pm to about 2 pm. [0043] In addition, the present invention is not necessarily limited by the number of internal electrode layers per set of alternating dielectric layers and internal electrode layers or in the entire capacitor. For instance, each set may include 5 or more, such as 10 or more, such as 25 or more, such as 50 or more, such as 100 or more, such as 200 or more, such as 300 or more, such as 500 or more, such as 600 or more, such as 750 or more, such as 1 ,000 or more internal electrode layers. Each set may have 5,000 or less, such as 4,000 or less, such as 3,000 or less, such as 2,000 or less, such as 1 ,500 or less, such as 1 ,000 or less, such as 750 or less, such as 500 or less, such as 400 or less, such as 300 or less, such as 250 or less, such as 200 or less, such as 175 or less, such as 150 or less internal electrode layers. Also, the entire capacitor may include the aforementioned number of electrode layers.

[0044] The internal electrode layers have a top edge and a bottom edge opposite the top edge. The internal electrode layers also have two side edges or lateral edges that extend between the top edge and the bottom edge. In one embodiment, the side edges, top edge, and bottom edge define a main body of the internal electrode layers.

[0045] In general, in one embodiment, the top edge and the bottom edge may have the same dimension (e.g., length). In another embodiment, the top edge and the bottom edge may have a different dimension (e.g., length). The side edges may have the same dimension (e.g., height). In addition, the height of a side edge of the internal electrode layer as it extends between the top and bottom surfaces of the capacitor may be less than the height of the capacitor. In other words, in one embodiment, the internal electrode layers may form an electrical connection, such as a direct electrical connection wherein the internal electrode layer contacts the external terminal, with only the external terminal on the top surface of the capacitor or the external terminal on the bottom surface of the capacitor.

[0046] For instance, each set of alternating dielectric layers and internal electrode layers comprises dielectric layers alternately arranged with internal electrode layers. In particular, the internal electrode layers include first internal electrode layers and second internal electrode layers interleaved in an opposed and spaced apart relation with a dielectric layer located between each internal electrode layer. In one embodiment, the first internal electrode layers electrically contact a first external terminal while the second internal electrode layers electrically contact a second external terminal. For instance, the first internal electrode layers of a respective set may electrically contact the external terminal on the top surface of the capacitor while the second internal electrode layers of the respective set electrically contact the external terminal on the bottom surface of the capacitor.

[0047] Each internal electrode of a respective set may be substantially aligned. For instance, in one embodiment, at least one lateral edge of a first internal electrode layer may be substantially aligned with at least one lateral edge of a second internal electrode layer. In another embodiment, the point of electrical contact of at least one lateral edge of a first internal electrode layer with a respective external terminal may be substantially aligned with the point of electrical contact of at least one lateral edge of a second internal electrode layer with the opposite external terminal. In one embodiment, the point of electrical contact of both lateral edges of a first internal electrode layer with a respective external terminal may be substantially aligned with the point of electrical contact of both lateral edges of a second internal electrode layer with the opposite external terminal.

[0048] By substantially aligned, it is meant that the side edge or point of contact of a first internal electrode layer is within +/-10%, such as within +/-5%, such as within +/-4%, such as within +/-3%, such as within +1-2%, such as within +/-1 %, such as within +/-0.5% of the side edge or point of contact of a second internal electrode layer based on the distance from a side edge of the coupling capacitor.

[0049] Generally, the internal electrode layers of one set may not overlap the internal electrode layers of another set. However, generally, the internal electrode layers within a given set may overlap. For instance, such internal electrode layers may at least partially overlap. In one embodiment, the internal electrode layers only partially overlap. As an example, a first internal electrode layer and a second internal electrode layer within a respective set may at least partially overlap. In particular, the top edge of one internal electrode layer overlaps with the bottom edge of another internal electrode layer. In the instance that the first internal electrode layer includes a top edge that contacts an external terminal on a top surface of the capacitor and the second internal electrode layer includes a bottom edge that contacts an external terminal on a bottom surface of the capacitor, the bottom edge of the first internal electrode layer and the top edge of the second internal electrode layer overlap. Furthermore, the overlap of the first internal electrode layers and second internal electrode layers may be at least 10% or more, such as 25% or more, such as 35% or more, such as 50% or more, such as 60% or more, such as 70% or more, such as 80% or more based on the area defined by the lateral edges of the internal electrode layers and the top and bottom surfaces of the capacitor. Alternatively, such percentage may be based on the area of an internal electrode layer.

[0050] In addition, in one embodiment, prior to the first internal electrode layer within the respective sets, one or more dielectric layers may be provided such that such one or more dielectric layers are present between such internal electrode layers and the adjacent side surface. Similarly, after the last internal electrode layer within the respective sets, one or more dielectric layers may be provided such that such one or more dielectric layers are present between such internal electrode layers and the adjacent side surface. In this regard, such dielectric layers may include at least 2, such as at least 3, such as at least 5, such as at least 10 dielectric layers. Accordingly, such region may have a thickness greater than the thickness of an individual dielectric layer within the respective sets. In particular, the distance may be at least 2, such as at least 3, such as at least 5, such as at least 10 times the thickness of a dielectric layer in the set.

[0051] Similarly, at least two sets of alternating dielectric layers and internal electrode layers are spaced apart in a longitudinal direction (i.e. , in a direction that spans across the length of the capacitor and the major surfaces of the internal electrode layers and dielectric layers). For the sake of clarity, the lateral direction (i.e., in a direction that spans across the thicknesses of the internal electrode layers and dielectric layers) is defined as the width of the capacitor that is dictated by the number of layers in the capacitors.

[0052] The distance and spacing between the internal electrode layers in a given set or column may be specifically designed to ensure guided formation of terminations. Such distance between internal electrode layers in a given column may be about 10 microns or less, such as about 8 microns or less, such as from about 2 microns to about 8 microns. However, it should be understood that such distance may not necessarily be limited.

[0053] Additionally, the distance between adjacent columnar stacks of electrodes may be, while not limited, greater by at least a factor of two than the distance between adjacent internal electrode layers in a given column to ensure that distinct terminations do not run together. In some embodiments, the distance between adjacent columnar stacks of exposed metallization is about four times the distance between adjacent exposed electrode tabs in a particular stack. However, such distance may vary depending on the desired capacitance performance and circuit board configuration.

[0054] In addition, as mentioned herein, the external terminals have a certain pitch. In this regard, the respective bottom edges and the respective top edges of the internal electrode layers of the first set and the second set may have the same or similar pitch. In addition, the width of the internal electrode layers, in particular the width at the point of electrical contact, may be the same as the width of the external terminal. In another embodiment, the width of the internal electrode layer, for instance at the point of electrical contact or elsewhere along the lateral dimension, may be less than the width of the external terminal.

[0055] In addition, the internal electrode layers may be symmetric and/or symmetrically positioned within the capacitor in a given direction. For instance, the internal electrode layers may be symmetrical about a vertical line (i.e. , a line extending from the center of the top edge to the center of the bottom edge of the internal electrode layer) through the center of the main body of the internal electrode layer. In addition, the internal electrodes of the first set and the second set may be symmetrically positioned within the capacitor such that they are symmetrical about a vertical line (i.e., a line extending from the top surface to the bottom surface) through the center of the main body of the capacitor.

[0056] As indicated herein, the capacitor includes dielectric regions that include one or more air voids. In this regard, the dielectric region may be a region that includes dielectric material but does not include the internal electrode material. In this regard, the dielectric region may constitute a region that does not include alternatively arranged dielectric layers and internal electrode layers. Accordingly, the dielectric region may include the dielectric material between the respective sets of alternating dielectric layers and internal electrode layers. In addition, the dielectric region may include the dielectric material between a lateral edge of the electrodes in a given set of alternating dielectric layers and internal electrode layers and an adjacent side surface in the longitudinal direction. It should be understood that while such dielectric regions may be formed from ceramic green sheets of alternating dielectric layers and internal electrode layers, such regions do not include any internal electrode material or corresponding layers. As a result, air voids may be provided within such regions. In addition, the dielectric regions may include the dielectric material present between the first internal electrode layer of the respective sets and an adjacent side surface of the capacitor. The dielectric regions may also include the dielectric material present between the last internal electrode layer of the respective sets and an adjacent side surface of the capacitor. In one particular embodiment, the dielectric region may include the region within the capacitor present between two external terminals. In addition, it should be understood that the dielectric region may include a combination of any of the aforementioned regions.

[0057] As indicated above, the dielectric regions include those that include dielectric material but do not include the internal electrode material. Accordingly, no considering the air voids, the dielectric regions may include 90 vol.% or more, such as 93 vol.% or more, such as 95 vol.% or more, such as 97 vol.% or more, such as 98 vol.% or more, such as 99 vol.% or more, such as 100 vol.% of dielectric material.

[0058] In general, such air voids may not include any material, in particular any dielectric material or internal electrode material. In one embodiment, the air voids may be enclosed, such as partially or completely, by an enclosure material. In one embodiment, the air voids may be partially enclosed by an enclosure material. By partially enclosed, the enclosure material is only partially present around the interior of the air void such that it is partially separated from the dielectric material. In this regard, at least a certain perimeter of the air void may be in direct contact with the dielectric material of the dielectric region. In another embodiment, the air voids may be completely or entirely enclosed by an enclosure material. By entirely enclosed, the enclosure material is present around the interior of the air void such that it is entirely separated from the dielectric material. Regardless, the enclosure material may be utilized to serve as a barrier between the interior of the air void and the dielectric material of the dielectric region. In one embodiment, the enclosure material may be a non-conductive material. However, it should be understood that in one embodiment, the air voids may not be enclosed, even partially, by an enclosure material.

[0059] In this regard, in one embodiment, the air voids may be provided without any barrier between the air void and the dielectric material of the dielectric region. The air void may have any shape and is not necessarily limited. For instance, the shape may be a sphere, a cylinder, etc. In one embodiment, the shape may be a sphere. The air void may have a maximum dimension (e.g., length, width, diameter, etc.). The maximum dimension may be 5 microns or more, such as 10 microns or more, such as 20 microns or more, such as 30 microns or more, such as 40 microns or more, such as 50 microns or more, such as 80 microns or more, such as 100 microns or more, such as 200 microns or more, such as 300 microns or more, such as 400 microns or more, such as 500 microns or more, such as 600 microns or more, such as 800 microns or more, such as 1 ,000 microns or more. The maximum dimension may be 5,000 microns or less, such as 4,000 microns or less, such as 3,000 microns or less, such as 2,000 microns or less, such as 1 ,800 microns or less, such as 1 ,600 microns or less, such as 1 ,400 microns or less, such as 1 ,200 microns or less, such as 1 ,000 microns or less, such as 800 microns or less, such as 600 microns or less, such as 500 microns or less, such as 400 microns or less, such as 300 microns or less, such as 250 microns or less, such as 200 microns or less, such as 180 microns or less, such as 160 microns or less, such as 140 microns or less, such as 120 microns or less, such as 100 microns or less, such as 80 microns or less, such as 60 microns or less, such as 50 microns or less, such as 40 microns or less.

[0060] These voids may be provided using means capable of providing such voids within the capacitor. For instance, these voids may be formed by printing particular patterns in the ceramic green sheets and thereafter laminating and firing the stacked laminated. Alternately, these voids may be formed using various drilling techniques in order to provide any desired shape within the dielectric material of the dielectric region. [0061] As another example, the air voids may be presented using one or more vias (e.g., through-hole vias). The vias may be unfilled with material, such as any conductive or nonconductive material, such that air is present within the interior. In addition, in one embodiment, the vias may be provided such that they are only present within the dielectric region. In this regard, the vias may be provided that such that they do not contact any of the internal electrode layers. [0062] In one embodiment, the vias may extend from a top surface of the capacitor to a bottom surface of the capacitor. In this regard, the vias may be columnar extending through the thickness of the capacitor. Accordingly, the via may be a through hole conductive via. In another embodiment, the vias may only partially extend through the thickness of the capacitor. For instance, the vias may extend 10% or more, such as 20% or more, such as 30% or more, such as 40% or more, such as 50% or more, such as 60% or more, such as 70% or more, such as 80% or more, such as 90% or more of the thickness of the capacitor. The vias may extend 100% or less, such as 90% or less, such as 80% or less, such as 70% or less, such as 60% or less, such as 50% or less, such as 40% or less, such as 30% or less, such as 20% or less, such as 10% or less the thickness of the capacitor. In one embodiment, such aforementioned extension through the thickness may refer to the average extension of the vias through the thickness of the capacitor.

[0063] In embodiments including more than one via, all of the vias may have the same length. For instance, two or more of the vias may have the same length. However, it should be understood that two or more of the vias may also have a different length.

[0064] The cross-sectional area of the via-hole may be 0.00005 mm ² or more, such as 0.0001 mm ² or more, such as 0.0005 mm ² or more, such as 0.001 mm ² or more, such as 0.005 mm ² or more, such as 0.01 mm ² or more. The cross- sectional area of the via-hole may be 1 mm ² or less, such as 0.5 mm ² or less, such as 0.1 mm ² or less, such as 0.09 mm ² or less, such as 0.07 mm ² or less, such as 0.05 mm ² or less, such as 0.01 mm ² or less, such as 0.005 mm ² or less, such as 0.001 mm ² or less.

[0065] The distance between vias may not be necessarily limited by the present invention. As mentioned herein, the external terminals may have a certain pitch. In this regard, the vias may also have the same or similar pitch. Furthermore, the average pitch between a first via and an adjacent second via may be less than the average pitch between the first via and another adjacent third via. [0066] Furthermore, the average length of a first and second via may be a certain length in comparison to the average pitch between a first via and an adjacent second via. In one embodiment, the average length may be greater than or equal to the average pitch between a first via and an adjacent second via. In a further embodiment, the average length may be less than or equal to the average pitch between a first via and an adjacent second via. For instance, the average length may be 10 times or less, such as 8 times or less, such as 6 times or less, such as 5 times or less, such as 4 times or less, such as 3 times or less, such as 2 times or less, such as 1 time or less the average pitch between a first via and an adjacent second via. The average length may be 0.001 times or more, such as 0.01 times or more, such as 0.1 times or more, such as 0.2 times or more, such as 0.3 times or more, such as 0.5 times or more, such as 0.7 times or more, such as 0.9 times or more, such as 1 time or more the average pitch between a first via and an adjacent second via.

[0067] In one embodiment, the vias may be provided between adjacent external terminals in an “L” direction of the capacitor. In one embodiment, the vias may be provided between adjacent external terminals in “W” direction of the capacitor. In an even further embodiment, the vias may be provided between adjacent external terminals in both an “L” direction and a “W” direction of the capacitor.

[0068] The method may also include forming the vias. In one embodiment, the vias may be formed by forming holes or cutouts in the ceramic green sheets before they are laminated together. Alternatively, the vias may be formed by forming holes into the stacked body after lamination. For instance, this may be done after laminating the layers and ceramic green sheets. In addition, in one embodiment, it may be done before firing the stacked body. In another embodiment, it may be done after firing the stacked body. Regardless, the vias may be capped such as to cover any holes on the top and/or bottom surface of the capacitor. For instance, the vias may be capped using a non-conductive material, such as the ceramic or a polymer. In particular, the ceramic may be the ceramic utilized in forming the dielectric layers of the capacitor.

[0069] In another embodiment, the dielectric region may include hollow filler materials. For instance, these hollow filler materials may allow for the presence of air within the interior of the material. These hollow filler materials may be entirely enclosed or may be at least partially open. By entirely enclosed, a barrier is present around the interior of the hollow filler material such that it is entirely separated from the dielectric material. Meanwhile, with an open hollow filler material, at least some of the perimeter is open and exposed such that a barrier is not present between the interior of the hollow filler material and the dielectric material.

[0070] The hollow filler materials may be any filler material that can include a hollow interior. For instance, these may include, but are not limited to, spheres, fibers, tubes, rods, etc. In one embodiment, the filler material may include spheres, such as microspheres or nanospheres. For instance, in one embodiment, the filler material may include microspheres. In another embodiment, the filler material may include nanospheres. In another embodiment, the filler materials may include tubes.

[0071] In one embodiment, the hollow filler materials may be non- conductive. For instance, the hollow filler materials may not be made of a metal. In addition, in one embodiment, the hollow filler materials may not be made from a material including a metal additive. In this regard, in one embodiment, the hollow filler material may be made from a polymer or a ceramic. For instance, the ceramic may include glass, a silicate, etc. In one embodiment, the ceramic may include glass. In another embodiment, the ceramic may include a silicate, such as an aluminosilicate. Meanwhile, the polymer may be a thermoplastic polymer or a thermoset polymer. In one embodiment, the polymer may be a thermoplastic polymer. In another embodiment, the polymer may be a thermoset polymer.

[0072] The hollow filler materials may have a certain density. For instance, the density may be 0.2 g/cc or more, such as 0.25 g/cc or more, such as 0.3 g/cc or more, such as 0.35 g/cc or more, such as 0.4 g/cc or more, such as 0.5 g/cc or more, such as 0.6 g/cc or more, such as 0.7 g/cc or more. The density may be 1 .5 g/cc or less, such as 1 .3 g/cc or less, such as 1 .1 g/cc or less, such as 1 g/cc or less, such as 0.9 g/cc or less, such as 0.8 g/cc or less, such as 0.7 g/cc or less, such as 0.6 g/cc or less, such as 0.5 g/cc or less, such as 0.4 g/cc or less. In one embodiment, the aforementioned density may refer to a bulk density.

[0073] The hollow filler materials may have a maximum dimension (e.g., length, width, diameter, etc.). The maximum dimension may be 5 microns or more, such as 10 microns or more, such as 20 microns or more, such as 30 microns or more, such as 40 microns or more, such as 50 microns or more, such as 80 microns or more, such as 100 microns or more, such as 200 microns or more, such as 300 microns or more, such as 400 microns or more, such as 500 microns or more, such as 600 microns or more, such as 800 microns or more, such as 1 ,000 microns or more. The maximum dimension may be 5,000 microns or less, such as 4,000 microns or less, such as 3,000 microns or less, such as 2,000 microns or less, such as 1 ,800 microns or less, such as 1 ,600 microns or less, such as 1 ,400 microns or less, such as 1 ,200 microns or less, such as 1 ,000 microns or less, such as 800 microns or less, such as 600 microns or less, such as 500 microns or less, such as 400 microns or less, such as 300 microns or less, such as 250 microns or less, such as 200 microns or less, such as 180 microns or less, such as 160 microns or less, such as 140 microns or less, such as 120 microns or less, such as 100 microns or less, such as 80 microns or less, such as 60 microns or less, such as 50 microns or less, such as 40 microns or less.

[0074] The hollow filler material may be present within the dielectric region in a particular weight percentage. For instance, the hollow filler material may be present in an amount of 0.1 wt.% or more, such as 0.5 wt.% or more, such as 1 wt.% or more, such as 2 wt.% or more, such as 3 wt.% or more, such as 5 wt.% or more, such as 8 wt.% or more, such as 10 wt.% or more, such as 15 wt.% or more, such as 20 wt.% or more, such as 25 wt.% or more, such as 30 wt.% or more of the weight of the dielectric region. The hollow filler material may be present in an amount of 50 wt.% or less, such as 40 wt.% or less, such as 35 wt.% or less, such as 30 wt.% or less, such as 25 wt.% or less, such as 20 wt.% or less, such as 18 wt.% or less, such as 16 wt.% or less, such as 14 wt.% or less, such as 12 wt.% or less, such as 10 wt.% or less, such as 9 wt.% or less, such as 8 wt.% or less, such as 7 wt.% or less, such as 6 wt.% or less, such as 5 wt.% or less. [0075] The hollow filler material may be present within the dielectric region in a particular volume percentage. For instance, the hollow filler material may be present in an amount of 0.1 vol.% or more, such as 0.5 vol.% or more, such as 1 vol.% or more, such as 2 vol.% or more, such as 3 vol.% or more, such as 5 vol.% or more, such as 8 vol.% or more, such as 10 vol.% or more, such as 15 vol.% or more, such as 20 vol.% or more, such as 25 vol.% or more, such as 30 vol.% or more of the weight of the dielectric region. The hollow filler material may be present in an amount of 50 vol.% or less, such as 40 vol.% or less, such as 35 vol.% or less, such as 30 vol.% or less, such as 25 vol.% or less, such as 20 vol.% or less, such as 18 vol.% or less, such as 16 vol.% or less, such as 14 vol.% or less, such as 12 vol.% or less, such as 10 vol.% or less, such as 9 vol.% or less, such as 8 vol.% or less, such as 7 vol.% or less, such as 6 vol.% or less, such as 5 vol.% or less.

[0076] While the above provides various options for providing air voids within the dielectric regions, it should be understood that may be used individually or in combination. For instance, air voids formed within the body (e.g., without a barrier/enclosure material) may be combined with air voids formed as vias. Similarly, air voids may include those formed by vias and a hollow filler material. Alternatively, the air voids may include a combination of those formed within the body without a barrier/enclosure material and hollow filler materials. In this regard, it should be understood that the present invention is not necessarily limited in this regard.

[0077] The air voids may constitute a particular volume of the capacitor. For instance, the air voids may constitute 1 vol.% or more, such as 2 vol.% or more, such as 3 vol.% or more, such as 5 vol.% or more, such as 10 vol.% or more, such as 15 vol.% or more, such as 20 vol.% or more of the capacitor, in particular the stacked laminate of dielectric layers and internal electrode layers. The air voids may constitute 30 vol.% or less, such as 25 vol.% or less, such as 20 vol.% or less, such as 18 vol.% or less, such as 15 vol.% or less, such as 13 vol.% or less, such as 11 vol.% or less, such as 10 vol.% or less, such as 9 vol.% or less, such as 8 vol.% or less, such as 7 vol.% or less, such as 6 vol.% or less, such as 5 vol.% or less of the capacitor, in particular the stacked laminate of dielectric layers and internal electrode layers. [0078] The air voids may constitute a particular volume of the dielectric regions of the capacitor. For instance, the air voids may constitute 1 vol.% or more, such as 2 vol.% or more, such as 3 vol.% or more, such as 5 vol.% or more, such as 10 vol.% or more, such as 15 vol.% or more, such as 20 vol.% or more, such as 25% or more, such as 30% or more of the dielectric regions of the capacitor. The air voids may constitute 40 vol.% or less, such as 30 vol.% or less, such as 25 vol.% or less, such as 20 vol.% or less, such as 18 vol.% or less, such as 15 vol.% or less, such as 13 vol.% or less, such as 11 vol.% or less, such as 10 vol.% or less, such as 9 vol.% or less, such as 8 vol.% or less, such as 7 vol.% or less, such as 6 vol.% or less, such as 5 vol.% or less of the dielectric regions of the capacitor.

[0079] Without intending to be limited, by providing the aforementioned air voids, the dielectric region may have a relatively low dielectric constant. For instance, the dielectric constant may be 3 or more, such as 3.5 or more, such as 4 or more, such as 4.5 or more, such as 5 or more, such as 7 or more, such as 10 or more, such as 15 or more, such as 20 or more, such as 25 or more, such as 30 or more, such as 40 or more, such as 50 or more, such as 60 or more, such as 70 or more, such as 80 or more, such as 90 or more, such as 100 or more, such as 200 or more, such as 300 or more, such as 400 or more, such as 500 or more, such as

1 ,000 or more. The dielectric constant may be 10,000 or less, such as 5,000 or less, such as 2,000 or less, such as 1 ,000 or less, such as 800 or less, such as 600 or less, such as 400 or less, such as 200 or less, such as 150 or less, such as 100 or less, such as 90 or less, such as 80 or less, such as 70 or less, such as 60 or less, such as 50 or less, such as 40 or less, such as 30 or less, such as 25 or less, such as 20 or less, such as 15 or less, such as 10 or less. In one embodiment, such aforementioned dielectric constant may be determined at 1 MHz.

[0080] The capacitor of the present invention also includes external terminals on the top surface and the bottom surface. In one particular embodiment, the external terminals may not be present on a side surface of the capacitor.

[0081] The external terminals include at least one first polarity terminal and at least one second and opposite polarity terminal. The capacitors may include at least one, such as at least two, such as at least four, such as at least six, such as at least eight first polarity terminals and/or second and opposite polarity terminals on a top surface of the capacitor. Additionally, the capacitors may include the aforementioned amounts of terminals on a bottom surface of the capacitor.

[0082] The capacitors may include an equal number of first polarity terminals and/or second polarity terminals on the top surface of a capacitor and the bottom surface of a capacitor. The number of first polarity terminals may equal the number of second and opposite polarity terminals on a top surface of a capacitor. The number of first polarity terminals may equal the number of second and opposite polarity terminals on a bottom surface of a capacitor. The total number of terminals present on a top surface of the capacitor may equal to the total number of terminals present on a bottom surface of the capacitor. The total number of first polarity terminals present on a top surface and a bottom surface of the capacitor may equal the total number of second and opposite polarity terminals present on a top surface and a bottom surface of the capacitor.

[0083] In general, the polarity terminals located on a top surface and a bottom surface of a capacitor may not be interdigitated. In this regard, corresponding polarity terminals on a top and a bottom surface may not be offset by a terminal position but may instead be positioned directly above or below another polarity terminal on the opposite top or bottom surface. In other words, corresponding polarity terminals that correspond to a particular set of alternating dielectric layers and internal electrode layers may be substantially aligned. By substantially aligned, it is meant that the offset from a side surface of the capacitor of one lateral edge of a polarity terminal on a top surface is within +/-10%, such as within +/-5%, such as within +/-4%, such as within +/-3%, such as within +1-2%, such as within +/-1 %, such as within +/-0.5% of the offset from a side edge of a corresponding polarity terminal on a bottom surface. However, in one embodiment, the external terminals may be interdigitated.

[0084] The capacitor of the present invention can be further described according to the embodiments as illustrated in Figures 1A-1C.

[0085] Figure 1A illustrates a capacitor 10 in a 2 by 1 configuration. That is, the capacitor includes two terminals along one dimension of the top surface and the bottom surface. In this regard, the capacitor 10 includes a total of two external terminals 12, 14 on a top surface and two corresponding external terminals (not shown) on a bottom surface wherein the external terminals on the top surface correspond to the external terminals on the bottom surface.

[0086] The capacitor 10 of Figure 1A includes external terminals 12, 14 and two sets of alternating dielectric layers and internal electrode layers 110, as illustrated in Figure 1C. As illustrated in Figures 1 B and 1 C, each set of alternating dielectric layers and internal electrode layers 110 includes internal electrode layers 105, 115 and dielectric layers (not shown) in an alternate arrangement.

[0087] In general, the internal electrode layers 105 extend to a top surface of the capacitor and internal electrode layers 115 extend to a bottom surface of the capacitor. The extensions assist in the formation of the external terminals. In this regard, the internal electrode layers may be exposed on the top surface and the bottom surface of the capacitor and allow for connection between the main body of the internal electrode layers and the external terminals. For instance, internal electrode layers 105, 115 extend to an edge of a dielectric layer and allow for formation of the external terminals.

[0088] The lateral or sides edges of the internal electrode layers 105, 115 may be aligned in the vertical direction. That is, a lateral edge of a first internal electrode layer 105 may be aligned with a lateral edge of a second internal electrode layer 115. In one embodiment, both lateral edges may be aligned. In another embodiment, the point of contact of a first internal electrode layer 105 with an external terminal may be aligned with the point of contact of a second internal electrode layer 115 with an external terminal.

[0089] In addition, as illustrated in Figures 1 B and 1 C, the capacitor 10 also includes dielectric regions 125. As indicated herein, such dielectric regions include those regions that may simply include dielectric material and not any internal electrode material. As illustrated in Figure 1 B, such dielectric regions 125 include the regions prior to the first internal electrode layer of the respect sets and between such layer and the adjacent side surface. The dielectric regions 125 also include the regions after the last internal electrode layer of the respective set and between such layer and the adjacent side surface. As illustrated in Figure 1 C, the dielectric regions 125 include the material between the respective sets of alternating dielectric layers and internal electrode layers as well as the material between the nearest lateral or side edge of the internal electrode layers and the adjacent side surface.

[0090] With such dielectric regions 125, one or more air voids may be provided as disclosed herein. As one example, a via 135 is provided as illustrated in Figure 1C. However, it should be understood that more than one via may be provided. In addition, such via extends through the thickness from the top surface to the bottom surface of the capacitor. However, it should be understood that the via may not extend through the entire thickness of the capacitor. As also indicated herein, the air voids may be presented in another manner as also disclosed herein. [0091] Additionally, capacitor 10 of Figure 1A includes at least one first polarity terminal and at least one second and opposite polarity terminal on a top surface. Although not shown, the bottom surface includes at least a first polarity terminal and a second and opposite terminal.

[0092] As illustrated in Figures 1A-1C, the capacitor contains two external terminals on each surface and two sets of alternating dielectric layers and internal electrode layers. However, as indicated above, the present invention is not limited by the number of external terminals and/or the number of sets of alternating dielectric layers and internal electrode layers. Also, Figure 1 B employs only eleven internal layers per set of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention may include any number of internal electrode layers per set and is not necessarily limited. [0093] In general, the present invention provides a capacitor having a unique configuration that provides various benefits and advantages. In this regard, it should be understood that the materials employed in constructing the capacitor may not be limited and may be any as generally employed in the art and formed using any method generally employed in the art.

[0094] In general, the dielectric layers are typically formed from a dielectric material. The dielectric material may have a relatively high dielectric constant in one embodiment. In another embodiment, the dielectric material may have a relatively low dielectric constant. For instance, the dielectric constant may be 3 or more, such as 3.5 or more, such as 4 or more, such as 4.5 or more, such as 5 or more, such as 7 or more, such as 10 or more, such as 15 or more, such as 20 or more, such as 25 or more, such as 30 or more, such as 40 or more, such as 50 or more, such as 60 or more, such as 70 or more, such as 80 or more, such as 90 or more, such as 100 or more, such as 200 or more, such as 300 or more, such as 400 or more, such as 500 or more, such as 1 ,000 or more, such as 2,000 or more, such as 5,000 or more, such as 10,000 or more. The dielectric constant may be 40,000 or less, such as 30,000 or less, such as 20,000 or less, such as 10,000 or less, such as 5,000 or less, such as 2,000 or less, such as 1 ,000 or less, such as 800 or less, such as 600 or less, such as 400 or less, such as 200 or less, such as 150 or less, such as 100 or less, such as 90 or less, such as 80 or less, such as 70 or less, such as 60 or less, such as 50 or less, such as 40 or less, such as 30 or less, such as 25 or less, such as 20 or less, such as 15 or less, such as 10 or less. [0095] In this regard, the dielectric material may be a ceramic. The ceramic may be provided in a variety of forms, such as a wafer (e.g., pre-fired) or a dielectric material that is co-fired within the device itself.

[0096] Particular examples of the type of high dielectric material include, for instance, NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and/or Y5V materials. It should be appreciated that the aforementioned materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and as such should be recognized by one of ordinary skill in the art. For instance, such material may include a ceramic. Such materials may include a pervoskite, such as barium titanate and related solid solutions (e.g., barium-strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, and so forth. In one particular embodiment, for instance, barium strontium titanate (“BSTO”) of the formula BaxSn-xTiOs may be employed, wherein x is from 0 to 1 , in some embodiments from about 0.15 to about 0.65, and in some embodiments, from about from 0.25 to about 0.6. Other suitable perovskites may include, for instance, Ba _x Cai- _x TiO3 where x is from about 0.2 to about 0.8, and in some embodiments, from about 0.4 to about 0.6, PbxZn-xTiOs (“PZT”) where x ranges from about 0.05 to about 0.4, lead lanthanum zirconium titanate (“PLZT”), lead titanate (PbTiOs), barium calcium zirconium titanate (BaCaZrTiOs), sodium nitrate (NaNOs), KNbOs, LiNbOs, LiTaOs, PbNb ₂ O ₆ , PbTa ₂ O ₆ , KSr(NbO ₃ ) and NaBa2(NbO3)sKHb2PO4. Still additional complex perovskites may include A[B1 I/ ₃ B22/3]O3 materials, where A is Ba _x Sri- _x (x can be a value from 0 to 1); B1 is Mg _y Zni- _y (y can be a value from 0 to 1); B2 is Ta _z Nbi- _z (z can be a value from 0 to 1). In one particular embodiment, the dielectric layers may comprise a titanate. [0097] The internal electrode layers may be formed from any of a variety of different metals as is known in the art. The internal electrode layers may be made from a metal, such as a conductive metal. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chrome, titanium, tungsten, etc.), and so forth, as well as various combinations thereof. Sputtered titanium/tungsten (Ti/W) alloys, as well as respective sputtered layers of chrome, nickel and gold, may also be suitable. In one particular embodiment, the internal electrode layers may comprise nickel or an alloy thereof.

[0098] External terminals may be formed from any of a variety of different metals as is known in the art. The external terminals may be made from a metal, such as a conductive metal. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chrome, titanium, tungsten, etc.), and so forth, as well as various combinations thereof. In one particular embodiment, the external terminals may comprise copper or an alloy thereof.

[0099] The external terminals can be formed using any method generally known in the art. The external terminals may be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray/air brushing, and so forth. [00100] The external terminals may be formed such that the external terminal is a thin-film plating of a metal. Such thin-film plating can be formed by depositing a conductive material, such as a conductive metal, on an exposed portion of an internal electrode layer. For instance, a leading edge of an internal electrode layer may be exposed such that it may allow for the formation of a plated termination. [00101] The external terminals may have an average thickness of about 50 pm or less, such as about 40 pm or less, such as about 30 pm or less, such as about 25 pm or less, such as about 20 pm or less to about 5 pm or more, such as about 10 pm or more, such as about 15 pm or more. For instance, the external terminals may have an average thickness of from about 5 pm to about 50 pm, such as from about 10 pm to about 40 pm, such as from about 15 pm to about 30 pm, such as from about 15 pm to about 25 pm.

[00102] In general, the external terminal may comprise a plated terminal. For instance, the external terminal may comprise an electroplated terminal, an electroless plated terminal, or a combination thereof. For instance, an electroplated terminal may be formed via electrolytic plating. An electroless plated terminal may be formed via electroless plating.

[00103] When multiple layers constitute the external terminal, the external terminal may include an electroplated terminal and an electroless plated terminal. For instance, electroless plating may first be employed to deposit an initial layer of material. The plating technique may then be switched to an electrochemical plating system which may allow for a faster buildup of material.

[00104] When forming the plated terminals with either plating method, a leading edge of the internal electrode layers that is exposed from the main body of the capacitor is subjected to a plating solution. By subjecting, in one embodiment, the capacitor may be dipped into the plating solution.

[00105] The plating solution contains a conductive material, such as a conductive metal, is employed to form the plated termination. Such conductive material may be any of the aforementioned materials or any as generally known in the art. For instance, the plating solution may be a nickel sulfamate bath solution or other nickel solution such that the plated layer and external terminal comprise nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution such that the plated layer and external terminal comprise copper.

[00106] Additionally, it should be understood that the plating solution may comprise other additives as generally known in the art. For instance, the additives may include other organic additives and media that can assist in the plating process. Additionally, additives may be employed in order to employ the plating solution at a desired pH. In one embodiment, resistance-reducing additives may be employed in the solutions to assist with complete plating coverage and bonding of the plating materials to the capacitor and exposed leading edges of the internal electrode layers. [00107] The capacitor may be exposed, submersed, or dipped in the plating solution for a predetermined amount of time. Such exposure time is not necessarily limited but may be for a sufficient amount of time to allow for enough plating material to deposit in order to form the plated terminal. In this regard, the time should be sufficient for allowing the formation of a continuous connection among the desired exposed, adjacent leading edges of the internal electrode layers of a given polarity of the respective internal electrode layers within a set of alternating dielectric layers and internal electrode layers.

[00108] In general, the difference between electrolytic plating and electroless plating is that electrolytic plating employs an electrical bias, such as by using an external power supply. The electrolytic plating solution may be subjected typically to a high current density range, for example, ten to fifteen amp/ft ² (rated at 9.4 volts). A connection may be formed with a negative connection to the capacitor requiring formation of the plated terminals and a positive connection to a solid material (e.g., Cu in Cu plating solution) in the same plating solution. That is, the capacitor is biased to a polarity opposite that of the plating solution. Using such method, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the internal electrode layers.

[00109] Prior to submersing or subjecting the capacitor to a plating solution, various pretreatment steps may be employed. Such steps may be conducted for a variety of purposes, including to catalyze, to accelerate, and/or to improve the adhesion of the plating materials to the leading edges of the internal electrode layers.

[00110] Additionally, prior to plating or any other pretreatment steps, an initial cleaning step may be employed. Such step may be employed to remove any oxide buildup that forms on the exposed edges of the internal electrode layers. This cleaning step may be particularly helpful to assist in removing any buildup of nickel oxide when the internal electrodes or other conductive elements are formed of nickel. Component cleaning may be effected by full immersion in a preclean bath, such as one including an acid cleaner. In one embodiment, exposure may be for a predetermined time, such as on the order of about 10 minutes. Cleaning may also alternatively be effected by chemical polishing or harperizing steps. [00111] In addition, a step to activate the exposed metallic leading edges of the internal electrode layers may be performed to facilitate depositing of the conductive materials. Activation can be achieved by immersion in palladium salts, photo patterned palladium organometallic precursors (via mask or laser), screen printed or ink-jet deposited palladium compounds or electrophoretic palladium deposition. It should be appreciated that palladium-based activation is presently disclosed merely as an example of activation solutions that often work well with activation for exposed tab portions formed of nickel or an alloy thereof. However, it should be understood that other activation solutions may also be utilized.

[00112] Also, in lieu of or in addition to the aforementioned activation step, the activation dopant may be introduced into the conductive material when forming the internal electrode layers of the capacitor. For instance, when the internal electrode layer comprises nickel and the activation dopant comprises palladium, the palladium dopant may be introduced into the nickel ink or composition that forms the internal electrode layers. Doing so may eliminate the palladium activation step. It should be further appreciated that some of the above activation methods, such as organometallic precursors, also lend themselves to codeposition of glass formers for increased adhesion to the generally ceramic body of the capacitor. When activation steps are taken as described above, traces of the activator material may often remain at the exposed conductive portions before and after termination plating.

[00113] Additionally, post-treatment steps after plating may also be employed. Such steps may be conducted for a variety of purposes, including enhancing and/or improving adhesion of the materials. For instance, a heating (or annealing) step may be employed after performing the plating step. Such heating may be conducted via baking, laser subjection, UV exposure, microwave exposure, arc welding, etc.

[00114] As indicated herein, the external terminal comprises at least one plating layer. In one embodiment, the external terminal may comprise only one plating layer. However, it should be understood that the external terminals may comprise a plurality of plating layers. For instance, the external terminals may comprise a first plating layer and a second plating layer. In addition, the external terminals may also comprise a third plating layer. The materials of these plating layers may be any of the aforementioned and as generally known in the art.

[00115] For instance, one plating layer, such as a first plating layer, may comprise copper or an alloy thereof. Another plating layer, such as a second plating layer, may comprise nickel or an alloy thereof. Another plating layer, such as a third plating layer, may comprise tin, lead, gold, or a combination, such as an alloy. Alternatively, an initial plating layer may include nickel, following by plating layers of tin or gold. In another embodiment, an initial plating layer of copper may be formed and then a nickel layer.

[00116] In one embodiment, initial or first plating layer may be a conductive metal (e.g., copper). This area may then be covered with a second layer containing a resistor-polymeric material for sealing. The area may then be polished to selectively remove resistive polymeric material and then plated again with a third layer containing a conductive, metallic material (e.g., copper).

[00117] The aforementioned second layer above the initial plating layer may correspond to a solder barrier layer, for example a nickel-solder barrier layer. In some embodiments, the aforementioned layer may be formed by electroplating an additional layer of metal (e.g., nickel) on top of an initial electrolessly or electrolytically plated layer (e.g., plated copper). Other exemplary materials for layer the aforementioned solder barrier layer include nickel-phosphorus, gold, and silver. A third layer on the aforementioned solder-barrier layer may in some embodiments correspond to a conductive layer, such as plated Ni, Ni/Cr, Ag, Pd, Sn, Pb/Sn or other suitable plated solder.

[00118] In addition, a layer of metallic plating may be formed followed by an electroplating step to provide a resistive alloy or a higher resistance metal alloy coating, for example, electroless Ni — P alloy over such metallic plating. It should be understood, however, that it is possible to include any metal coating as those of ordinary skill in the art will understand from the complete disclosure herewith.

[00119] It should be appreciated that any of the aforementioned steps can occur as a bulk process, such as barrel plating, fluidized bed plating and/or flow- through plating termination processes, all of which are generally known in the art. Such bulk processes enable multiple components to be processed at once, providing an efficient and expeditious termination process. This is a particular advantage relative to conventional termination methods, such as the printing of thick-film terminations that require individual component processing.

[00120] As described herein, the formation of the external terminals is generally guided by the position of the exposed leading edges of the internal electrode layers. Such phenomena may be referred to as “self-determining” because the formation of the external plated terminals is determined by the configuration of the exposed conductive metal of the internal electrode layers at the selected peripheral locations on the capacitor.

[00121] Additional aspects of the above-described technology for forming thin-film plated terminations are described in U.S. Pat. Nos. 7,177,137 to Ritter et al. and 7,463,474 to Ritter et al., which are incorporated by reference herein for all purposes. It should be appreciated that additional technologies for forming capacitor terminals may also be within the scope of the present technology. Exemplary alternatives include, but are not limited to, formation of terminations by plating, magnetism, masking, electrophoretics/electrostatics, sputtering, vacuum deposition, printing or other techniques for forming both thick-film or thin-film conductive layers.

[00122] The coupling capacitors of the present invention can be employed in many applications. For instance, they can be employed in in various applications that require a high speed interface (e.g., high speed differential interface). These applications may include those that employ a SerDes (i.e. , Serializer/Deserializer) function or architecture. These may also include those applications that employ a PCIE (i.e., PCI Express) and/or QPI (i.e., QuickPath Interconnect) function or architecture. These applications can include various communications devices. For instance, they can include Ethernet systems, such as Gigabit Ethernet systems, wireless network routers, fiber optic communications systems, and storage devices.

[00123] These and other modifications and variations of the present invention may be practiced by those of ordinary skill in the art, without departing from the spirit and scope of the present invention. In addition, it should be understood that aspects of the various embodiments may be interchanged both in whole or in part. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only and is not intended to limit the invention so further described in such appended claims.