Title:
SURFACE-MOUNTED THIN FILM RESISTOR NETWORK
Document Type and Number:
WIPO Patent Application WO/2018/003402
Kind Code:
A1
Abstract:
The present invention relates to a surface-mounted thin film resistor network in which a chip on which a thin-film resistor integrated array comprising a metal film is sealed with a mold resin. The present invention is provided with: a chip (13) on which a thin-film resistor integrated array has been formed; an island (12) to which the chip is secured; a plurality of lead terminals (14) extending outward around the periphery of the island; wires (15) connecting electrodes of resistors mounted on the chip and the lead terminals; and a mold resin (20) that seals a portion that includes the wires. Hanging leads (18) extending from the island are cut at a package end surface sealed with the mold resin, and electrical insulation (21) is applied to the cut sections (18a) of the hanging leads.
Inventors:
KANEGAE SATOSHI (JP)
OGUCHI TOMONORI (JP)
KASHIWAGI NOBORU (JP)
OGUCHI TOMONORI (JP)
KASHIWAGI NOBORU (JP)
Application Number:
PCT/JP2017/020591
Publication Date:
January 04, 2018
Filing Date:
June 02, 2017
Export Citation:
Assignee:
KOA CORP (JP)
International Classes:
H01L23/29; H01C13/02; H01L23/31; H01L23/50
Foreign References:
| JPS61208257A | 1986-09-16 | |||
| JPS6164143A | 1986-04-02 | |||
| JPS5963736A | 1984-04-11 |
Attorney, Agent or Firm:
HIROSAWA, Tetsuya et al. (JP)
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