Title:
SWITCH CIRCUIT, HIGH-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/159705
Kind Code:
A1
Abstract:
A switch circuit (10) is provided with: a transistor (T1) in which a drain terminal (D1) is connected to an input/output terminal (110), a source terminal (S1) is connected to a node (N1) on a first path, and switching between conduction and non-conduction between the drain terminal (D1) and the source terminal (S1) is performed; a transistor (T2) in which a source terminal (S2) is connected to an input/output terminal (120), a drain terminal (D2) is connected to the node (N1), and switching between conduction and non-conduction between the drain terminal (D2) and the source terminal (S2) is performed in synchronization with the transistor (T1); a transistor (T3) in which a drain terminal (D3) and a source terminal (S3) are disposed on a second path connecting the node (N1) and a ground, and switching between conduction and non-conduction between the drain terminal (D3) and the source terminal (S3) is exclusively performed separately from the transistors (T1 and T2); and a capacitor (C1) disposed on the second path and series-connected to the transistor (T3).
Inventors:
BEPPU NOBUYASU (JP)
Application Number:
PCT/JP2019/003479
Publication Date:
August 22, 2019
Filing Date:
January 31, 2019
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03K17/687; H03K17/693; H04B1/00; H04B1/401
Foreign References:
| JP2007214825A | 2007-08-23 | |||
| JP2005303794A | 2005-10-27 | |||
| JP2010147589A | 2010-07-01 | |||
| JP2004072362A | 2004-03-04 | |||
| JPH05299995A | 1993-11-12 |
Attorney, Agent or Firm:
YOSHIKAWA, Shuichi et al. (JP)
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