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Title:
SWITCHED-MODE PWM REGULATOR WITH RAMP RESET
Document Type and Number:
WIPO Patent Application WO/2011/066402
Kind Code:
A2
Abstract:
A regulator circuit can include a ramp generator configured to provide a ramp signal, a switch configured to provide input power to a filter, an error amplifier configured to provide an error signal at least in part using a difference between a first reference voltage and an output of the filter, a first comparator configured to compare the error signal with the ramp signal, control logic configured to control a state of the switch in response to an output signal from the first comparator, a second comparator configured to compare the output of the filter with a second reference voltage. The ramp generator can be configured to reset the ramp signal to a specified state in response to an output signal from the second comparator.

Inventors:
BACON RODERICK (US)
Application Number:
PCT/US2010/058022
Publication Date:
June 03, 2011
Filing Date:
November 24, 2010
Export Citation:
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Assignee:
BACON RODERICK (US)
International Classes:
G05F1/00; G05F1/10
Foreign References:
US7372238B12008-05-13
US5917313A1999-06-29
KR20030094010A
Attorney, Agent or Firm:
PERDOK-SHONKA, Monique M., Reg. No. 42,989 et al. (LUNDBERG & WOESSNER P.A.,P.O. Box 293, Minneapolis Minnesota, US)
Download PDF:
Claims:
WHAT IS CLAIMED IS:

1. A regulator circuit, comprising:

a ramp generator configured to provide a ramp signal;

a switch configured to provide input power to a filter;

an error amplifier configured to provide an error signal at least in part using a difference between a first reference voltage and an output of the filter;

a first comparator configured to compare the error signal with the ramp signal;

control logic configured to control a state of the switch in response to an output signal from the first comparator;

a second comparator configured to compare the output of the filter with a second reference voltage; and

wherein the ramp generator is configured to reset the ramp signal to a specified state in response to an output signal from the second comparator.

2. The regulator circuit of claim 1, wherein the switch comprises at least one transistor selected from the list including a bipolar junction transistor, a field-effect transistor, or an insulated gate bipolar transistor.

3. The regulator circuit of claim 1, wherein the control logic is configured to inhibit the ramp generator from resetting the ramp signal when the switch is in a conducting state. 4. The regulator circuit of claim 1, wherein the filter comprises:

a shunt rectifier;

a shunt capacitor;

a series inductor coupled between the shunt rectifier and shunt capacitor; wherein the switch is connected between an input power source and the shunt rectifier and configured provide input power from the input power source to the shunt rectifier; and wherein the output of the filter includes a node connecting the series inductor and the shunt capacitor;

5. The regulator circuit of claim 1, wherein the first reference voltage is greater than the second reference voltage.

6. The regulator circuit of claim 1, wherein at least one of the first or second reference voltages is provided at least in part using a precision voltage reference circuit.

7. The regulator circuit of claim 6, wherein the precision voltage reference circuit and one or more of the first comparator, the second comparator, the switch, the control logic, the ramp generator, or the error amplifier are configured to be included together in a single integrated circuit package.

8. The regulator circuit of claim 1, wherein at least one of an error amplifier input or a second comparator input are connected to the output the filter using a divider configured to provide a signal proportional to a voltage at the output. 9. The regulator circuit of claim 1, comprising:

an input power source configured to supply the input power;

a current sense amplifier configured to sense a current through the switch; and

wherein the first comparator is configured to compare an output of the current sense amplifier with the ramp signal.

10. The regulator circuit of claim 9, wherein the first comparator is configured to compare a sum of the output of the current sense amplifier and the error signal with the ramp signal.

11. The regulator circuit of claim 1, wherein the ramp generator is configured to generate a periodic ramp signal at least in part using a clock generator, and wherein the ramp generator is configured to reset the ramp signal to the specified state asynchronously to the clock generator.

12. A method, comprising:

comparing an output of a filter to a first reference voltage and separately, to a second reference voltage;

determining an error signal using the comparing the output of the filter to the first reference voltage ;

generating a ramp signal;

comparing the ramp signal to the error signal;

controlling a state of a switch using the comparing the ramp signal to the error signal, wherein the switch is configured to provide input power to the filter; and

controllably resetting the ramp signal to a specified state using the comparing the output of the filter to the second reference voltage.

13. The method of claim 12, comprising inhibiting the resetting the ramp signal when the switch is in a conducting state.

14. The method of claim 12, wherein the first reference voltage is greater than the second reference voltage. 15. The method of claim 12, comprising generating at least one of the first or second reference voltages at least in part using a precision voltage reference circuit.

16. The method of claim 15, wherein the comparing the output of a filter to the first reference voltage includes using a first comparator;

wherein the comparing the output of the filter to the second reference voltage includes using a second comparator;

wherein the comparing the ramp signal to the error signal includes using an error amplifier;

wherein the controlling the state of the switch includes using control logic; wherien the generating the ramp signal includes using a ramp generator; and wherein the method comprises providing an integrated circuit package including the precision voltage reference circuit together with one or more of the first comparator, the second comparator, the switch, the control logic, the ramp generator, or the error amplifier.

17. The method of claim 12, wherein the output filter includes an output having an output node voltage;

wherein the method comprises providing a signal proportional to the output node voltage; and

wherein at least one of the comparing the output of the filter to the first reference voltage or the comparing the output of the filter to the second reference voltage includes using the signal proportional to the output node voltage.

18. The method of claim 12, comprising:

sensing a current flowing through the switch when the switch is in a conducting state;

determining a voltage proportional to the current;

comparing the ramp signal to the voltage proportional to the current; and controlling the state of the switch using the comparing the ramp signal to the voltage proportional to the current.

19. The method of claim 12, wherein the generating the ramp signal includes generating a periodic ramp signal; and

wherein the controllably resetting the ramp signal includes resetting the ramp signal asynchronously to a period of the ramp signal.

20. The method of claim 19, comprising generating a clock signal;

wherein the generating the periodic ramp signal includes using the clock signal; and

wherein the controllably resetting the ramp signal includes resetting the ramp signal asynchronously to the clock signal.

Description:
SWITCHED-MODE PWM REGULATOR

WITH RAMP RESET

CROSS REFERENCE TO RELATED APPLICATION

Benefit of priority is claimed to U.S. Provisional Patent Application

Serial Number 61/263,879 , entitled "SWITCHED-MODE PWM REGULATOR WITH RAMP RESET," filed on November 24, 2009 (Attorney Docket No. 2921.008PRV), the entirety of which is herein incorporated by reference. BACKGROUND

Electronic circuitry can be sensitive to variations in power supply voltage. Thus, a regulated power supply can be used to provide operating energy for electronic circuitry by regulating or adjusting an input power signal to provide output power within a specified output voltage range. A regulated power supply can include a DC-DC regulator. In an example, the DC-DC regulator can receive a DC input and provide a regulated, relatively stable DC output across different load conditions, including sudden or transient changes in load current.

In an example, to maintain a regulated DC output voltage, the DC-DC regulator can provide an increased output current when the load current demand increases. In certain examples, the output voltage of the regulator can droop if the increased current demand is not met. Drooping can refer to the regulator failing to provide an output within the specified output voltage range. Drooping, or loss of regulation, can cause unwanted behavior in electronic circuitry, including one or more unwanted resets, glitches, noise, or one or more other behaviors.

In certain power supplies, feedback can be used to help maintain the output voltage within the specified range. In an example, a "linear" regulator can include a shunt or series transistor operating in a partially conductive or linear region to modulate a current supplied by the regulator, such as in response to changing load conditions. In certain examples, the transistor can be controlled by feedback circuitry, such as one or more operational amplifiers, to further improve the transient response and regulation performance of the regulator. In the linear regulator, excess current not needed by the load can be diverted away from the load and dissipated elsewhere (e.g., as heat). The linear regulator can thus achieve reasonable levels of regulation performance, but at relatively high costs in terms of size, complexity, or efficiency, compared other regulators, such as a switched-mode regulator. For example, in a linear regulator, the series or shunt transistor must be able to operate continuously at the maximum rated supply current of the regulator, necessitating a relatively large shunt or series transistor as compared to correspondingly-rated switched-mode supply.

OVERVIEW

In certain examples, a regulator circuit can include a ramp generator configured to provide a ramp signal, a switch configured to provide input power to a filter, an error amplifier configured to provide an error signal at least in part using a difference between a first reference voltage and an output of the filter, a first comparator configured to compare the error signal with the ramp signal, control logic configured to control a state of the switch in response to an output signal from the first comparator, a second comparator configured to compare the output of the filter with a second reference voltage. The ramp generator can be configured to reset the ramp signal to a specified state in response to an output signal from the second comparator.

This overview is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

FIG. 1 illustrates generally an example of a PWM regulator. FIG. 2 illustrates generally an example of a PWM regulator including a ramp reset.

FIG. 3 illustrates generally an example of a reset control circuit.

FIG. 4 illustrates generally an illustrative example of various signals, such as provided by the PWM regulator of FIG. 1, when the regulator is supplying a relatively constant output current.

FIG. 5 illustrates generally an illustrative example of various signals, such as provided by the PWM regulator of FIG. 1, when the regulator encounters an abrupt increase in output current demand.

FIG. 6 illustrates generally an illustrative example of various signals, such as provided by the PWM regulator of FIG. 2, when the regulator encounters an abrupt increase in output current demand.

FIG. 7 illustrates generally an illustrative example of a comparison between a reset signal and ramp signal such as provided by the PWM regulator of FIG. 1, and a reset signal and a ramp signal such as provided by the PWM regulator of FIG. 2.

FIG. 8 illustrates generally an example of a method of regulating an output.

DETAILED DESCRIPTION

In an example, a switched-mode regulator, instead of operating a shunt or series transistor in a linear region of conduction, can be connected to input power selectively by a transistor, or one or more other switches. For example, the switch can be toggled rapidly between a fully-conducting on-state and a nonconducting off-state (e.g., switching between saturation or cut-off states). In an example, the switch can be controlled using voltage or current feedback in order to provide a desired time-averaged power to a load.

In certain examples, a switched-mode regulator can use pulse-width modulation (PWM) to control the on-time of the switch connected to an unregulated DC input. In an example, the switch can selectively connect an output of the PWM regulator to the unregulated input, such as through an inductor. In certain examples, a filter can be used to reduce, suppress, or reject high frequency transient signals present at the output, including transient signals caused by cycling the switch.

In certain examples, a comparator can be used to drive the input of the switch. In an example, a pulse width of a signal provided by the comparator can control the on-time of the switch. In certain examples, a ramp generator output can drive one input of the comparator. In an example, the ramp generator can provide a periodic ramp signal to be compared with another signal, such as an error signal. In an example, the error signal can be derived from an

instantaneous output voltage of the regulator. In an example, the error signal can be proportional to a difference between the instantaneous output voltage of the regulator and a desired output voltage. In an example, the error signal can include a comparison between a voltage proportional to the instantaneous output voltage, and a reference voltage. In this manner, the on-time of the output switch can be increased proportionally to a drop in output voltage. In an example, the comparator can adjust the pulse width of the of a control signal to the switch using the error signal and the ramp signal.

In an example, the control signal can turn on the switch for an interval corresponding to the pulse width of the control signal. In certain examples, this cycle can be repeated periodically at a rate corresponding to frequency (or inversely, the period) of the ramp signal. In an example, a new variable- width pulse can be generated as the control signal once for each new cycle in the ramp signal. In an example, the comparator can increase a pulse-width of the control signal to the switch, such as when the error signal reflects a difference between the instantaneous output voltage and the desired output voltage. In an example, an abrupt increase in load current can cause the error signal to increase abruptly.

In certain examples, load current demand can increase during the middle of a ramp signal cycle. In an example, the regulator can delay a pulse- width increase or a turn on of the output switch until the beginning of the next ramp cycle. In this example, the output switch will not be turned on until at least until the beginning of a new cycle of the ramp signal. Thus, in this example, an unwanted transient in the output voltage, such as a droop, can be worsened. In certain examples, one or more ramp signal parameters can be varied, such as to lessen the unwanted transient. For example, a ramp rate (e.g., a slew rate of a ramping portion), a period, a duty cycle, or one or more other parameters can be varied by the PWM regulator. The present inventor has recognized, among other things, that resetting the ramp signal to a specified state can be simpler than varying other ramp signal parameters, such as the ramp signal ramp rate. In an example, resetting a ramp signal to a specified state can improve a PWM switched- mode regulator' s response to an abrupt increase in load current.

Further, the present inventor has recognized, among other things, that the PWM regulator including a ramp reset can recover to a desired output voltage range more rapidly after an abrupt increase in load current demand than a regulator having no ramp signal reset. In certain examples, a second

comparator, such as a ramp oscillator reset comparator, can compare a second reference voltage to a voltage proportional to the instantaneous output voltage of the regulator. In an example, the ramp oscillator reset comparator can reset the ramp signal asynchronously and the output switch can be switched on nearly immediately. In an example, the regulator can supply increased current, such as by turning on the output switch almost immediately when the output voltage drops abruptly below a threshold, rather than delaying until the beginning of the next ramp cycle. In an example, the threshold can be set by a second voltage reference, or by one or more other references.

FIG. 1 illustrates generally an example of a PWM regulator 100

configured to provide an output voltage, Vout, to a load 145. In the example of FIG. 1, the regulator 100 includes a reference 125, an error amplifier 115, a clock and ramp generator 105, a comparator 110, a control logic circuit 120, a switch 140, and a filter 130. In an example, the filter 130 can include a series inductor 136, a shunt rectifier 132, a shunt capacitor 134, or one or more other components.

In certain examples, voltage feedback can be used to control the state of the switch 140. In an example, a feedback connection 185 can provide a voltage to an input to the error amplifier 115 from the output voltage node, Vout, such as through a voltage divider. In an example, the feedback connection 185 can provide a voltage proportional to the output voltage, Vout, such as using a divider circuit as shown in FIG. 1. In certain examples, current feedback can be used to control the state of the switch 140, in addition to or instead of one or more other forms of feedback, such as voltage feedback. In an example, a current sense amplifier 198 can be configured to monitor current supplied by the switch 140, such as for monitoring a current through the switch 140. In this example, the current sense amplifier 198 can provide an output signal to a summing amplifier 199. In an example, the summing amplifier 199 can add the current sense output signal to an error signal 175 from the error amplifier 115, such as to provide an input to the comparator 110. In this example, both voltage and current feedback can be used to control the state of the switch 140. In an example, the control logic 120 can selectively toggle the switch 140 between a conducting on-state, or a nonconducting off- state.

In an example, the switch 140 can be toggled on and off, such as to deliver a desired time-averaged power to the load 145, at a specified voltage range. In an example, the switch 140 can be connected to an unregulated input node, Vin. In certain examples, a battery, a rectified output from a transformer, a voltage from a prior regulator stage, or one or more other sources can supply Vin.

In an example, the clock and ramp generator 105 can supply two or more signals, including a switch reset signal 160, and a ramp signal 165. In this example, both the switch reset signal 160 and the ramp signal 165 include the same constant period, such as determined by a clock signal from an oscillator included in the clock and ramp generator 105. In certain examples, the clock and ramp generator 105 can supply one or more other ramp or clock signals. In certain examples, the switch reset signal 160 can notify control logic to reset the switch 140 to a specified state, such as at the beginning of each clock cycle, such as either an on-state or an off-state. FIGS. 4, 5, and 7 include illustrative examples of the switch reset signal 160 and the ramp signal 165, such as provided by the clock and ramp generator 105.

In certain examples, the ramp signal 165 and the error signal 175 can be provided to the comparator 110. In this example, the comparator 110 can provide a PWM output 155 to the control logic 120, or to one or more other portions of the PWM regulator 100. In certain examples, the error amplifier 115 can provide a pulse including a pulse width proportional to the magnitude of the error signal 175.

In an example, the control logic 120 can then use the PWM output 155 to provide an output drive signal 150 to the switch 140 to turn on the switch 140, such as for a duration proportional to the PWM output 155 pulse width. In certain examples, the switch 140 can be an NMOS device, or one or more other devices, and control logic 120 can be configured to condition the PWM output 155 to a specified polarity and voltage range to control the switch 140.

FIG. 2 illustrates generally an example of a PWM regulator 200

including a ramp reset 295. The regulator 200 can provide an output voltage, Vout, to a load 245. In the example of FIG. 2, the regulator 200 can include a first reference 225, a second reference 280, an error amplifier 215, a clock generator 207, a ramp generator 206, a first comparator 210, second comparator 290, a control logic circuit 220, a switch 240, and a filter 230. In an example, the filter 230 can include a series inductor 236, a shunt rectifier 232, and a shunt capacitor 234, or one or more other components.

In certain examples, voltage feedback can be used to control the state of the switch 240. In an example, a feedback connection 285 can provide a voltage to an input to the error amplifier 215 from the output voltage node, Vout, such as through a voltage divider, or through one or more other filters, dividers, amplifiers, or connections. In an example, the feedback connection 285 can provide a voltage proportional to the output voltage, Vout, or proportional to one or more other voltages.

In certain examples, current feedback can be used to control the state of the switch 240, in addition to or instead of one or more other forms of feedback, such as voltage feedback. In an example, a current sense amplifier 298 can monitor current supplied by the switch 240, such as monitoring a current through the switch 240. In this example, the current sense amplifier 298 can provide an output signal to a summing amplifier 299. In an example, the summing amplifier 299 can add the current sense amplifier output signal to an error signal 275 from the error amplifier 215, such as to provide an input to the first comparator 210. In an example, a precision voltage reference circuit can provide the first and second references 225, 280, such as using a band-gap circuit, or one or more other circuits, components, or references. In an example, a magnitude of a first reference 225 voltage, Vrefl, can be greater than a magnitude of a second reference 280 voltage, Vref2. In an example, the second reference 280 can be proportional the first reference 225, such as a second reference 280 voltage, Vref2 = X * Vrefl, where X can be less than 1.0 and greater than zero, or using one or more other relationships, differences, ratios, proportions, or the like.

In certain examples, one or more of the first reference 225, the second reference 280, the first comparator 210, the second comparator 290, the error amplifier 215, the clock generator 207, the ramp generator 265, the control logic 220, the switch 240, the current sense amplifier 298, the summing amplifier 299, the filter 230, or one or more other components or devices can be included together in a single assembly, such as co-integrated together within a single integrated circuit package, on or within a single integrated circuit die, within a multi-chip module, or in one or more other integrated packages or assemblies.

In certain examples, the control logic 240 can be toggled on and off, such as to deliver a desired time-averaged power to the load 245, within a specified voltage range. In an example, the switch 240 can be connected to an

unregulated input node, Vin. In certain examples, a battery, a rectified output from a transformer, a voltage from a prior regulator stage, or one or more other sources can supply Vin.

In certain examples, the clock generator 207 can supply a switch reset signal, or one or more other signals. In an example, the control logic 220 can reset the switch 240 to a non-conducting off- state, such as in response to the switch reset signal. In an example, the clock generator 207 can control the frequency (and period) of the switch reset signal 260. In certain examples, the clock generator 207 can include one or more oscillators, such as to generate the switch reset signal 260 including a constant pulse repetition rate. In an example, a coupling 261 can provide one or more signals to the ramp generator 206. In certain examples, the ramp generator 206 can use the one or more signals provided by coupling 261 to provide a reference period or frequency for the ramp signal 265. In certain examples, one or more portions, parts, or components of the ramp generator 206 and clock generator 207 can be combined, such as shown in the example of FIG. 3.

In certain examples, the ramp signal 265 and the error signal 275 can be provided to the first comparator 210. In this example, the first comparator 210 can provide a PWM output 255 to the control logic 220. In certain examples, the PWM output 255 can include, during each clock cycle, a pulse including a pulse width proportional to the magnitude of the error signal 275.

In an example, the control logic 220 can use the PWM output 255 to provide an output drive signal 250 to the switch 240 to turn on the switch 240, such as for a duration proportional to the PWM output 255 pulse width. In the example shown in FIG. 2, the switch 240 can be an NMOS device, or one or more other devices. In certain examples, the control logic 220 can be configured to condition the PWM output 255 to a specified polarity and voltage range to control the switch 240, such as shown in the example of FIG. 3.

In an example, the control logic 220 can include an S/R latch including

SET and RESET inputs, and a Q output. In an example, the switch reset signal 260 can be coupled to the SET input (e.g. "S"), the PWM output 255 can be coupled to the RESET (e.g. "R") input, and the non-inverted output ("Q") can be used at least in part for the switch drive signal 250. In certain examples, the switch 240 can include one or more other types of components or devices, such as one or more NMOS, PMOS or junction field-effect transistors (FETs), one or more insulated gate bipolar transistors (IGBTs), one or more bipolar junction transistors (BJTs), or one or more other mechanical or solid-state switches.

The present inventor has recognized, among other things, that the reset or ramp signals 260, 265 can be reset to an initial state, such as asynchronously to the clock cycle. For example, the period of the switch reset signal 260 or the ramp signal 265 can be shortened, such as to start a new clock cycle

asynchronously to a previous clock cycle. In certain examples, the second comparator 290 can be used as an "oscillator reset comparator," such as to provide a ramp reset 295 to the control logic 220, or one or more other signals.

In an example, the existing ramp signal 265 and switch reset signal 260 can be interrupted by the ramp reset 295, such as by the control logic 220, using one or more signals sent over the coupling 262 or coupling 261. In an example, the ramp signal 260 can be reset to a specified state, such as back to an initial ramp signal state, when the ramp reset 295 is asserted. In certain examples, the switch reset signal 260 can issue a switch reset pulse, such as in response to the ramp reset 295, or one or more other signals. In an example, the feedback signal 285 can decrease, such as when the load 245 current increases abruptly. In an example, the ramp reset 295 can be asserted, such as when the feedback signal 285 drops below a voltage indicated by the second reference 280, or in response to one or more other events.

In certain examples, the ramp signal 265 can include a constant ramp rate (e.g., a constant slew rate), but can be reset by reaching a specified level, or in response to the ramp reset 295. In an example, the control logic 220 can reset one or more of the ramp generator 206 or the clock generator 207, such as in response to a signal from the second comparator 290, as shown in the examples of FIGS. 3, and 6-8. While the example of FIG. 2 includes a series inductor 236, the present inventor contemplates examples of other regulator 200

configurations within the scope of the present subject matter, such as those including more than one switch 240, or one or more other filter 230

configurations.

FIG. 3 illustrates generally an example of a ramp reset control circuit 300. In certain examples, the ramp reset control circuit 300 can be included as a portion, part, or component of the regulator 200 shown in FIG. 2, such as including one or more portions, parts, or components of the ramp generator 206, the clock generator 207, or the control logic 220, or one or more other circuits or devices. The reset control circuit 300 of FIG. 3 can include a first one shot 303 triggered by a comparator, a second one shot 301 including a first trigger 355 and a second trigger 395, an "or" gate 307, an integrating capacitor 311, and a reset switch 309. In an example, a switch reset signal 360, can be used to reset the switch 309, or can be used elsewhere in a PWM regulator, such as for the switch reset signal 260 shown in FIG. 2.

In certain examples, the integrating capacitor 311 can be charged by a constant current source to provide a constant ramp rate (e.g., a constant slew rate) ramp signal 365. The ramp signal 365 can be compared with a reference input 325, or one or more other signals. For example, when the ramp signal 365 exceeds the reference input 325, the first one shot 303 can be triggered (e.g., to produce a single pulse having a specified duration), and can thus trigger the reset switch 309 via the "or" gate 307. In this manner, the ramp signal 365 can be periodic, such as having a constant frequency, period, ramp rate, or peak amplitude, such as determined in part by the reference input 325. In certain examples, one or more other techniques or circuits can be used to generate the ramp signal 365.

The present inventor has recognized, among other things, that when certain conditions occur, such as shown and discussed in the example of FIG. 2, the ramp signal can be reset to an initial state prior to reaching a peak amplitude, such as using the second one shot 301. In certain examples, the first trigger 355 can be coupled to a second comparator output, such as the ramp reset 295 from the second comparator 290 of FIG. 2. In certain examples, the second trigger 395 can be coupled to a first comparator output, such as the PWM output 255 of FIG. 2. In an example, the second one shot 301 can include logic configured to trigger a one shot output pulse (e.g., a reset) to the "or" gate 307, such as to trigger the reset switch 309 asynchronously. In an illustrative example, the one shot 301 can be configured to operate according to Table 1, below.

Table 1. Illustrative Example of One Shot 301 Logic Truth Table

First Trigger 355 Second Trigger 395 One Shot 301 Output (e.g., Reset Comparator Output) (e.g., PWM Output)

Asserted - Asserted - Trigger One Shot (Reset)

Feedback voltage less than second Error signal voltage less

reference voltage. than instantaneous ramp

signal voltage.

Asserted - Not Asserted - Do Not Trigger One Shot

Feedback voltage less than second Error signal voltage

reference voltage. greater than instantaneous

ramp signal voltage.

Not Asserted - Don't Care Do Not Trigger One Shot - feedback voltage greater than (e.g., fixed-frequency switch second reference voltage. reset operation)

In an example, the one shot 301 can operate according to Table 1, such as to inhibit resetting the ramp signal 365, or asserting the switch reset signal 360, when the PWM regulator output switch, such as the switch 240 of FIG. 2, is already turned on.

FIG. 4 illustrates generally an illustrative example of various signals 400, such as provided by the PWM regulator of FIG. 1, such as when the regulator is supplying a relatively constant output current 445. In an example, a switch reset signal 460 can include one or more periodic switch reset pulses, such as to set or reset a state of a PWM output switch, such as using the switch reset signal 160 from the example of FIG. 1. In this example, the PWM switch can include the switch 140 from the example of FIG. 1. In this example, the period between successive switch reset pulses can be the same as the period of a ramp signal, such as the ramp signal 165 of the example of FIG. 1.

In an example, a first comparator output signal 455 can include a pulse corresponding to an instantaneous comparison between the ramp signal and an error signal, such as the error signal 175 and PWM output 155 of FIG. 1. In this example, the pulse width of the low (e.g., "0V") portion of the first comparator output signal can be proportional to a magnitude of the error signal. In an example, a larger error signal can correspond to a longer pulse- width, such as up to a limit of the period of the switch reset signal. A switch control signal 450 can be derived from the first comparator output signal 455, such as the output drive signal 150 of the example of FIG. 1.

In an example, when the output drive signal 150 is asserted (e.g., at about "Vin"), the switch can be conducting. In this example, a duty cycle of the switch can be proportional to the magnitude of the error signal. In an illustrative example, the switch control signal 450 can be used to generate an output inductor current 436, and a corresponding AC-coupled output voltage, Vout(ac). In this illustrative example, the output current 436 can be the output current through the inductor 136, and Vout(ac) can be the AC-coupled voltage at the output node, Vout, such as shown in the example of FIG. 1.

FIG. 5 illustrates generally an illustrative example of various signals 500, such as provided by the PWM regulator of FIG. 1, and similar to FIG. 4. In this illustrative example, an output current demand 545 abruptly increases, rather than remaining constant. In this example, the increase in output current demand occurs in the middle of a switch reset signal 560 period. In certain examples, an interval between switch reset pulses can be similar to a ramp signal period, such as the ramp signal 165 of the example of FIG. 1.

Similar to the example of FIG. 4, in this example, the first comparator output signal 555 can be low during the beginning of the cycle, and the switch control signal 550 can be used to turn on the switch during the low portion of the first comparator output signal 555. In this example, an inductor output current 536 can be increases when the switch control signal 550 is high (e.g., asserted). However, since the switch is turned off later in the cycle, the inductor output current 536 decreases, even though the output current demand 545 is increasing. In this example, the inductor output current 536 decreases more rapidly as the output current demand 545 increases, causing a corresponding negative-going spike in the AC-coupled output voltage, Vout(ac), and a continued gradual decrease in Vout(ac) thereafter.

In this example, since the switch reset signal 560 period is fixed, the switch remains off at least until the beginning of the next ramp signal period. This delay can cause the PWM output to fall below a specified output voltage threshold 525. The present inventor has recognized, among other things, that an output voltage decrease below the specified output voltage threshold 525 can be undesirable and a speed of recovery of regulation can be limited by the period of the ramp signal (and the corresponding switch reset signal 560 period).

FIG. 6 illustrates generally an illustrative example of various signals 600, such as provided by the PWM regulator of FIG. 2, such as when the regulator encounters an abrupt increase in output current demand 645. A switch reset signal 660 can include a fixed period such as shown in the example FIG. 4, during steady- state operation (such as according the truth table discussed with respect to the example of FIG. 3).

However, in this illustrative example, when the output current demand 645 increases abruptly, an asynchronous switch reset pulse 661 can be provided. In certain examples, a corresponding first comparator output signal 655 pulse can be generated during or after the switch reset pulse. In certain examples, an asynchronous reset pulse can be triggered when the AC-coupled output voltage, Vout(ac), of the regulator remains below a specified threshold 680 for a specified duration, such as established by the second voltage reference 280 of FIG. 2.

In certain examples, spurious output transients can be ignored, such as by selecting the specified duration so that the asynchronous reset pulse 661 is inhibited for very short duration transient events. In certain examples, the very short duration transient events can include an inductive voltage transient, such as shown in the AC-coupled output voltage 680.

In certain examples, the switch reset signal 660 can have a non-fixed period, such as to increase the inductor output current 636 almost immediately, rather than waiting for a switch reset to occur according to a fixed period. This can reduce the magnitude or duration of droop in the AC-coupled output voltage, Vout(ac), as compared to the fixed-period reset signal 560 of the example of FIG. 5. In certain examples, the switch reset signal 660 can be the switch reset signal 260, the first comparator output signal 655 can be the PWM output 255, the inductor current can be the current through the inductor 236, and the AC- coupled output voltage can be the AC voltage at Vout, such as shown in FIG. 2. In certain examples, the switch reset signal 660 can be generated, such as by the clock generator 207 in response to the control logic 220, when the ramp reset 295 is asserted, such as shown in FIG. 2. FIG. 7 illustrates generally an illustrative example of a comparison 700 between a switch reset signal 760A and ramp signal 762A such as provided by the PWM regulator of FIG. 1, and a switch reset signal 760B and a ramp signal 762B such as provided by the PWM regulator of FIG. 2. The switch reset and ramp signals 760A, 762A can correspond to a fixed-frequency PWM regulator, such as shown and discussed in FIGS. 1 and 5, and with respect to the steady- state example of FIG. 4.

In this example, the ramp signal 762A can have a constant ramp rate, and the period of the ramp signal 762A can be determined in relation to the peak voltage of the ramp signal 762A. For example, the ramp signal 762A can cycle back from VREF to 0V at the end of each fixed period when the ramp signal 762A reaches a voltage at or below VREF, resulting in a saw-tooth ramp signal 762A shown in FIG. 7. In this example, a switch reset signal 760A can include a reset pulse at the beginning or end of each cycle of the ramp signal 762A.

The reset and ramp signals 760B, 762B can correspond to a non-fixed frequency PWM regulator, such as shown and discussed in FIGS. 2, 6, and 8. In certain examples, the ramp rate of the ramp signal 762B can be the same as the ramp signal 762A. However, the ramp signal 762B can be reset to specified state asynchronously to an original period of the ramp signal and switch reset signals, such as shown by signals 760A, 762A. In certain examples, the ramp signal 762B can be reset in response to an abrupt increase in load current, such as shown in the example of FIG. 6. In an example, the ramp signal can return to a specified state of about zero volts (e.g., 0V) when reset, such as shown in the ramp signal 762B of FIG. 7.

FIG. 8 illustrates generally an example of a method 800 for regulating an output, such as the output voltage, Vout, shown in the example of FIG. 2.

At 802, an output of a filter can be compared to a first reference and separately, to a second reference. The filter can include, for example, the filter 230, the first reference 225, or the second refer 280, such as shown in FIG. 2, or one or more other filters.

At 804, an error signal can be determined using the comparing the output of the filter to the first reference. At 806, a ramp signal can be generated, such as using one or more of the ramp generator 206 or the clock generator 207, or the ramp reset circuit 300, such as shown in the examples of FIGS. 2-3.

At 808, the ramp signal can be compared to the error signal, such as the error signal 275 shown in FIG. 2. At 810, a state of a switch can be controlled using the comparing the ramp signal to the error signal. In certain examples, the controlling the state of the switch can include using a switch 240, driven by control logic 220, such as shown in FIG. 2.

At 812, the ramp signal can be controllably reset to a specified state using the comparing the out of the filter to the second reference voltage, such as using one or more of the ramp generator 206, the clock generator 207, the control logic 220, or the ramp reset circuit 300 as shown in the examples of

FIGS. 2-3.

Additional Notes

Example 1 includes subject matter (such as an apparatus) comprising a ramp generator configured to provide a ramp signal, a switch configured to provide input power to a filter, an error amplifier configured to provide an error signal at least in part using a difference between a first reference voltage and an output of the filter, a first comparator configured to compare the error signal with the ramp signal, control logic configured to control a state of the switch in response to an output signal from the first comparator, a second comparator configured to compare the output of the filter with a second reference voltage, and the ramp generator can be configured to reset the ramp signal to a specified state in response to an output signal from the second comparator.

In Example 2, the subject matter of Example 1 can optionally include a switch comprising at least one transistor selected from the list including a bipolar junction transistor, a field-effect transistor, or an insulated gate bipolar transistor.

In Example 3, the subject matter of one or any combination of Examples 1-2 can optionally include control logic configured to inhibit the ramp generator from resetting the ramp signal when the switch is in a conducting state.

In Example 4, the subject matter of one or any combination of Examples 1-3 can optionally include a filter comprising a shunt rectifier, a shunt capacitor, a series inductor coupled between the shunt rectifier and shunt capacitor, the switch connected between an input power source and the shunt rectifier and configured provide input power from the input power source to the shunt rectifier, and the output of the filter including a node connecting the series inductor and the shunt capacitor.

In Example 5, the subject matter of one or any combination of Examples

1-4 can optionally include a first reference voltage greater than the second reference voltage.

In Example 6, the subject matter of one or any combination of Examples 1-5 can optionally include at least one of the first or second reference voltages provided at least in part using a precision voltage reference circuit.

In Example 7, the subject matter of one or any combination of Examples 1-6 can optionally include a precision voltage reference circuit and one or more of the first comparator, the second comparator, the switch, the control logic, the ramp generator, or the error amplifier, configured to be included together in a single integrated circuit package.

In Example 8, the subject matter of one or any combination of Examples 1-7 can optionally include at least one of an error amplifier input or a second comparator input connected to the output the filter using a divider configured to provide a signal proportional to a voltage at the output.

In Example 9, the subject matter of one or any combination of Examples

1-8 can optionally include an input power source configured to supply the input power, a current sense amplifier configured to sense a current through the switch, the first comparator configured to compare an output of the current sense amplifier with the ramp signal.

In Example 10, the subject matter of one or any combination of

Examples 1-9 can optionally include a first comparator configured to compare a sum of the output of the current sense amplifier and the error signal with the ramp signal.

In Example 11, the subject matter of one or any combination of

Examples 1-10 can optionally include a ramp generator configured to generate a periodic ramp signal at least in part using a clock generator, the ramp generator configured to reset the ramp signal to the specified state asynchronously to the clock generator. Example 12 can include, or can optionally be combined with the subject matter of one or any combination of Examples 1-11 to include, subject matter (such as a method, a means for performing acts, or a machine-readable medium including instructions that, when performed by the machine, cause the machine to perform acts) comprising comparing an output of a filter to a first reference voltage and separately, to a second reference voltage, determining an error signal using the comparing the output of the filter to the first reference voltage, generating a ramp signal, comparing the ramp signal to the error signal, controlling a state of a switch using the comparing the ramp signal to the error signal, the switch configured to provide input power to the filter, and

controllably resetting the ramp signal to a specified state using the comparing the output of the filter to the second reference voltage.

In Example 13, the subject matter of Example 12 can optionally include inhibiting resetting the ramp signal when the switch is in a conducting state.

In Example 14, the subject matter of one or any combination of

Examples 12-13 can optionally include a first reference voltage greater than the second reference voltage.

In Example 15, the subject matter of one or any combination of

Examples 12-14 can optionally include generating at least one of the first or second reference voltages at least in part using a precision voltage reference circuit.

In Example 16, the subject matter of one or any combination of

Examples 12-15 can optionally include comparing the output of a filter to the first reference voltage using a first comparator, comparing the output of the filter to the second reference voltage using a second comparator, comparing the ramp signal to the error signal using an error amplifier, controlling the state of the switch using control logic, generating the ramp signal using a ramp generator, and providing an integrated circuit package including the precision voltage reference circuit together with one or more of the first comparator, the second comparator, the switch, the control logic, the ramp generator, or the error amplifier.

In Example 17, the subject matter of one or any combination of

Examples 12-16 can optionally include using an output filter including an output having an output node voltage, providing a signal proportional to the output node voltage, and at least one of comparing the output of the filter to the first reference voltage or comparing the output of the filter to the second reference voltage including using the signal proportional to the output node voltage.

In Example 18, the subject matter of one or any combination of

Examples 12-17 can optionally include sensing a current flowing through the switch when the switch is in a conducting state, determining a voltage proportional to the current, comparing the ramp signal to the voltage

proportional to the current, controlling the state of the switch using the comparing the ramp signal to the voltage proportional to the current.

In Example 19, the subject matter of one or any combination of

Examples 12-18 can optionally include generating the ramp signal including generating a periodic ramp signal, and controllably resetting the ramp signal including resetting the ramp signal asynchronously to a period of the ramp signal.

In Example 20, the subject matter of one or any combination of

Examples 12-19 can optionally include generating a clock signal, the generating the periodic ramp signal including using the clock signal, and the controllably resetting the ramp signal including resetting the ramp signal asynchronously to the clock signal.

In Example 21, a system or apparatus can include, or can optionally be combined with any portion or combination of any portions of any one or more of Examples 1-20 to include, means for performing any one or more of the functions of Examples 1-20, or a machine -readable medium including instructions that, when performed by a machine, cause the machine to perform any one or more of the functions of Examples 1-20.

The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." Such examples can include elements in addition to those shown or described.

However, the present inventor also contemplates examples in which only those elements shown or described are provided. Moreover, the present inventor also contemplates examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

The above description is intended to be illustrative, and not restrictive.

For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. ยง 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.