BACKGROUND

This specification relates to DC-DC converters.

Converters for converting a first DC voltage to a second DC voltage are availing for a wide range of applications. Switched capacitor converters (SCC) are one example. A conventional SCC include multiple flying capacitors and switches. Input and output bulk capacitors are also typically required for power buffering and energy storage. The switches are typically controlled with a certain switching frequency, and multiple switching states are used to transfer power from an input to an output through charging and discharging flying capacitors. A SCC usually has a constant voltage conversion ratio and can support bidirectional power conversion.

Some SCC's also use inductor components to set certain resonant frequencies for switching. By driving the switches at resonant frequencies of the resulting charging and discharging circuits Zero Current Switching (ZCS) can be achieved.

SUMMARY

In general, one innovative aspect of the subject matter described in this specification is embodied in a device that includes a plurality of resonant tanks, each resonant tank including at least one resonant inductor and one resonant capacitor and having respective first and second nodes that are connected to respective circuit nodes in a circuit: a plurality of switches, each switch having first and second terminals and an input that receives a control signal that places the switch in either an open state in which a conduction path is established between the first and second terminals, or a closed state in which the conduction path is eliminated between the first and second terminals, and each first terminal and each second terminal connected to a respective circuit node in the circuit; one or more non-resonant capacitors having respective first and second nodes, and wherein each non-resonant capacitor has at least a first node connected to a circuit node formed by a connection of two switches that are each respectively connected to a respective resonant tank; and control logic that generates two or more sets of control signal inputs applied to the inputs of the switches so that for each set of control signals: one or more sub-circuit loops are formed, and wherem the one or more sub-circuit loops for a first set of control signals is different from the one or more sub-circuit loops for a second set of control signals, each of the one or more sub-circuit loops includes one or more of the resonant tanks, and at least one of the sub-circuit loops includes at least one non-resonant capacitor, and each of the one or more non-resonant capacitors facilitates clamping of a voltage across the first and second terminals of the switch when the switch is in an open state.

Another innovative aspect of the subject matter described is embodied in a device that includes a plurality of resonant tanks, each resonant tank including at least one resonant inductor and one resonant capacitor and having respective first and second nodes that are connected to respective circuit nodes in a circuit; a plurality of switches, each switch having first and second terminals and an input that receives a control signal that places the switch in either an open state in which a conduction path is established between the first and second terminals, or a closed state in which the conduction path is eliminated between the first and second terminals, and each first terminal and each second terminal connected to a respective circuit node in the circuit; and control logic that generates two or more sets of control signal inputs applied to the inputs of the switches so that for each set of control signals: at least two sub-circuit loops are formed, and wherein the at least two sub-circuit loops for a first set of control signals are different from the at least two sub-circuit loops for a second set of control signals, and at least one circuit node receives respective currents from at least two resonant tanks that are reversed in polarity with respect to each other such that the respective currents substantially cancel each other.

Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. Each indi vidual current conduction sub-circuit loop in a switched tank converter (STC) has an inductive impedance, and each flying capacitor is softly charged and discharged during normal operation due to the di/dt limit of the inductive impedance. This overcomes the inherent weakness of the conventional SCC where large inrush currents can be generated,

instantaneously leading to charge redistribution losses, and resulting in high switching losses and high RMS current losses. When the switches of the STC topology have their drain-to- source voltages (Vds) clamped during the OFF state, parasitic ringing between the resonant inductors and switch junction capacitors is eliminated, thereby reducing the stress on each switch. Additionally, benefitting from the resonant operation of the resonant tanks, the switches of the STC can be controlled in a way such that ZCS is achieved, resulting in very low or negligible switching losses and very high efficiencies relative to circuits that do not have ZCS. A precharger-less duty cycle ramp start and intrinsic droop current sharing for parallel operation provide the control simplicity, modularity and scalability.

The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a circuit diagram of a 1 -phase 4-to-l STC topology with full-wave output rectification.

Fig. 2A is a circuit diagram of a first set of sub-circuit loops of the circuit Fig. 1.

Fig. 2B is a circuit diagram of a second set of sub-circuit loops of the circuit of Fig. 1.

Fig. 2C is a timing diagram of the control input signals for the switches and the current waveforms of the circuits depicted if Fig. 2A and Fig. 2B during charging and discharging states.

Figs. 3A - 3C are circuit diagrams that illustrate clamping of switch voltages during various switch states.

Fig. 4A is a block diagram of a power system architecture including multiple paralleled STCs with a front-end hot swap.

Fig. 4B is a block diagram of two-stage point of load (POL) power conversion architecture that incorporate STCs.

Fig. 5 is a circuit diagram of a 1 -phase 4-to-l STC topology with half-wave output rectification

Fig. 6 is a circuit diagram of another 1 -phase 4-to-l STC topology with half- wave output rectification.

Fig. 7 is a circuit diagram of a 2-phase 4-to-l STC topology with full-wave output rectification. Fig. 8 is a circuit diagram of another 2-phase 4-to-l STC topology with full- wave output rectification.

Fig. 9 is a modified circuit diagram of Fig. 7 to realize reversed polarity power conversion

Fig. 10 is a circuit diagram of a 1 -phase 6-to-l STC topology with full-wave output rectification.

DETAILED DESCRIPTION

The subject matter of this written description relates to a switched tank converter. The switched tank converter (STC) includes multiple flying resonant tanks, and each resonant tank includes at least one resonant inductor and at least one resonant capacitor. The resonant tanks are each connected to two circuit nodes. The switched tank converter also includes one or more flying non-resonant capacitors, and each non-resonant capacitor has at least a first node connected to a circuit node other than ground. Additionally, multiple switches are connected to the circuit nodes. The switches are driven by a control logic that generates two or more sets of control signal inputs applied to the inputs of the switches. For each set of control signals, one or more sub-circuit loops are formed. Each sub-circuit loop for a first set of control signals is different from each sub-circuit loop for a second set of control signals, and each sub-circuit loop includes one or more of the resonant tanks. At least one of the sub-circuit loops includes at least one non-resonant capacitor. Each of the non- resonant capacitors facilitates clamping of a voltage across the switch when the switch is in an open state. Finally, in some implementations, the control logic generates each set of control signals to cause zero current switching in each of the switches.

Fig. 1 is a circuit diagram of a 1 -phase 4-to-l STC topology with full-wave output rectification. The circuit 100 is constructed on or within a circuit bearing structure, such as a printed circuit board, silicon substrate, or any other circuit bearing structure.

The circuit 100 includes a plurality of flying resonant tanks 102 and 104. Each resonant tank includes at least one resonant inductor Lr and one resonant capacitor Cr, and has first and second nodes. In some instances, a resonant inductor in a resonant tank may be a stray inductance of a circuit bearing structure. The circuit 100 also includes one or more flying non-resonant capacitors 106, each with respective first and second nodes. As used in this specification, a non-resonant capacitor is a capacitor that is separate from a resonant tank and does not contribute to the characteristic resonant frequency of the resonant tank itself.

In the example circuit 100, only one non-resonant capacitor 106 is included in the circuit. However, more than one non-resonant capacitor can be used, depending on the topology of the STC circuit. In a particular switching state, each resonant tank can be connected in series or in parallel with a particular non-resonant capacitor, depending on the circuit topology and application. Other example STC circuits will be described with reference to Figs. 5 - 9 below.

In the circuit 100 of Fig. 1, the non-resonant capacitor 106 has a first node connected to a circuit node 110 formed by a connection to switches Q2 and Q3 that are each

respectively connected to a respective resonant tank 102 and 104. In some implementations, the other node of the non-resonant capacitor may be connected to another connected pair of switches that are respectively connected to resonant tanks. In other implementations, the other node of the non-resonant capacitor may be directly connected to ground or may be switched to ground through a switch connection. This latter implementation is shown in Fig. 1, where the non-resonant capacitor is connected to circuit node 114 formed by a connection to switches Q7 and Q8.

A plurality of switches Ql, Q2, Q3, Q4, Q5, Q6, Q7 and Q8 have respective first and second terminals and an input. The input receives a control signal that places the switch in an "off state in which a conduction path is eliminated between the first and second terminals, or an "on" state in which the conduction path is established between the first and second terminals. In the example of Fig. 1 , N-channel MOSFET switches are used.

However, other types of switches can also be used.

During operation, the current flow direction in the switches differentiates the switches into two categories - mam switches and synchronous-rectifier (SR) switches. For the N- Channel MOSFETs of Fig. 1, a main switch has its current flow from drain to source in normal operation, and a SR switch has its current flow from source to drain. Thus, switches Ql - Q4 are main switches, and Q5 - Q8 are the synchronous rectifier (SR) switches. In some applications, SR switches can be replaced by diodes, where the diodes are forward biased in the "on" state and being reversed biased in the "off state. In the circuit of Fig. 1, the main switches are coupled between the input voltage VIN 132 and either the low voltage side VOUT 130 or system ground 136, while the SR. switches are coupled between VOUT 130 and system ground 136. For a step-up STC, the main switches are swapped with the SR. switches. A load 134 is connected to VOUT.

In the circuit of Fig. 1, the switches are divided into two switch groups, and each switch group receives a same input signal at the respective inputs of the switches. The switch groups are respectively identified by the input signals SI and S2 at the switch inputs in Fig. 1. As will be described in more detail with reference to Figs. 2A - 2C below, the first switch group shares the same control signal input from the control logic 150, and the second switch group shares a control signal input from the control logic 150 that is an approximately 180-degree phase shift from the input to the first switch group. The duty cycles for both control signal inputs are the same, or approximately the same.

The sets of control signal inputs applied to the inputs of the switches Q so that two or more respective sub-circuit loops that are different from each other are formed between the STC input node 138 and the STC output node 130. Each sub-circuit loop includes one or more resonant tanks and at least one sub-circuit loops includes one or more non-resonant capacitors. The non-resonant capacitor of the sub-circuit loop also facilitates clamping of a voltage across the terminals of the switch when the switch i s in the open state. The sub- circuit loops resulting from the switching operations in the circuit of Fig. 1 are described in more detail with reference to Figs. 2A and 2B.

In some implementations, the control logic 150 controls the switches such that they are turned on and off at zero current, e.g., zero current switching (ZCS). This ZCS feature reduces switching losses when compared to switching when current is flowing in the switches. Furthermore, the circuit 100 allows larger voltage ripples on the flying resonant capacitors due to the lossless switching feature. Hence, the flying capacitor sizes may be reduced when compared to those that are used in a system that does not have ZCS. In some implementations, the switching may instead occur without ZCS.

The "on" and "off time of each switching state depends on the resonant frequency of the inductors and flying resonant capacitors involved in that particular switching state. Also, as input and output bulk capacitors and flying non-resonant capacitors usually do not participate in the resonance, such capacitors can reasonably be treated as voltage sources, which have negligible impact to the resonant frequency. Ideally, the "on" time of a switching state equals to half of the sinusoid resonant period of the equivalent LC circuit. In practice, however, because the existence of series resistance introduces some damping to the resonant circuit, the actual "on" time of each switching state can be tuned to deviate slightly from half of the sinusoid resonant time period to achieve ZCS.

As described above, various charge and discharging states can be realized by use of the control logic 150, resulting in different sub-circuit loops. Fig. 2A is a circuit diagram of a first set of sub- circuit 200 loops of the circuit 100 Fig. 1, and Fig. 2B is a circuit diagram of a second set of sub-circuit loops 240 of the circuit 100. Fig. 2C is a timing diagram of the input signals for the switches and the current waveforms of the circuits depicted if Fig. 2A and Fig. 2B during charging and discharging states.

With reference to Fig. 2A, the sub-circuit loop set 200 is formed with the signal SI is "on" and the signal S2 is "off, resulting in the switches Ql, Q3, Q5, and Q8 being open, and Q2, Q4, Q6 and Q7 being closed. The sub-circuit loop formed by the path through VTN, Ql , CI, LI, L2, C3, Q3, C2 and Q8 includes the resonant tanks 102 and 104 and the non-resonant capacitor C2. Conversely, the sub-circuit loop set 240, in Fig, 2B, is formed when signal SI is "off" and the signal S2 is "on" resulting in the switches Ql, Q3, Q5, and Q8 being closed, and Q2, Q4, Q6 and Q7 being open. The particular sub-circuit loop formed by the path through CI , LI, Q2, C2, Q7, Q4, L2 and C3 includes the resonant tanks 102 and 104 and the non-resonant capacitor C2,

Note that there are dead times between the respective states during which both control input signals S I and S2 are "off and all the switches Q of the circuit 100 are in the closed state. This third set of control signal inputs accommodate ZCS. In this instance, the first and second sets of control signals, SI and S2, have respective duty cycles of less than 50%. This dead time is usually minimal to accommodate current reset when ail switches are off however, and ZCS can be accomplished with just the first two sets of control signals, by setting the "on" time of SI ("off for S2) and the "on" time for S2 ("off for SI) to approximately half of the sinusoid resonant period of the resonant tanks, as well as accounting for resistive damping in the circuit elements.

The two sub-circuit loop sets 200 and 240 of circuit 100 demonstrate how inductive impedances are seen in each sub-circuit during the different switching states. Each sub- circuit has an LC resonant tank with inductive impedance at high frequency. Therefore, every flying capacitor (both resonant and non-resonant) is softly charged and discharged during normal operation, due to the di/dt limit from inductor. This reduces or eliminates inrush current or charge redistribution losses associated with flying capacitor voltage ripples in conventional SC converters.

In the example of Fig. 1, the non- resonant capacitor 106 has larger capacitance than the capacitors of the LC tanks. In some implementations, the non-resonant capacitors may be approximately over an order of magnitude higher than the capacitors of the resonant tank. Because the capacitance of the non-resonant capacitor 106 is much higher than that of the resonant capacitors CI and C3 in the resonant tanks 102 and 104, the equivalent series capacitances are dominated by the smaller, resonant capacitor CI and C3. In an example implementation, high performance Class-I (e.g., COG, U2J) MLCC capacitors can be used as resonant capacitors for their small tolerance and low ESR over a wide voltage and temperature range. Class-II (X5R, X7R, etc.) MLCC capacitors can be used as non-resonant capacitors.

The timing diagram illustrated in Fig. 2C shows the input signals for the switches and the current waveforms of the sub-circuits of Figs. 2A and 2B in their charging and discharging states, respectively. As indicated by the timing diagram 300, the switches in control group SI and the switches in control group S2 are toggled "on" and "off," respectively, according to the resonant frequencies of the sub-circuits 200 and 240. This facilitates ZCS, as illustrated by the respective charge and discharge currents in Ql and in Q2. The resulting current in the resonant tank 102 is shown as the Lr Current in Fig. 2C.

In the topology illustrated in Fig. 1, each of the switches in various switch states have their respective drain-to-source voltage (Vds) clamped by a combination of VIN 132, VOUT 130 and the non-resonant capacitor 106 during the "off states of each switch. Figs. 3A-3C demonstrate the clamping of the switches of Fig. 1 through different clamp paths. The resonant tanks 102 and 104 do not appear in the clamp paths, eliminating the possibility of parasitic ringing between resonant inductors Lr and the switch junction capacitors in the circuit and reducing the Vds stress on each switch.

In some implementations, at least one of the circuit nodes receives respective currents from at least two resonant tanks that are reversed in polarity with respect to each other such that they tend to cancel each other out such that the non-resonant capacitor connected to that particular circuit node can be very small relative to a non-resonant capacitor that would be required if the currents did not tend to cancel each other out.

The STC of Fig. 1 can be used as a stand-alone converter. However, multiple STCs can be connected in parallel for multi-phase or multi-cell operation. Fig. 4A is a block diagram of an example power system architecture including multiple paralleled STCs, including 414 and 416, and hot swap control 410. Multiple STCs in parallel can be used when power delivery requirements exceed the power delivery capability of a single STC. Such a configuration offers the flexibility of STC control logic with hot swap functionality. For example, STC 414 inserted into circuit 400 can start up once the VIN HS 408 has reached a threshold voltage such that the gate drive and control logic circuitries are powered, but is still below the Vds rating of the switches within STC 414. This type of topology additionally benefits from fault protections, where the hot swap controller 410 can shut off power to an individual STC upon receiving fault notifications, (such as over-temperature, over-voltage, or over-current), from the controller of the individual STC 414.

The parallel STC architecture can also be extended to a variety of applications where high voltage conversion ratios are required, but galvanic isolation is not.

In another configuration, a single or multiple STCs can be connected in parallel in a two-stage point of load (PoL) power conversion architecture. Again, multiple STCs may be used in parallel when a power delivery requirement exceeds the power delivery capability of any one STC. Fig. 4B is a block diagram of an example two-stage PoL power conversion delivery architecture 450 that incorporates multiple STCs, including 460 and 462, in parallel and multiple point of load converters, including 464 and 466. In Fig. 4B, the STCs, including 460 and 462, receive input voltage VIN 406 and step down the voltage to an intermediate bus voltage VIB 470. The point of load converters, including 464 and 466, each receive the intermediate bus voltage as input and generate a corresponding output regulated VOUT 404, whose voltage value depends on the voltage requirements of the load. One example implementation receives a 48V input and generates a 12V output. A pulse width modulation (PWM) interleaving technique can be applied for parallel operation to reduce input and output voltage ripples. Although the implementation of the STC has been described in the context of a 4-to-l topology with full-wave output rectification, the STC can be implemented in multiple other topologies and voltage conversion ratios. Examples of such topologies are illustrated by Figs. 5-10. An example of a -phase 4-to-l half- wave output rectification STC topology is illustrated in Fig. 5, where the output current is a half- wave sinusoid. In Fig. 5, circuit 500 includes main switches Q1-Q6, synchronous rectifier (SR) switches Q7-Q8, resonant tanks 502, 504, and 506, each including a resonant inductor Lr and resonant capacitor Cr, and non- resonant capacitors 508 and 510. Control signal inputs at each switch Q is provided by control logic 550. At steady state, all switches Q1-Q8 are biased by VOUT 530 during their respective "off states. Each flying capacitor, resonant and non-resonant, has approximately identical ripple current, though each may be biased by different DC voltages (e.g., VOUT, 2* VOUT, and 3* VOUT) during normal operation. However, in other topologies, flying capacitors may be biased by a same voltage. For example, in the circuit diagram 600 shown in Fig. 6, each flying capacitor is biased by the same DC voltage VOUT 630, and the respective ripple currents of each flying capacitor may vary. Figs. 5 and 6 illustrate the design and performance tradeoffs that can be made between capacitor ripple currents and DC bias voltages.

Two example circuit diagrams of 2-phase 4-to-l full-wave output rectification STC topologies are depicted in Figs. 7 and 8. In Fig. 7, resonant tanks 710, 712, and 714 belong to a first phase sub-circuit 704, and resonant tanks 716, 718, and 720 belong to a second phase sub-circuit 702. Non-resonant capacitors 706 and 708 are coupled to both phase sub- circuits 702 and 704. The two different phase sub-circuits are controlled by control logic 750 in an approximately 180 degree phase shift, such that the ripple currents in the non-resonant capacitors 706 and 708 are minimized. The interleaving between the two phases of the circuit 700, represented by sub-circuits 702 and 704, gives the potential to significantly reduce the non-resonant capacitors 706 and 708.

The circuit diagram 800 in Fig. 8 includes resonant tanks 802, 804, 806 and 808, and non-resonant capacitors 810 and 812, that are included both sub-circuits SI and S2 as determined by input control from control logic 850. Sub-circuit SI incudes switches Ql 1, Q13, Q15, Q22, Q24, and Q26. The switch Q26 is connected to a circuit node at one lead, and to ground 836 with the other lead. Sub-circuit S2 incudes switches Q12, Q14, Q16, Q21, Q23, and Q25. The switch Q 6 is connected to a circuit node at one lead, and to ground 840 with the other lead. The SR switches Ql 5, Q16, Q25, and Q26 are symmetrical and each carry approximately the same current, forming part of the output full-bridge topology 800.

A modified circuit diagram of Fig. 7 in which reversed polarity power conversion can be achieved using STCs is depicted in Fig. 9. In Fig. 9, the resonant tanks 910, 912, and 914 belong to a first phase sub-circuit 904, and resonant tanks 916, 918, and 920 belong to a second phase sub-circuit 902. The non-resonant capacitors 906 and 908 have one lead each to both sub-circuits 902 and 904, and the other respective leads are coupled to ground. The two different phase sub-circuits are controlled by control logic 950 in an approximately 180 degree phase shift, such that the ripple currents in the non-resonant capacitors 906 and 908 are minimized. A negative DC input voltage at VTN 932, is converted by a conversion ratio of K and then inverted in polarity to a positive DC output voltage VOUT 930. For a given conversion ratio of K in the circuit 700 in Fig. 7, the reversed polarity converter circuit 900 of Fig. 9 would yield a conversion ratio of -(K-l).

The circuit diagram 1000 in Fig. 10 is an example of a STC topology with a scaled-up voltage conversion ratio from Fig. I. In Fig. 0, a 1 -phase 6-to-l STC full-wave rectification topology includes main switches Q1-Q6, synchronous rectifier (SR) switches Q7-Q16, resonant tanks 1010, 1012, and 1014, each included a resonant inductor Lr and resonant capacitor Cr, and non-resonant capacitors 1006 and 1008. Control signal inputs at each switch Q is provided by control logic 1050. The SR switches Q7-Q16 in circuit 1000 use multiple MOSFETs connected in parallel to achieve identical current in each MOSFET.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate

embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments. Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results.