Present invention relates to a driver apparatus and method of controlling a bias voltage supplied to a cascode stage connected to an input transistor means arranged to receive a binary input signal.

Laser drivers and optical modulator drivers are widely employed in optical communication systems. The continuing demand for higher bit rates can be satisfied by employing new bipolar technologies that realize even faster transistors. However, in these fast RF IC technologies, unity gain frequency (fT) is traded for collector-emitter breakdown voltage BVceo. The consequence is that the fastest technologies have the lowest BVceo.

In traditional laser driver and modulator driver circuits, this poses a severe limit on the maximum output voltage swing and consequently the maximum laser/modulator current.

This current is important since it determines the optical output power and that is a major parameter for the system performance. In many applications there is a need to increase the laser/modulator current above the described limit.

Bipolar digital output drivers with a common emitter configuration are commonly used to drive a load impedance, e. g. in a current mode logic (CML) stage or in a class A amplifier. The maximum output swing is defined as: Vout, swing, max = Vout, max-Vout, min The maximum output swing is limited to: Vout, swing, max = BVceo-Vce, sat where BVceo is the collector-emitter voltage where collector breakdown can occur and Vce, sat is the collector-emitter voltage where saturation occurs.

If the required output voltage is so high that the output transistor comes into the collector breakdown region, normally a cascode stage is added that acts as a level shifter and increases the output voltage. The insertion of a bipolar cascode or common base stage increases the maximum output voltage but also the minimum output voltage with the same amount because the cascode transistor should also be kept outside the saturation region. Thus the maximum output voltage swing is not increased and remains equal to: Vout, swing, max = BVceo-Vce, sat

In conventional cascoding techniques, the gates or control terminals of the cascode transistors are usually driven from a fixed DC voltage. This arrangement causes the cascode transistors to turn off as the common mode input voltage of the differential amplifier is about a threshold voltage from the gate or control voltage of the cascode transistors. As a result, the differential pair is also turned off. Thus, the upper end or the lower end of the common mode voltage range is reduced, depending on the conduction type of the input transistors of the differential pair.

US2002/0070804A1 discloses a dynamic cascoding technique for operational amplifiers, wherein the above common mode range problem is reduced by applying the common mode input voltage of the differential amplifier to the gates of both cascode transistors. This dynamic cascoding technique can prevent the cascode transistors from turning off.

Another way to increase the maximum output voltage is to use a different type of transistor with higher BVceo. In many BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) and bipolar processes this so-called High-Voltage NPN is available.

However, this device always has a lower unity gain frequency (fT) and therefore it is not suited for high frequency applications.

It is an object of the present invention to provide a driver control method and driver apparatus, by means of which laser or modulator current can be increased without entering the transistor breakdown region.

This object is achieved by a driver apparatus as claimed in claim 1 and a method as claimed in claim 10.

Accordingly, the cascode stage is driven by a binary signal having the opposite logical value or polarity as the respective input signal driving the input transistor means. The absolute values of the signals, which drive input and cascode transistors are different such that a maximum signal value can be obtained in a load of the driver apparatus. Thereby, the maximum output signal of the driver apparatus can be increased.

The input transistor means may comprise a differential pair comprising a first input transistor arranged to receive a non-inverting binary input signal and a second input transistor arranged to receive an inverting binary input signal, the cascode stage may comprise first and second cascode transistors respectively coupled to the first and second input transistors, and the dynamic cascode bias generator circuit may be adapted to generate

first and second control signals supplied to the first and second cascode transistors, respectively, the first and second control signals having the same logical value as the inverting and non-inverting binary input signals, respectively, but different absolute values than the inverting and non-inverting binary input signals, respectively. Thereby, the improved output range of the driver apparatus can be provided in an advantageous differential embodiment with improved linearity and noise rejection.

Furthermore, the dynamic cascode bias generator circuit may comprise a differential pair comprising a third input transistor arranged to receive a modified non- inverting input signal generated from the non-inverting input signal, and a fourth input transistor arranged to receive a modified inverting input signal generated from the inverting input signal. Thereby, signal distortions or asymmetries can be kept low while the modified input signals are processed to be applied to the cascode stage.

The non-inverting and inverting input signals may be generated from the modified non-inverting and inverting input signals by applying a predetermined phase shift corresponding to the delay of the dynamic cascode bias generator circuit. This measure ensures that the dynamic variations of the control voltages of the cascode transistors are in phase with the respective input signals supplied to the first and second input transistors, to thereby optimize the circuit behaviour.

Furthermore, the dynamic cascode bias generator circuit may be arranged to generate the absolute values of the first and second control signals in such a manner that the collector-emitter voltage of the first input and second transistors is kept within a range between a minimum and maximum allowable value, wherein the minimum allowable value may be higher than the saturation voltage. In particular, the dynamic cascode bias generator circuit may be arranged to generate the first and second control signals so as to switch between the following absolute maximum and minimum values: Vmax = Vcc-BVceo + Vbe, and Vmin= Vcc-2*BVceo + Vce, sat + Vbe, wherein Vcc designates a supply voltage supplied to the driver apparatus, BVceo designates the maximum allowable collector-emitter voltage drop, Vbe designates the base-emitter voltage drop, and Vce, sat designates the minimum allowable collector emitter voltage drop.

Thus, the output voltage can be increased the twofold of the maximum allowable collector- emitter voltage.

The dynamic cascode bias generator circuit may comprise respective emitter follower stages for supplying the first and second control signals to the first and second

cascode transistors. These emitter follower stages serve to reduce the load applied to the dynamic cascode bias generator circuit by increasing the impedance value of the cascode stage.

Additionally, the dynamic cascode bias generator circuit may comprise compensation means for compensating a temperature dependency in at least one of the emitter follower stage and the cascode stage. As an example, the compensation means may comprise at least one of resistor means and current source means having a predetermined temperature coefficient adapted to the temperature dependency.

Further advantageous modifications are defined in the dependent claims.

The present invention will now be described on the basis of a preferred embodiment with reference to the accompanying drawings, in which: Fig. 1 shows a schematic block diagram of a driver control scheme according to the preferred embodiment, Fig. 2 shows a schematic circuit diagram of a conventional driver circuit; Fig. 3 shows a schematic circuit diagram of a driver circuit according to the preferred embodiment; Fig. 4 shows signal waveforms of said driver circuit according to the preferred embodiment; and Fig. 5 shows a schematic circuit diagram of a dynamic bias voltage generator according to the preferred embodiment.

The preferred embodiment will now be described on the basis of a laser or optical modulator driver which may be used in an optical communication system. Initially, a conventional driver circuit is shortly explained to provide a link to the proposed solution.

Fig. 2 shows a conventional solution for a laser/modulator driver. Binary non- inverting and inverting input voltages Vinl and Vin2 are supplied to respective control or base terminals to switch a current switch consisting of T1 and T2. A current source is provided to generate a current Itail which limits the maximum output current Iout, max flowing either through the left input transistor Tl and a matched dummy load Rm or through the right input transistor T2 and the real load, i. e. laser or modulator, indicated by a symbolic diode element.

This binary behaviour can be expressed as follows: Iout, min = 0, which corresponds to the logical signal value"zero" Iout, max = Itail, which corresponds to the logical signal value"one".

From a transistor's point of view, the maximum achievable collector-emitter voltage drop BVceo is: (Vout-Ve) max = BVceo, where Vout designates the output voltage at the collector terminal of the right input transistor T2, and Ve designates the voltage at the emitter terminal of both input transistors Tl and T2.

On the other hand, the minimum collector-emitter voltage drop Vce, sat, in order to avoid saturation of the respective input transistor, is: (Vout-Ve) min = Vce, sat.

This leads to a maximum output voltage swing as follows: Vout, pp, max = (Vout-Ve) max- (Vout-Ve) min = BVceo-Vce, sat.

The resulting maximum swing of the output current lout flowing through a load with resistance value Rload, e. g. the laser or modulator, can be expressed as follows: Iout, pp, max = (BVceo-Vce, sat)/Rload.

Since the minimum current Iout, min for the logical output state or value"zero"equals 0, it follows that: Iout, max = Iout, min + Iout, pp, max = (BVceo-Vce, sat)/Rload.

As already mentioned, this maximum value might be insufficient in cases where the maximum collector-emitter voltage BVceo is low.

In the following, a solution is described based on the preferred embodiment to increase the maximum output current lout. In particular, it is proposed that the base or control terminal of each cascode transistor is not connected to a DC voltage, but connected to a signal that is inverted with respect to the respective input signal. This configuration can be called a"switching cascode".

Fig. 1 shows a schematic block diagram of such a switching cascode circuit to be used in the preferred embodiment. As can be gathered from Fig. 1, a cascode transistor Tc is connected to the collector terminal of an input transistor Ti. The input signal supplied to the input transistor Ti is also supplied to the cascode transistor Tc via an inverter circuit 10.

For a low input voltage, the output voltage Vout must go high. The cascode voltage Vcasc supplied to the control terminal of the cascode transistor Tc is generated in such a way that the output voltage is distributed across both transistors Tc and Ti. Thereby, the maximum output voltage may be well above BVceo, in fact it may go up to 2*BVceo. For a high input

voltage, the output voltage must go low. The cascode voltage Vcasc is generated in such a way that the input transistor Ti is kept just outside the saturation region, i. e. the collector- emitter voltage of the input transistor Ti is slightly larger than Vce, sat. The output voltage can go down until the cascode transistor Tc also reaches the saturation region. So the maximum output voltage swing can be doubled to: Vout, swing, max = 2*BVceo-2*Vce, sat In the following, a practical implementation of the switching cascode and the inverting circuit 10 of Fig. 1 is described as the preferred embodiment.

Fig. 3 shows a driver circuit according to the preferred embodiment, which is based on the conventional driver circuit of Fig. 2 and to which a cascode transistor stage is added, consisting of cascode transistors T3 and T4. These cascode transistors T3 and T4 are controlled by respective control voltages Vcascl and Vcasc2, which have the same logical value or state as Vin2 and Vinl, respectively (and thus opposite logical value or state as Vinl and Vin2, respectively), but different absolute values. The function of this cascode stage is to consume part of the increased output voltage Vout. As explained above, the maximum achievable voltage drop across each branch, consisting of either T1 and T3, or T2 and T4, is now changed to: (Vout-Ve) max = 2 * BVceo.

The minimum voltage drop across each branch, in order to avoid saturation, is: (Vout-Ve) min = 2 * Vce, sat.

These output voltage values can be realized or obtained if the cascode transistors T2 and T4 are switched at appropriate voltage levels Vcascl and Vcasc2.

Hence, the maximum output voltage swing now equals to: Vout, pp, max = (Vout-Ve) max- (Vout-Ve) min = 2 * BVceo-2 * Vce, sat.

This results in a maximum swing of the output current lout : Iout, pp, max = Vout, pp, max/Rload = 2 * (BVceo-Vce, sat)/Rload.

Since the minimum output current Iout, min (for logical value"zero") equals 0, it follows that: Iout, max = Iout, min + Iout, pp, max = 2 * (BVceo-Vce, sat)/Rload.

This value is twice as large as Iout, max in the traditional circuit of Fig. 2, while using the same technology.

In the following a way to generate the control voltages Vcascl and Vcasc2 of the respective cascode transistors T3 and T4 is explained.

Fig. 4 shows a time dependent diagram which depicts the waveform of the output voltage Vout (thick line) and the control voltage Vcasc2 (thin line) required at the base terminal of the right cascode transistor T4 of the cascode stage. It is noted that the waveform of the other control voltage Vcascl is the opposite, i. e. can be obtained by inverting the waveform of Fig. 4.

As can be gathered from Fig. 4, the output voltage changes or switches between the minimum value Vcc-2*BVceo+2*Vce, sat and the maximum value Vcc (Iout = 0), wherein Vcc corresponds to the supply voltage of the laser or modulator. To achieve this, the control voltages Vcascl and Vcasc2 have to be changed or switched between: a minimum value: Vmin = Vcc-2*BVceo+Vce, sat+Vbe, and a maximum value: Vmax = Vcc-BVceo+Vbe Fig. 5 shows an exemplary circuit diagram of an implementation of a dynamic bias voltage generator for generating the cascode control voltages Vcascl and Vcasc2. The input voltages Vinl and Vin2 of the driver circuit in Fig. 3 can be identical to the input voltages Vin4 and Vin3, respectively, of the bias voltage generator, but have to be delayed or shifted in phase by a predetermined amount. The delay or phase shift in the input voltages of the driver circuit Vinl and Vin2 can be generated by a separate circuit (not shown) and must be selected to match the delay of the circuit in Fig. 5. According to Fig. 5, the dynamic bias voltage generator comprises a differential input stage consisting of input transistors T5 and T6 to which the respective non-inverting and inverting input signals Vin4 and Vin3 are applied. the tail current is set by a corresponding current source. The required amplification for setting the above minimum and maximum values of the cascode control voltages can be determined by the resistors of the differential input stage based on commonly known calculations. The output signals at the collectors of the input transistors T5 and T6 of the differential input stage are supplied to respective transistors T7 and T8 of respective emitter follower stages which serve to decouple the differential input stage from the cascode stages of Fig. 3 by impedance transformation. The emitter currents of the emitter follower transistors T7 and T8 are set by respective current sources.

The following measures can be taken to compensate for the temperature dependency of the voltage drop 2*Vbe along the two successive base-emitter portions in the emitter follower stage of the dynamic bias voltage generator and in the cascode stage of the driver circuit. Temperature compensation can be achieved by choosing an appropriate shift

resistor Rs with a positive temperature coefficient, e. g. equal to 2 times the Vbe temperature coefficient, or by varying the tail current Itail over temperature with a temperature-dependent current source.

In summary, a driver apparatus and driver control method are proposed for driving high currents used e. g. for lasers or optical modulators or line drivers. The cascode transistor is driven by a binary control signals having a polarity or logical value opposite to the signal driving the input transistor means. The absolute value of the cascode control signal is different from the absolute value of the input signal, such that a maximum signal value is obtained in a load of the driver apparatus. The present invention is however not restricted to the above preferred embodiment but can be used in any driver apparatus with an input stage and a cascode stage, formed by any kind if semiconductor element. Any suitable absolute values can be used for the cascode control voltages. The preferred embodiments may thus vary within the scope of the attached claims.