Background Art Switching power supplies are known in the art. Typical uses of switching power supplies include generating a constant, regulated output voltage Vout from an input source, whose voltage Vin may be decreasing in amplitude over time. A switching power supply having a"boost" circuit topology is capable of generating a regulated output voltage Vout that is greater than the unregulated supply voltage Vin. As an example, a switching power supply may be used to generate a regulated output voltage Vout from the potential difference across terminals of a battery in order to operate an electrical device such as a portable computer, a radio, a CD player, a cellular phone or the like. As the electrical device drains energy from the battery, the input voltage Vin supplied by the battery diminishes over time, and it is the job of the boost regulator to continue generating a constant output voltage Vout to keep the electrical device operating.

With reference to Figures 1-2, the topography and operation of a traditional boost switching regulator 100 of the Prior Art will now be described. Prior Art Figure 1 illustrates the boost switching regulator 100 including an inductor L, an output filter capacitor C, an n-channel Metal-Oxide Semiconductor Field Effect Transistor (NMOS) switch 102, a p-channel MOSFET (PMOS) switch 104, and duty-cycle control circuitry 106. Voltage Vin is typically an unregulated source of DC voltage connected to a first terminal of the inductor L and to a common ground reference 110. The second terminal of the inductor L and the drains of the switches 102 and 104 are coupled together at a node Lx. The source and body of the PMOS switch 104 are coupled together at a first terminal of the capacitor C, thereby forming a PMOS body diode from Lx to the first capacitor terminal. The control circuitry 106 implements a duty- cycle algorithm, controlling the operation of the NMOS switch 102 and the PMOS switch 104.

The second terminal of the capacitor C, a second terminal of the voltage Vin, and the source and body of the NMOS switch 102 are all coupled to a common ground reference 110. The output voltage Vout of the switching regulator 100 measured across the output capacitor C.

Prior Art Figure 2 illustrates a state diagram 150 for operation of the boost switching regulator 100. During an on-cycle 152, the duty-cycle control 106 turns the NMOS switch 102 on and the PMOS switch 104 off. The inductor current Il thus increases at a rate of about Vin/L and, since the PMOS switch 104 is off, no power is transferred from the inductor L to the output.

During an off-cycle 154, the duty-cycle control 106 turns the NMOS switch 102 off and the PMOS switch 104 on. Hence during the off-cycle 154, power is transferred from the inductor L to the output and the inductor current Il decreases at a rate of (Vout-Vin)/L. For ease of reference, the relevant control voltages for the on-cycle 152 and the off-cycle 154 are shown in both Figure 2 and in the following table. Traditional Boost NMOS Gate Drive PMOS Gate Drive PMOS Body On-Cycle 152 Vin Max (Vin, Vout) Vout Off-Cycle 154 Ground Ground Vout As will be appreciated, a variety of duty-cycle algorithms can be implemented by the duty-cycle control 106 in order to regulate the output. For example, in a constant ripple, hysteretic converter, the on-cycle 152 is terminated when the inductor current reaches a predetermined maximum value, and the off-cycle 154 is terminated when the inductor current drops below a predetermined minimum value.

Although the traditional boost topology is effective for regulating power under certain circumstances, both the traditional topology and the prior art control algorithms have significant drawbacks. One such drawback is the inability of prior art algorithms to limit inrush current across a variety of input and output voltages. Large inrush currents tend to drastically reduce the life of battery input power supplies. What is needed is a boost switching power supply capable of limiting inductor current at any point regardless of the input and output voltages.

Disclosure of the Invention In order to achieve the foregoing and in accordance with the present invention, a variety of switching power supplies and methods for controlling the same are disclosed. In particular, the present invention teaches several modes for operating a boost type switching power supply.

A linear charging mode couples the input voltage directly to the output voltage, thereby precharging the output capacitor of the switching power supply. The linear mode serves to reduce inrush battery current and limit the stress voltage on the power switching devices. A pseudo-buck mode, preferably entered into after the linear mode has precharged the output capacitor, operates the boost type switching power supply in a manner providing power to the output essentially as would a buck type switching power supply. This results in continuous charging of the output capacitor, thereby reducing startup time and increasing power efficiency.

The pseudo-buck mode also enables step-down voltage generation with boost type circuitry. A pseudo-boost mode facilitates a smooth transition between the pseudo-buck and traditional boost modes. The power devices are operated in the pseudo-buck mode such that control over the inductor current is maintained to minimize inrush current.

One specific embodiment of the present invention teaches a switching power supply having an inductor, an output capacitor, first and second variable impedance devices, and a control circuit for controlling the first and second variable impedance devices. The first variable impedance device couples the inductor and the output capacitor terminal together. The second variable impedance device couples the inductor to a common ground reference. The control circuit is operable to implement one or more of a linear mode, a pseudo-buck mode, and a pseudo-boost mode.

The variable impedance devices may be formed from transistor switches such as NMOS and PMOS devices. In such a case, the pseudo-buck mode is implemented having an on-cycle and an off-cycle. During the pseudo-buck mode on-cycle, the second switch gate is coupled to the common ground reference, the first switch gate is coupled to the common ground reference, the diode anode is coupled to Vout, and the diode cathode is coupled to the second inductor terminal. During the pseudo-buck mode off-cycle, the second switch gate is coupled to the common ground reference, the first switch gate is coupled to a voltage suitable to choke the current flowing through the first switch, the diode anode is coupled to Vout, and the diode cathode is coupled to the second inductor terminal.

Another aspect of the present invention teaches a pseudo-boost mode having an on-cycle and an off-cycle. During the pseudo-boost mode on-cycle, the first switch gate is coupled to the greater of Vin and Vout, the second switch gate is coupled to Vin, the diode anode is coupled to

the second inductor terminal, and the diode cathode is coupled to Vout. During the pseudo-boost mode off-cycle, the second switch gate is coupled to a ground reference, the first switch gate is coupled to Vin, the diode anode is coupled to Vout, and the diode cathode is coupled to the second inductor terminal.

In certain embodiments of the present invention, the power supply further includes a third variable impedance device such as a transistor switch having a gate, a source, and a drain, the drain being coupled to the first inductor terminal and the source being coupled to Vout. This enables operation of the power supply in a linear mode during which both the first and second switches are disabled and the third switch gate is coupled to Vin, thereby directly coupling the input voltage Vin to the output voltage Vout through the third switch.

In preferred embodiments, the power supply is initially operated in the linear mode in order to precharge the output capacitor. Once the output capacitor has reached a desired precharge voltage Vpc, the power supply is operated in the pseudo-buck mode until Vout reaches a predefined threshold value V,, that is less than Vin. When Vout is between about Vt, and V, V, being greater than or equal to Vin, the power supply is then operated in the pseudo-boost mode. Once Vout has exceeded about V, the power supply is then operated according to a traditional boost duty-cycle algorithm.

Brief Description of the Drawings Prior Art Figure 1 is a schematic of a traditional boost power supply.

Prior Art Figure 2 illustrates a state diagram for the on-and off-cycles of the traditional boost power supply of Figure 1.

Figure 3 is a schematic of a power supply in accordance with one embodiment of the present invention.

Figure 4 illustrates a state diagram for several different modes of operation for the power supply of Figure 3.

Best Modes for Carrving out the Invention Figure 3 illustrates a regulated switching power supply 300 in accordance with one embodiment of the present invention. The switching power supply 300 includes an inductor L, a capacitor C, two NMOS transistor switches 302 and 304, a PMOS transistor switch 306, and duty-cycle control circuitry 308. An input power supply provides a voltage Vin coupled to both a first terminal of the inductor L and at the drain of the NMOS switch 302, the voltage Vin measured with respect to a common ground reference 310. The source and body of the NMOS transistor 302, and the first terminal of the output filter capacitor C are coupled together forming the output voltage Vout of the power supply 300. The second terminal of the inductor L and the drains of both the NMOS switch 304 and the PMOS switch 306 are coupled together at a node Lx.

Control circuitry 308 is coupled to drive the gates of the transistors 302-306, and further to sense the voltages at an output Vout and a node Lx. The control circuitry 308 implements a duty-cycle algorithm for providing a regulated power supply having a regulated voltage Vout.

Control circuitry 308 may be implemented in a microprocessor, programmable logic such as a PLD, PLL, PAL, or any other suitable circuitry. Several different control algorithms according to the present invention are described below.

The present invention contemplates four distinct modes of operation for a boost power supply such as power supply 300 of Figure 3, including three that are intended for implementation during startup as well as a more traditional boost mode. The startup modes are referred to herein as the"linear"mode, the"pseudo-buck"mode and the"pseudo-boost"mode.

Figure 4 illustrates a state diagram 400 progressing through a pseudo-buck, pseudo-boost, and boost modes. As will be described below, each of these modes has particular advantages and requirements. Further, in accordance with the present invention, these modes may be used individually or in various combinations with each other and the traditional boost mode.

The linear mode is a preferred control algorithm when the output voltage Vout is less than a predefined precharge voltage Vpc. During linear mode, the input power supply is directly coupled to the output, enabling the output voltage Vout to charge up to the precharge voltage.

To accomplish this, the control circuitry 308 disables the NMOS switch 304 and the PMOS switch 306, and turns the NMOS switch 302 fully on.

By directly coupling the input to the output, the linear mode reduces the battery inrush current normally seen across the inductor L during the initial charging of a regulated power supply. In order to implement the linear mode, the power supply 300 requires an additional NMOS switch, i. e., NMOS switch 302, not required in the traditional boost regulator 100 of

Figure 1. However, by precharging the output voltage Vout, the linear mode reduces the stress voltage placed upon the PMOS switch 306, particularly during the pseudo-buck mode described below. Because of this, the power supply 300 can be designed with a smaller, low-voltage PMOS switch 306. Thus even with an additional NMOS switch, there is nonetheless space savings over having to implement a large PMOS switch.

Once the output voltage Vout has charged up to the precharge voltage Vpc, one embodiment of the present invention teaches transitioning into a pseudo-buck mode 402. During the pseudo-buck mode 402, the NMOS switches 302 and 304 are disabled and the body of the PMOS switch 306 is connected to the node Lx. Hence, that portion of the power supply 300 utilized during the pseudo-buck mode 402 has a topology similar to that of a traditional buck power supply. (Essentially, the inductor L and the PMOS switch 306 are"swapped"with respect to the input voltage Vin.) In fact, as will be seen, the operation of the power supply 300 during the pseudo-buck mode 402 results in charging the output in a manner essentially identical to the traditional buck power supply.

During a pseudo-buck on-cycle 410, the PMOS switch 306 is turned on and the inductor current Il increases at the rate of (Vin-Vout)/L. During a pseudo-buck off-cycle 412, the gate of the PMOS switch 306 is coupled to the input voltage Vin so that the inductor current decreases at a rate of Vgs (PMOS)/L. As shown in Figure 3, Vgs (PMOS) is the voltage differential between the gate and the source of the PMOS switch 306 with the inductor current flowing through the PMOS switch 306.

In the off-cycle 412 of the pseudo-buck mode, as in the traditional buck mode, the inductor current Il must still flow through the PMOS switch 306. However, the control circuitry 308 has set the gate of the PMOS switch 306 to Vin. Therefore, in order for current to keep flowing through the PMOS switch 306, the source of the PMOS switch 306 must fly up to at least a couple volts above the gate of the PMOS switch 306. For example, if the input voltage Vin is nominally 5 Volts, then during the off-cycle 412, the PMOS switch 306 source voltage must fly up to about 6-7 Volts to enable the inductor current to continue flowing. Hence, if one were to skip the linear mode and not precharge the output voltage Vout, the pseudo-buck mode 402 would apply about 6-7 Volts across the PMOS switch 306 during the off-cycle. As a result, a high-voltage, space inefficient PMOS switch would be required. However, providing the linear mode is one method for avoiding this large stress voltage. The precharge voltage should thus be set by reference to the breakdown voltage of the PMOS switch 306. Specifically, the precharge voltage Vpc should be greater than (Vin + Vgs (PMOS)-Vbreakdown). The precharge voltage

Vpc should be chosen without forgetting, however, that the larger Vpc is, the more power inefficient the power supply 300 will be.

Because the inductor current Il continuously charges the output capacitor C during the pseudo-buck mode 402, the startup time of the power supply 300 is less that than obtained by many traditional boost regulator startup algorithms. Further, there is an improvement in power efficiency of the power supply 300 during startup. Another advantage over traditional boost algorithms, the pseudo-buck mode 402 actually enables a circuit having a boost topology (i. e., the power supply 300) to provide a step down operation, working like a buck circuit.

For ease of reference, the relevant control voltages for the pseudo-buck mode 402 are shown in Figure 4 and are also provided in the following table. Pseudo-Buck NMOS Gate Drive PMOS Gate Drive PMOS Body On-Cycle 410 Ground Ground Lx Off-Cycle 412 Ground Vin Lx As Vout approaches Vin during the pseudo-buck mode 402, the duty-cycle of the PMOS switch 306 likewise approaches one-hundred percent (100%). In practice, a duty-cycle of 100% is not obtainable. However, immediately switching into a traditional boost mode algorithm from such a point is not suitable because the output voltage Vout is still less than the input voltage Vin.

Accordingly, once the output voltage Vout exceeds a second transition voltage Vt such as one diode below Vin, the present invention teaches transitioning into the pseudo-boost mode 404. The pseudo-boost mode 404 serves to facilitate a smooth transition between the pseudo- buck mode 402 and the traditional boost mode 406. Additionally, the pseudo-boost mode 404 provides even further control over the inductor current Il, thus further minimizing battery inrush current.

During an on-cycle 414 of the pseudo-boost mode 404, the gate of the NMOS switch 304 is tied to Vin, the gate of the PMOS switch 306 is tied to the greater of the input voltage Vin and the output voltage Vout, and the body of the PMOS switch 306 is tied to the output voltage Vout.

As a result, during the on-cycle 414 the inductor current Il increases at a rate of Vin/L. During an off-cycle 416, the gate of the NMOS switch 304 is tied to ground 310, the gate of the PMOS switch 306 is tied to Vin, and the body of the PMOS switch 306 is tied to Lx. Thus during the off-cycle, the inductor current Il decreases at a rate of Vgs (PMOS)/L, similar to the off-cycle 412 of the pseudo-buck mode 402.

For ease of reference, the relevant control voltages for the pseudo-boost mode 404 are shown in the state diagram 400 of Figure 4, and are also provided in the following table. Pseudo-Boost NMOS Gate Drive PMOS Gate Drive PMOS Body On-Cycle 414 Vin Max (Vin, Vout) Vout Off-Cycle 416 Ground Vin Lx

Finally, once the output voltage exceeds the input voltage Vin, the power supply 300 will enter into a traditional boost mode, the duty-cycle control circuitry 308 implementing a suitable boost duty-cycle algorithm such as the hysterisis algorithm described above with reference to Figures 1 and 2.

Although only a few embodiments of the present invention have been described in detail herein, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention.

It is not essential to the present invention that the duty-cycle control circuitry implement the algorithms for all three of the linear, pseudo-buck, and pseudo-boost modes. For example, by eliminating the linear mode, the smaller NMOS switch 302 could also be eliminated. Thus the pseudo-buck and pseudo-boost modes can be implemented on traditional boost topology without additional switching devices.

Without the linear mode, however, certain precautions must be taken to avoid the breakdown of the PMOS switch 306. Perhaps the crudest solution is to simply design the PMOS switch 306 large enough to handle the stress voltage that would arise during the pseudo-buck mode. However, more elegant solutions are contemplated. In particular, rather than coupling the gate of the PMOS switch 306 to Vin during the off-cycle 412, the control circuitry 308 could drive the gate of the PMOS switch 306 to Vin/2 or some other suitable voltage value. This would, similar to the linear mode, eliminate a high stress voltage across the PMOS switch 306.

The transistor switches described above were all MOSFET technology. However, those skilled in the art will recognize that the concepts of the present invention can be implemented utilizing other suitable variable impedance devices such as bipolar transistors.

Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims.