[Technical Field]

The present invention generally relates to the field of switched mode power supplies (sometimes referred to as switch mode power supplies or switching mode power supplies) and more specifically to the synchronisation of the switching of two or more switched mode power supplies that are connected in parallel to a common power source.

[Background]

The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency, for example in servers, personal computers and portable electronic devices such as cell phones. A SMPS achieves these advantages by switching one or more switching devices such as power MOSFETs at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching being adjusted using a feedback signal to convert an input voltage to a desired output voltage. A SMPS may take the form of a rectifier (AC/DC converter), a DC/DC converter, a frequency changer (AC/AC) or an inverter (DC/AC).

If the power output capability of a single SMPS is not sufficient for a given application, it may be possible to connect multiple SMPSs in parallel to supply power to a load via a common output rail. Alternatively, in other applications, such as signal processing systems having multiple high-performance processors that are characterised by their need for multiple low supply voltages, high current demand and tight supply voltage regulation requirements, two or more SM PSs, which are respectively configured to output the required regulated voltages, may be connected in parallel to a common input rail. In applications of these kinds, where two or more SM PSs are connected in parallel to a common power source, small differences in the switching frequencies of the paralleled SM PSs can cause an input current component at the beat frequencies to appear in the input supply rail, which may cause electromagnetic interference (EM I) problems.

One conventional approach to dealing with these EM I problems is to use a phase- or delay-locked loop in the control of the paralleled SM PSs. A simpler approach, which is also cheaper to implement, is to configure one of the paralleled SM PSs (designated as a 'master' SMPS) to transmit a synchronisation pulse to the remaining 'slave' SMPSs every switching period of the master SM PS in order to synchronise the switching of the SM PSs.

[Summary] The inventors have devised a power supply system comprising a first switched mode power supply (SM PS) connected to a power source, the first SM PS comprising a controller configured to control switching of the first SM PS so as to convert an input voltage of the first SM PS into an output voltage of the fi rst SMPS, and a second SM PS connected to the power source in parallel with the first SM PS, the second SMPS being configured to generate and transmit to the controller a synchronisation signal every N switching periods of the second SM PS for synchronising the switching of the first SM PS with the switching of the second SMPS, where N is an integer greater than or equal to 1. The controller is configured to synchronise the switching of the first SM PS with the switching of the second SMPS using the received synchronisation signal only when the synchronisation signal is received in one of a plurality of separate time windows.

The inventors have further devised a n SM PS for connection in parallel with a second SM PS to a common power source, and operable to receive from the second SM PS a synchronisation signal transmitted by the second SM PS every N switching periods of the second SM PS for synchronising the switching of the SM PS with the switching of the second SMPS, where N is an integer greater than or equal to 1. The SMPS comprises a switching circuit configured to convert an input voltage of the SMPS into an output voltage of the SMPS by switching a switching device included in the switching circuit, and a controller configured to control the switching of the switching device. The controller is further configured to receive the synchronisation signal and synchronise the switching of the switching device with the switching of the second SMPS using the received synchronisation signal only when the synchronisation signal is received in one of a plurality of separate time windows. The inventors have further devised a controller for an SMPS having a switching circuit configured to convert an input voltage of the SMPS into an output voltage of the SMPS by switching a switching device included in the switching circuit, the SMPS being connectable in parallel with a second SMPS to a common power source and operable to receive from the second SMPS a synchronisation signal transmitted by the second SMPS every N switching periods of the second SMPS for synchronising the switching of the switching device with the switching of the second SMPS, where N is an integer greater than or equal to 1. The controller comprises a switching control module configured to control the switching of the switching device, and a receiver module configured to receive the synchronisation signal. The switching control module is configured to synchronise the switching of the switching device with the switching of the second SMPS using the received synchronisation signal only when the synchronisation signal is received by the receiver module in one of a plurality of separate time windows.

The inventors have further devised a method of synchronising the switching of an SMPS with the switching of a second SMPS that is connected in parallel with the SMPS to a common power source, the SMPS having a controller configured to control switching of the SMPS so as to convert an input voltage of the SMPS into an output voltage of the SMPS, the second SMPS being configured to generate and transmit to the controller a synchronisation signal every N switching periods of the second SMPS for synchronising the switching of the SMPS with the switching of the second SMPS, where N is an integer greater than or equal to 1. The method comprises the controller receiving the synchronisation signal, and synchronising the switching of the SMPS with the switching of the second SMPS using the received synchronisation signal only when the synchronisation signal is received by the controller in one of a plurality of separate time windows.

The inventors have further devised a computer program product, comprising a signal or a non-transitory computer-readable storage medium carrying computer program instructions which, when executed by a processor, cause the processor to perform a method as set out above.

[Brief Description of the Drawings]

Embodiments of the invention will now be explained in detail, by way of example only, with reference to the accompanying figures, in which:

Fig. 1 illustrates a power supply system according to an embodiment of the present invention;

Fig. 2A shows an example circuit of an SMPS, in which the switching devices on the primary side have a half-bridge arrangement;

Fig. 2B illustrates how the 'safe' and 'extended' time windows described herein relate to the switching cycle of the circuit in Fig. 2A and the ramp signal generated by the clock of SMPS 30 in Fig. 1;

Fig. 3 is a more detailed illustration of the power supply system of the embodiment, showing components of the switched mode power supplies;

Fig. 4 illustrates an exemplary implementation of the clock of the master SMPS; Fig. 5 illustrates an exemplary implementation of the clock of the slave SMPS;

Fig. 6 illustrates an example of logic implemented by the controller of the slave SMPS according to an embodiment;

Fig. 7 shows an exemplary hardware implementation of the controllers shown in Figs. 1 and 3;

Fig. 8 is a flow diagram illustrating a method of synchronising the switching of the slave MSPS with the switching of the master SMPS by the slave SMPS according to an embodiment;

Fig. 9 is a flow diagram illustrating in more detail the method of synchronising the switching of the slave MSPS with the switching of the master SMPS by the slave SMPS according to the embodiment;

Fig. 10 shows the results of a simulation which illustrate how the slave SMPS operates in a synchronised mode; and Fig. 11 shows the results of a simulation which illustrate how the slave SMPS begins to operate in a non-synchronised mode after operating in the synchronised mode.

[Detailed Description of Embodiments] The present inventors have recognised that, in conventional power supply systems of paralleled SMPSs of the kind mentioned above, in which the switching of one or more slave SMPSs to a master SMPS is achieved by the transmission of synchronization signals by the master SMPS to the slave SMPS(s), it may be undesirable for a slave SMPS to synchronise its switching using the synchronisation signal regardless of when it is received, as this can cause several problems. In the simplest case, it may cause an output voltage disturbance due to duty cycle changes or an abrupt change in the switching frequency. In SMPSs having a transformer, it is important to keep the flux in the transformer balanced, otherwise the flux will saturate the magnetic material, which can cause a short. The embodiments described herein below address at least some of these draw-backs.

Figure 1 is a schematic of a power supply system 100 according to an embodiment of the present invention, which comprises a first SMPS 10 connected to a power source 20, and a second SMPS 30 which is also connected to the power source 20, in parallel with the first SMPS 10.

By way of an example, the power supply system 100 may be an Intermediate Bus Architecture (IBA) power supply system, with the SMPS 10 and SMPS 30 being Point-of- Load (POL) regulators. Each of the SMPS 10 and SMP 30 may thus deliver a regulated output voltage to its respective load (shown at 12 and 32 in Fig. 1), by switching at least one switching device (such as a power transistor, e.g. a power MOSFET) in the SMPS. Voltage regulation may be achieved by employing a feedback loop for feeding back to the switch controller of the SMPS a signal indicative of the output voltage V , so that the controller can adjust the duty cycle with which the switching device(s) is/are switched in order to minimise any deviation from a target output voltage value. However, it should be noted that output voltage regulation is not an essential feature of SMPS 10 and SMPS 30 so that, in general, only one (or neither) of these converters may provide a regulated output voltage. Furthermore, SMPS 10 and SMPS 30 may alternatively supply power to a common load. Aspects of the possible configuration and functionality of the SMPSs 10 and 30 other than those described herein will be well-known to those skilled in the art, and are therefore not described in the following.

Power may be supplied to SMPS 10 and SMPS 30 from any suitable source 20. For example, where the power supply system 100 is an IBA power supply system, power may be fed to the SMPS 10 and SMPS 30 by a power source 20 in the exemplary form of a first stage DC/DC converter (so-called 'Intermediate Bus Converter', IBC). The power source 20 may alternatively generate the input voltage V _in by, e.g. electro-chemical or electro-optic conversion, and thus take the alternative form of a cell/battery or solar panel, for example.

The first SM PS 10 comprises a controller 11 which is configured to control switching of the first SM PS 10 so as to convert the input voltage V _in of the SM PS 10, which is supplied by the power source 20 via the input power rail, into an output voltage V _ou ti and to supply the output voltage V _out i to the load 12 of the first SM PS 10.

The second SM PS 30 is similarly configured to convert the input voltage V _in into an output voltage V ₀ ut2 (which may differ from V _ou ti) for the load 32 of the second SM PS 30. The second SM PS 30 (which is designated as a 'master' SMPS in the present embodiment) is further configured to generate and transmit to the controller 11 of the first SM PS 10 (which is designated as 'slave' SMPS in the present embodiment) a synchronisation signal S _S ync every switching period of the second SM PS 30 for synchronising the switching of the first SM PS 10 with the switching of the second SM PS 30. More generally, the master SM PS 30 may be configured to generate and transmit to the slave SM PS 10 the synchronisation signal S _Sy nc every N switching periods of the master SM PS 30, where N is an integer greater than or equal to 1. The value of N may be varied in dependence on the difference between the switching frequencies of the master and slave SM PSs, with preferred values of N becoming smaller as the frequency difference increases, in order to maintain synchronisation more effectively. The controller 11 is configured to synchronise the switching of the slave SM PS 10 with the switching of the master SM PS 30 using the received synchronisation signal S _Sy nc only when the synchronisation signal S _Sy nc is received in one of a plurality of separate time windows (in other words, in one of a plurality of time periods (intervals) that are temporally separated) as determined by the controller 11. These time windows are set so as to ensure that performing switch synchronising in any of the time windows will not cause (or minimise, or at least reduce) disturbance(s) in the output voltage V _ou ti caused by, e.g. a change in the switching duty cycle or a momentary change in the switching frequency.

The preferred size and timing of these time windows in relation to the switching cycle of the slave SMPS 10 may depend on factors such as the specific implementation of the SMPS (including the topology of its switching circuit) and the operating conditions, including the switching duty cycle, D. For example, where the slave SMPS 10 has a half- bridge power train in its switching circuit, as illustrated in Fig. 2A, the time windows most preferably span intervals of time between controller events 4 and 1 shown in Fig. 2B, during which the performance of switch synchronisation using the synchronisation signal S _S ync may be considered safe. As also shown in Fig. 2B, the time window may be extended all the way until just before controller event 2, but this may show a disturbance in the output voltage V _out i since the pulse will be shortened or disappear totally. In this example, the time window size is dependent on the duty cycle D. Figure 2B also illustrates the temporal relationship between the ramp (clock count C) of the clock of the SMPS 30 discussed below and the switching cycle of the SMPS 10.

It will be appreciated that Fig. 2B merely shows examples of how the time windows may be set for the particular exemplary implementation of the slave SMPS 10 shown in Fig. 2A. More generally, the time windows to be used can easily be set by considering the operation of the particular SMPS at hand and fine-tuning by trial-and-error adjustments, for example, or simply by systematically trialling different time windows in the switching cycle to identify those that avoid or reduce the problems discussed above. Figure 3 illustrates some additional features which may be included in the master SMPS 30 and the slave SMPS 10 in the present embodiment.

Besides the controller 11, the slave SMPS 10 shown in Fig. 3 also has a switching circuit 13 comprising one or more switching devices (e.g. transistors such as MOSFETs) that are connected and controlled to switch between conducting ("ON") and non-conducting ("OFF") states with a switching duty cycle that is determined by the controller 11, such that the slave SMPS 10 converts the input voltage V _in to the output voltage V _out i. The controller 11 may, as in the present embodiment, be provided in the form of a Pulse Width Modulator (PWM). The switching circuit 13 may, for example, comprise a buck converter having a single switching device and a diode, or employ a more complex arrangement. For example, if the SMPS 10 includes an isolation transformer, the switching circuit 13 may comprise a half-bridge arrangement of two switching devices, a push-pull arrangement or, in higher-power applications, a full-bridge arrangement of four switching devices on the primary side of the transformer. Those skilled in the art will appreciate that the switching circuit 13 may be configured in other ways, depending on various operational requirements. The switching circuit 13 may therefore comprise additional components to those shown in Fig. 3 (such as an isolation transformer, and a rectifying network, choke, output capacitor etc. on the secondary side of the transformer), depending on the selected converter topology and requirements of the user. The need for, and configuration of, such further power train components in various converter topologies will be familiar to those skilled in the art, such that further explanation thereof is unnecessary here.

As illustrated in Fig. 3, the controller 11 may, as in the present embodiment, have a clock 14 and be configured to control a timing at which the switching device(s) in the switching circuit 13 is/are switched based on the timings at which the clock 14 is repeatedly reset. As will be explained in the following, the clock 14 may be reset by the controller 11 in response to receiving the synchronisation signal S _Sy nc or independently of S _Sync - The controller 11 may also have a receiver module 15 configured to receive the synchronisation signal S _Sy nc (which can be communicated by the master SMPS 30 by any suitable means), and a switching control module 16 configured to control the switching of the switching device(s) in the switching circuit 13. The switching control module 16 is configured to synchronise the switching of the switching device(s) with the switching of the switching device(s) in the switching circuit 34 of the master SMPS 30 using the received synchronisation signal S _Sy nc only when the synchronisation signal is received by the receiver module 15 in one of the aforementioned time windows, as will be explained in more detail below. The switching circuit 34 forming part of the master SMPS 30 is the same as switching circuit 13 of the slave SMPS 10 or a variant thereof as described above. The master SMPS 30 includes a controller 31 having a clock 33, which is configured to repeatedly count to a predetermined count (number) before resetting. The times at which the clock 33 resets mark the temporal boundaries between adjacent switching periods (or sets of two or more adjacent switching periods, if N > 1) of the master SMPS 30. In other words, the frequency at which the controller 31 controls the switch(es) in the switching circuit 34 to switch ON and OFF is based on the temporal separation of the edges in the saw-tooth pattern in a plot of the clock's count versus time (discussed further below, with reference to Figs. 10 and 11). The master SMPS 30 is configured to generate and transmit the synchronisation signal S _Sy nc (e.g. in the form of a pulse) to the slave SMPS 10 every time the clock 33 is reset (either at the time of reset or after a predetermined delay following the reset).

In response to receiving the synchronisation signal S _Syn c, but only while a count C of the clock 14 is between a first count value, C _M i _n , and a second count value, C _Max , higher than the first count value, the switching control module 16 of the slave SMPS 10 is configured to operate in a synchronised mode so as to synchronise the switching of its switching device(s) with the switching of the switching device(s) of the master SMPS 30 using the received synchronisation signal S _Sy nc by resetting the clock 14 in response to receiving the synchronisation signal S _Sy nc (taking the aforementioned predetermined delay (if any) into account). The controller 11 is further configured to operate in a non-synchronised mode when the synchronisation signal S _Sync is not received while the count of the clock 14 is between the first count value and the second count value, by resetting the clock 14 when the count of the clock 14 reaches the second count value.

Fig. 4 illustrates an exemplary implementation of the clock 33 of the master SMPS 30. As illustrated in Fig. 4, the clock 33 is configured to count up to a predetermined count value C _N0 m, before resetting the count C to zero, and generating and transmitting the synchronisation signal S _Sy nc to the slave SMPS 10.

Fig. 5 illustrates an exemplary implementation of the clock 14 of the slave SMPS 10. As illustrated in Fig. 5, the clock 14 is configured to count up before it is reset by a reset (synchronisation) signal provided by the switching control module 16.

An example of logic implemented by the controller 11 of the slave SMPS 10 (in particular, the switching control module 16 thereof) to generate the reset signal for the slave clock 14 is illustrated in Fig. 6. The operation of this logic will be described in more detail below with reference to Fig. 9.

Figure 7 shows an exemplary implementation of the controller 11, in programmable signal processing hardware. The controller 31 of the master SMPS 30 may be implemented in the same way. The signal processing apparatus 400 shown in Fig. 7 comprises an input/output (I/O) section 410 for receiving the synchronisation signal S _Sy nc- The signal processing apparatus 400 further comprises a processor 420, a working memory 430 and an instruction store 440 storing computer-readable instructions which, when executed by the processor 420, cause the processor 420 to perform the processing operations hereinafter described to synchronise the switching of the slave SMPS 10 with the switching of the master SMPS 30, in order to eliminate or at least reduce the occurrence of a current component at a beat frequency on the input power rail to the SMPSs 10 and 30. The instruction store 440 may comprise a ROM which is pre-loaded with the computer-readable instructions. Alternatively, the instruction store 440 may comprise a RAM or similar type of memory, and the computer-readable instructions can be input thereto from a computer program product, such as a computer-readable storage medium 450 such as a CD-ROM, etc. or a computer-readable signal 460 carrying the computer-readable instructions. In the present embodiment, the combination 470 of the hardware components shown in Fig. 7, comprising the processor 420, the working memory 430 and the instruction store 440, is configured to implement the functionality of the aforementioned controller 11, including the clock 14, receiver module 15, and switching control module 16, which will now be described in detail with reference to Fig. 8.

Figure 8 is a flow chart illustrating a process by which the controller 11 synchronises the switching of the slave SMPS 10 with the switching of the master SMPS 30 in the present embodiment.

In step S100, the controller 11 receives the synchronisation signal S _Sy nc-

In step S200, the controller 11 synchronises the switching of the SMPS 10 with the switching of the second SMPS 30 using the received synchronisation signal S _Syn c only if the synchronisation signal S _Sy nc has been received by the controller 11 in one of the time windows.

The process by which the controller 11 (more specifically, the switching control module 16) selectively synchronises the switching of the slave SMPS 10 with the switching of the master SMPS 30 in step S200 will now be described in more detail with reference to Fig. 9.

In step S201, the controller 11 beings operating in a synchronised mode ('Sync mode'), in which the switching of the slave SMPS 10 is (or, at this stage of the process, assumed to be) synchronised with the switching of the master SMPS 30.

In step S202, the controller 11 resets the clock 14 by setting the count C of the clock 14 to zero. In step S203, the controller 11 determines whether the count C has reached a nominal count C _Nom , where the time taken by the clock 14 to count to C _Nom corresponds to the switching period of the slave SM PS 10 (or N times the switching period, in case N > 1). By way of an example, C _Nom = 2000 in the present embodiment. As C < C _Nom at this stage, the process proceeds to step S204.

In step S204, the controller 11 determines whether C has exceeded a maximum count Civiax, which is greater than C _Nom - By way of an example, C _Ma x = 2100 in the present embodiment. As C is not greater than C _Max at this stage, the process proceeds to step S205.

In step S205, the controller 11 determines whether C has exceeded a minimum count Civiin, which is smaller than C _Nom . By way of an example, C _M m = 1900 in the present embodiment. As C is not greater than C _M in at this stage, the process proceeds to step S206, in which the count C is incremented by 1. The process then loops back to step S203.

After the loop of steps S203 to S206 has been repeated C _M m times, the process proceeds from step S205 to step S207, in which the controller 11 determines whether the synchronisation signal S _Sy nc has been received within the immediately preceding count period (i.e. from the last time the count was incremented by 1 in step S206). If the synchronisation signal S _Sy nc is determined to have been received, then the process proceeds to step S208, wherein the controller 11 synchronises the switching of the switching device(s) in the switching circuit 13 of the slave SM PS 10 with the switching of the switching device(s) in the switching circuit 34 of the master SMPS 30 by resetting the clock 14, specifically, by setting C = 0. The controller 11 is then set to continue operating in the synchronised mode in step S209 (e.g. by setting and storing a 'Sync mode' flag), and the process loops back to step S203. The controller thus synchronises the clock 14 of the slave SM PS 10 with the clock 33 of the master SM PS 30 if (and only if) the synchronisation signal S _Sy nc is received after one of the 'time window' is entered upon C reaching the minimum count C _M m- On the other hand, if it is determined in step S207 that the synchronisation signal S _Sy nc has not been received, the count C is incremented by 1 in step S210, and the process loops back to step S203. The loop consisting of the sequence of steps S203 to S205, S207 and S210 is then repeated until a positive determination is made in step S207, or C exceeds Civiax in step S204. If C exceeds C _Ma x in step S204, then the synchronisation signal S _Syn c has not been received in the allowed time window, and the control ler 11 begins to operate in a non-synchronised mode ('Non-Sync mode') in step S211, and the process then loops back to step S203.

As the count C now exceeds C _Nom , a positive determination is made is step S203, and the process proceeds to step S212, in which the controller 11 determines whether it is currently operating in the Non-Sync mode. If this determination is negative, then the process proceeds to step S204. On the other hand, if this determination is positive, then the process loops back to step S202, wherein the controller 11 resets the clock 14 by setting the count C of the clock 14 to be equal to zero. I n this way, the controller 11, having attempted and failed to receive the synchronisation signal S _Syn c in the allowed time window that occurred between the count value C being between C _M m and C _Max , resets the clock 14 independently of the synchronisation signal S _Sy nc, and then continues to operate in the Non-Sync mode.

In the next switching period (or set of N > 1 switching periods, as the case may be), the controller 11 repeats the loop consisting of steps S203 to S206, and then the loop consisting of step S203 to S207 and S210 until either the synchronisation signal S _Sync is determined in step S207 to have been received ("Yes" in step S207) or C reaches the value of C _Nom ("Yes" in step S203). In this way, the controller 11 continues to operate in the Non-Sync mode, resetting the clock 14 each time the count C reaches the nominal value C _N0 m so that the switching of the slave SM PS 10 proceeds at the timing of the slave SMPS's clock 14, whilst attempting to synchronise the clock 14 of the slave SMPS 10 to the clock 33 of the master SM PS 30 using the synchronisation signal S _Sync provided that the synchronisation signal S _Sy nc is received in one of the allowed time windows (i.e. corresponding to the periods of time during which C is between C _M in and C _Nom ). By not making use of any synchronisation pulse that are received outside these allowed time windows, the controller 11 allows the problems inherent in the conventional synchronisation scheme summarised above to be circumvented.

[Experimental Results]

The results of a Simulink™ simulation of the above embodiment are shown in Figs. 10 and 11. In these simulations, the C _N0 m = 2000, C _M m = 1900, and C _Max = 2100. The clock 14 of the slave SMPS 10 runs at 4% higher clock frequency than the clock 33 of the master SMPS 30. These extreme values are chosen for simplicity, in order to clearly illustrate the described synchronisation scheme. In the Simulink™ simulation shown in Fig. 10, the count (or 'ramp') of the clock 33 of the master SMPS 30 is shown in trace 1, while the count kept by the clock 14 of the slave SMPS 10 is shown in trace 2. The corresponding reset signals are also shown, as well as an AND-ed signal (Reset at the same time) between the reset signals, in order to show when the reset is performed at the same time. The disturbance signal (discussed below) is not used in this simulation.

In the beginning, the master and slave clocks count to C _Nom = 2000. It is easy to observe that the period of clock 14 is shorter than the period of clock 33. Slightly after time t = 0.05, the count of clock 33 is reset, the count of clock 14 is above C _M m = 1900, and clock 14 is reset at the same time and operation proceeds in the Sync mode. The next reset of clock 14 is performed at the same time as that of clock 33, and the periods become very similar. Since the clock 14 is faster, its counter exceeds C _Nom .

The simulation shown in Fig. 11 illustrates what happens when the synchronisation signals S _Sy nc disappear, owing to some disturbance (e.g. noise or a communication failure). From time t = 0.4, the disturbance prevents the synchronisation signals S _Sy nc from reaching the controller 11 of the slave converter 10. The clock 14 of the controller 11 continues to count until its count C reaches C _Ma x = 2100, and then its resets and enters Non-Sync mode. In the following ramp cycles, the clock 14 counts to C _Nom . Now the controller 11 waits for the synchronisation signal S _Sy nc to be received again and within the allowed time window.

[Modifications and Variations] Many modifications and variations can be made to the embodiments described above.

For example, although the power supply system 100 of the above embodiment employs SMPSs in the form of DC/DC converters, it will be appreciated that the control techniques described herein are not limited to SMPSs of this kind and a power supply having such SMPSs. For example, in another embodiment, the SMPSs may be provided in the form of an AC/DC converter, for example. Moreover, the power supply system 100 may comprise one or more such AC/DC converters and one or more such DC/DC converters.

Furthermore, the controller 11 (or any described component thereof) need not be implemented in digital signal processing hardware, as described above, but may alternatively be implemented as an analog circuit or a combination of an analog circuit and digital signal processing hardware, using techniques known to those skilled in the art.

The ordering of steps in Fig. 9 may be varied. For example, the ordering of steps S204 and S205, and/or the ordering of steps S208 and S209 may be reversed. The latter steps may alternatively be performed in parallel.