SYNCHRONIZATION SIGNAL TRANSMISSION AND RECEPTION Cross Reference to Related Applications

This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 62/444,113 entitled “Method of Synchronization Signal Transmission and Reception,” filed January 9, 2017, the disclosure of which is incorporated herein by reference; U.S. Provisional Patent Application No. 62/467,636 entitled“Synchronization Signal Transmission and Reception,” filed March 6, 2017, the disclosure of which is incorporated herein by reference; and U.S. Provisional Patent Application No. 62/474,467 entitled “Synchronization Signal Transmission and Reception,” filed March 21, 2017, the disclosure of which is incorporated herein by reference. Field

Embodiments of the present disclosure generally relate to the field of networks, and more particularly, to apparatuses, systems, and methods for synchronization signal transmission and reception. Background

In a cellular communication system, a base station may enable a device, such as, for example, a user equipment (UE), to access a cellular network, which may also be referred to as a cell, supported by the base station. A base station may transmit a synchronization signal (SS) for each cell available for the UE to access. In order to access a cell, a UE may engage in a cell search procedure. The cell search procedure may include a synchronization procedure that includes detection of the SS’s for available cells.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Fig.1 illustrates an example of an SSS structure. Fig.2 illustrates an example of false cell detection.

Fig.3 illustrates an example SSS sequence mapped within an SS bandwidth according to some embodiments.

Fig.4 illustrates another example SSS sequence mapped within an SS bandwidth according to some embodiments.

Fig.5 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments.

Fig.6 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments.

Fig.7 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments.

Fig.8 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments.

Figs.9A and 9B illustrate example SSS sequence mappings according to some embodiments, where:

Fig.9A illustrates an example SSS sequence mapping of a length 127 sequence; and

Fig.9B illustrates an example SSS sequence mapping of a length 255 sequence. Fig.10 illustrates an example operation flow/algorithmic structure of a base station according to some embodiments.

Fig.11 illustrates another example operation flow/algorithmic structure of a base station according to some embodiments.

Fig.12 illustrates yet another example operation flow/algorithmic structure of a base station according to some embodiments.

Fig.13 illustrates an example detected transmitted SSS sequence according to some embodiments.

Fig.14 illustrates an example operation flow/algorithmic structure of a UE according to some embodiments.

Fig.15 illustrates yet another example operation flow/algorithmic structure of a base station according to some embodiments.

Fig.16 illustrates another example operation flow/algorithmic structure of a UE according to some embodiments.

Fig.17 illustrates an example architecture of a system of a network according to some embodiments. Fig.18 illustrates example components of a device according to some

embodiments.

Fig.19 illustrates example interfaces of baseband circuitry according to some embodiments.

Fig.20 is a block diagram illustrating example components according to some embodiments. Detailed Description

The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc., in order to provide a thorough understanding of the various aspects of the claimed embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the embodiments claimed may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of embodiments of the present disclosure with unnecessary detail.

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that alternate embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that alternate embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

Further, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the illustrative embodiments;

however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

The phrase“in various embodiments,”“in some embodiments,” and the like are used repeatedly. The phrase generally does not refer to the same embodiments; however, it may. The terms”comprising,”“having,” and“including” are synonymous, unless the context dictates otherwise. The phrase“A or B” means (A), (B), or (A and B).

Example embodiments may be described as a process depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations may be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be re-arranged. A process may be terminated when its operations are completed, but may also have additional operations not included in the figure(s). A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, and the like. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function and/or the main function.

As used herein, the term“processor circuitry” refers to, is part of, or includes circuitry capable of sequentially and automatically carrying out a sequence of arithmetic or logical operations; recording, storing, and/or transferring digital data. The term “processor circuitry” may refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single-core processor, a dual-core processor, a triple-core processor, a quad-core processor, and/or any other device capable of executing or otherwise operating computer-executable instructions, such as program code, software modules, and/or functional processes. As used herein, the term “interface circuitry” refers to, is part of, or includes circuitry providing for the exchange of information between two or more components or devices. The term“interface circuitry” may refer to one or more hardware interfaces (for example, buses, input/output (I/O) interfaces, peripheral component interfaces, and the like).

As used herein, the term“user equipment” or“UE” may be considered

synonymous to, and may hereafter be occasionally referred to, as a client, mobile, mobile device, mobile terminal, user terminal, mobile unit, mobile station, mobile user, subscriber, user, remote station, access agent, user agent, receiver, etc., and may describe a remote user of network resources in a communications network. Furthermore, the term “user equipment” or“UE” may include any type of wireless/wired device such as consumer electronics devices, cellular phones, smartphones, tablet personal computers, Internet of Things (“IoT”) devices, smart sensors, wearable computing devices, personal digital assistants (PDAs), desktop computers, and laptop computers, for example.

As used herein, the term“base station” may be considered synonymous to, and may hereafter be occasionally referred to, as access nodes (ANs) can be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNB), radio access node (RAN) nodes, and so forth, and may comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell). A base station may be a device that is consistent with cellular communications protocols, such as a Global System for Mobile Communications (GSM) protocol, a code- division multiple access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular (POC) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation (5G) protocol or a protocol that is consistent with other existing generations, generations in development or to be developed in the future (e.g., second generation (2G), sixth generation (6G), etc.), a New Radio (NR) protocol, and the like.

As explained in more detail below, an SS may enable a UE to detect and identify cells with which to connect. Further, an SS may be used to correct frequency offset and find an orthogonal frequency division multiplex (OFDM) symbol boundary or a transmission subframe boundary. For example, an SS may coarsely correct frequency offset between a transmitter and a receiver and may derive a coarse timing estimation. The timing estimation may be used to determine the OFDM symbol boundary and subframe boundary. A transmission subframe may refer to the smallest number of groups of OFDM symbols that may be used for control and data transmission. This may be referred to as a scheduling unit.

A UE may communicate with a base station in order to access a cell supported by the base station. Downlink communication may refer to a communication link from the base station to the UE, and uplink communication may refer to the communication link from the UE to the base station. A UE and a base station may transmit data at their physical layers, which may also be referred to as the PHY layer, of for example, the Open System Interconnection (which may be known as OSI), or Transmission Control

Protocol/Internet Protocol (which may be known as TCP/IP) network protocol stack. A channel defined for the physical layer in the downlink may include a physical broadcast channel (PBCH). The PBCH may be a physical channel that carries system information used by UEs in order to access a network.

The detection of the SS’s may provide a UE with the physical cell identities of available cells. An SS may include multiple components, including, for example, a primary synchronization signal (PSS), a secondary synchronization signal (SSS), and possibly a tertiary synchronization signal (TSS). In order to access a cell, a UE may undertake a cell search procedure. At the physical layer, the cell search procedure may include detection of SS’s and thus detection of SSS’s. SSS’s, which may be a signal defined for the physical layer in the downlink, may include the physical cell identities of available cells.

Fig.1 illustrates an example of an SSS structure. The SSS structure in Fig.1 may be consistent with the 3 ^rd Generation Partnership Project’s (3GPP) Long Term Evolution (LTE) standard. As shown in Fig.1, an LTE SSS structure 100 may include two maximum length sequences (M-sequences), x ₁ through x _N and y ₁ through y _N that may be interlaced in an SS bandwidth. As shown in Fig.1, SSS structure 100 may further include a number of guard subcarriers prior to and following the interlaced M-sequences.

An M-sequence (which may also be referred to as a maximum run length sequence) may be a type of pseudorandom sequence (which may also be referred to as a pseudorandom binary sequence) that may be created by cycling through possible states of a shift register of a length and may result in a sequence of that length. An M-sequence may have a length of L bits, each of which may have a value of either 0 or 1, and the M- sequence may repeat after every L bits. Thus, for example, an M-sequence that has a length L of 255 may have a sequence of 255 bits that repeats itself after every 255 bits. Two M-sequences in an SSS may be interlaced in the sense that, for example, both M- sequences may be mapped in an SS bandwidth, with a portion of each M-sequence mapped in an alternating manner, as shown in Fig.1. Because an SSS structure may include two M-sequences that may be interlaced, a UE that receives SSS’s from multiple cells simultaneously may have an issue with false cell detection.

Fig.2 illustrates an example of false cell detection. As shown in Fig.2, four cells may each provide a UE 200 with a cell identity that includes two information components in an SSS, one representing a first sequence and the other representing a second sequence interlaced with the first sequence. For each first and second sequence, a sequence for a cell is selected from a pool of sequences for the first and second sequence, respectively. For example, the first and second M-sequences, respectively, for cell #1202 may be {1,1}, for the cell #2204 may be {1,2}, for the cell #3206 may be {2,3}, and for cell #4 208 may be {2,3}. For a cell, {X,Y} refers to an X ^th sequence among the pool of sequences for the first sequence, and a Y ^th sequence among the pool of sequences for the second sequence.

An issue with false cell detection may arise if the UE 200 detects a cell that does not exist, where the UE 200 may combine the detected sequence index of one cell and the detected sequence index of a different cell, to detect a cell identity for a cell that does not exist. For example, the UE 200 in Fig.2 may detect a first sequence of 1 and a second sequence of 3, for a cell identity of {1,3}, which is not the cell identity of any of the four cells that transmitted cell identities to the UE 200. This may happen if, for example, one cell, such as, for example, cell #1202 or cell #2204, transmits a 1 as the first sequence, and another cell, such as, for example, cell #3206 or cell #4208 transmits a 3 as the second sequence. Consequently, the UE 200 may create a cell that may be referred to as a ghost cell having the cell identity {1,3}, and thus have an issue with false cell detection, where the UE 200 may detect a cell that does not exist as one of the cells transmitting a cell identity to the UE 200.

Embodiments herein may include an SSS structure that may include a single, long sequence that may span an SS bandwidth. The single, long sequence may be generated, for example, by combining multiple M-sequences, and for example, using a complex scrambling code. Embodiments herein may include an SS that includes a sequence of length N that may occupy the central N subcarriers of an SS bandwidth, where a sequence may be generated from one of a plurality of primitive polynomials of M-sequences. In various embodiments, SSS structures may be generated from one or more primitive polynomials. In an embodiment, a primitive polynomial may be a polynomial that cannot be factored into the product of two polynomials, has a non-zero constant term, and (other than the primitive polynomial x+1) has an odd number of terms. An SSS structure generated from one or more primitive polynomials may, among other things, prevent or reduce the occurrence of false cell detection, because one sequence is transmitted to the UE, rather than two interlaced M-sequences. Additionally or alternatively, such an SSS structure may provide large cell identities. A large cell identity may, for example, increase the number of available physical cell identities. Although embodiments described herein may refer to the generation of SSS’s, such embodiments may apply to the generation of any component of an SS, including, but not limited to, for example, a PSS or a TSS.

Fig.3 illustrates an example SSS sequence mapped within an SS bandwidth according to some embodiments. In an embodiment, an M-sequence may be chosen from a set of M-sequences and mapped within an SS bandwidth. In an embodiment, an M- sequence of length L may be generated from a primitive polynomial, G(x), such as, for example, x ⁷ + x + 1, and mapped to L central subcarriers of the SS bandwidth, where each bit may be modulated using binary phase shift keying (BPSK) modulation to provide modulated bits x ₁ through x _N of SSS sequence 300. Although embodiments herein may be described in terms of an M-sequence as a pseudorandom sequence, embodiments herein are not limited to M-sequences. Other types of pseudorandom sequences may be used, such as, for example, but not limited to, a pseudorandom sequence generated from a gold code or a pseudorandom sequence generated from a Kasami code. Further, although embodiments herein are described in terms of BPSK modulation, embodiments herein are not limited to BPSK modulation. Other types of modulation may be used, such as, for example, but not limited to, quadrature phase shift keying (QPSK) modulation.

If the structure in Fig.3 is used to generate an SSS, different cell identities may be represented by different cyclic shift versions of the M-sequence. As a result, a transmitter, such as, for example, a base station, may indicate L distinct cell identities. In addition, in order to provide more information bits, the chosen M-sequence may be from one of the multiple primitive polynomials. For example, the transmitter may provide 3L different cell identities by sending one of the L cyclic shifted versions of one of the three primitive polynomials, G1(x) = x ⁷ + x + 1, G2(x) = x ⁷ + x ³ + 1, and G3(x) = x ⁷ + x ³ + x ² + x + 1. For example, if length L is equal to 127 M-sequences are used, and 3 primitive polynomials are used in the M-sequence set, the polynomial index, PID, may be derived from cell identity (which may also be referred to as a cell ID), N _ID , by P _ID = floor(N _ID /L), and the cyclic shift (which may also be referred to as CS) value of the chosen M-sequence may be derived from the cell ID by CS = (N _ID ) mod L. A cyclic shift value may also be referred to as a cyclic shift parameter.

Fig.4 illustrates another example SSS sequence mapped within an SS bandwidth according to some embodiments. In an embodiment, an M-sequence may be mapped to every K subcarriers within the central K x N subcarriers, as shown in Fig.4, where the modulated bits x1 through xN of SSS sequence 400 are mapped to every other subcarrier. In yet another embodiment, the M-sequence may be mapped with a different subcarrier offset depending on the primitive polynomial used to generate the M-sequence, where the modulated bits y ₁ through y _N of sequence 402 are mapped as shown.

Fig.5 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments. In an embodiment, an M-sequence may be multiplied by a repeated complex scrambling code and mapped within an SS bandwidth. In an embodiment, an M-sequence of length N may be generated from a primitive polynomial, G(x), such as, for example, x7 + x + 1, and BPSK modulated. Further, each BPSK modulated bit x1 through xN of SSS sequence 500 may be mapped to N central subcarriers of the SS bandwidth, where each occupied subcarrier may be multiplied by a real value 502 or a complex value 504, which may result in a BPSK modulated M- sequence that is scrambled by a complex scrambling sequence.

If this structure is used to generate an SSS, different cell identities may be mapped to different cyclic shift versions of the M-sequence. As a result, a transmitter, such as, for example, a base station, may indicate L distinct cell identities. In addition, in order to provide more information bits, a chosen M-sequence may be from one of the multiple primitive polynomials according to an embodiment. An M-sequence generated from different primitive polynomials may be multiplied with different complex scrambling sequences. For example, the transmitter may provide 2L different cell identities by sending one of the L cyclic shifted versions of one of the two primitive polynomials, G1(x) = x7 + x + 1, and G2(x) = x7 + x6 + 1. The M-sequence generated with G1(x) may be BPSK modulated and may be mapped to the central N subcarriers of the SS bandwidth, while the M-sequence generated with G2(x) may be BPSK modulated and scrambled with repeated {+1, +j} complex scrambling sequence.

Fig.6 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments. In an embodiment, two M-sequences 600 and 604 may be mapped to in-phase and quadrature constellations, respectively, of the subcarriers within an SS bandwidth, where M-sequence 600 may be multiplied by a complex value 602, for example, j, and M-sequence 604 may be multiplied by a real value 606, for example, 1.

In an embodiment, two M-sequences of length N may be generated from primitive polynomials, G1(x) and G2(x), such as x ⁷ + x + 1, and x ⁷ + x ⁶ + 1, and BPSK modulated bits z ₁ through z _N of SSS sequence 608 from the first and second primitive polynomials may be mapped to the in-phase and quadrature constellation of the N central subcarriers of the SS bandwidth, respectively, which may result in a QPSK modulated sequence.

If this structure is used for SSS, different cell identities may be determined by the two cyclic shift versions of the two M-sequences. As a result, a transmitter may indicate L ² distinct cell identities, which may increase the available number of cell IDs.

Fig.7 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments. In an embodiment, two M-sequences may be bitwise exclusive-OR (XOR) computed and mapped within an SS bandwidth, as illustrated in Fig.7, which also may equivalently illustrate an SSS generated by performing modulated symbol-wise multiplication of two BPSK modulated M-sequences. In an embodiment, two M-sequences 700 and 702 of length N may be generated from primitive polynomials, G1(x) and G2(x), such as, for example, x ⁷ + x + 1, and x ⁷ + x ⁶ + 1, and the two M-sequences 700 and 702 may be bitwise XOR computed, and the scrambled (i.e., XOR operated) sequence may be BPSK modulated, to provide modulated bits z1 through z _N of SSS sequence 704, and mapped to N central subcarriers of the SS bandwidth.

Equivalently, two M-sequences 700 and 702 of length N may be generated from primitive polynomials, G ₁ (x) and G ₂ (x), such as, for example, x ⁷ + x + 1, and x ⁷ + x ⁶ + 1, and the two M-sequences 700 and 702 may be BPSK modulated, and the modulated sequence may be multiplied with each other for each modulated symbol, to provide modulated bits z ₁ through zN of SSS sequence 704, and mapped to N central subcarriers of the SS bandwidth.

If this structure is used for an SSS, different cell identities may be determined by the two cyclic shift versions of the two M-sequences. As a result, a transmitter may indicate L ² distinct cell identities, and thus may increase the available number of cell IDs.

In an embodiment, the two primitive polynomials may be chosen to obtain good cross-correlation properties between two distinct SS sequences. Examples of primitive polynomial pairs are shown in Table 1. Table 1. Primitive Polynomials

In an embodiment, the sequence d(0),…,d(L-1) may be used for the secondary synchronization signal may be a gold sequence, which may be a bitwise XOR of two length-127 binary M-sequences generated from G1(x) and G2(x) primitive polynomials, respectively.

A gold-like sequence as an SSS, d(n), may be defined as

d(n) = (1– 2∙ ((c ₀ (n) + c ₁ (n)) mod2), n = 0,… L.

The two sequences c ₀ (n) and c1(n) are defined as two different cyclic shifts of the M-sequence s ₀ (n) and s ₁ (n) according to

c ₀ (n) = s0((n + m0)mod L),

c ₁ (n) = s ₁ ((n + m ₁ )mod L), where s0(n) and s1(n) are the M-sequence generated from primitive polynomials G ₁ (x) and G ₂ (x), respectively.

Physical cell ID, NID, may be determined by:

When L = 127, s ₀ (n) and s ₁ (n) may be M-sequences generated from G ₁ (x) = x ⁷ + x ³ + 1, and G2(x) = x ⁷ + x ³ + x ² + x +1, respectively. Both M-sequences may be generated with initial conditions {0,0,0,0,0,1}.

The following may be the sequence s0(n) of length 127:

{1,0,0,0,0,0,0,1,0,0,0,1,0,0,1,1,0,0,0,1,0,1,1,1,0,1,0,1,1,0 ,1,1,0,0,0,0,0,1,1,0,0,1,1,0 ,1,0,1,0,0,1,1,1,0,0,1,1,1,1,0,1,1,0,1,0,0,0,0,1,0,1,0,1,0,1 ,1,1,1,1,0,1,0,0,1,0,1,0,0,0,1,1,0,1, 1,1,0,0,0,1,1,1,1,1,1,1,0,0,0,0,1,1,1,0,1,1,1,1,0,0,1,0,1,1, 0,0,1,0,0}. The above formulation may be provided in the following recursive form:

s(n + 7) = (s(n + 3) + s(n))mod2, 0 < n < 127,

where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0

The following may the sequence s ₁ (n) of length 127:

{1,0,0,0,0,0,0,1,0,0,0,1,1,1,1,1,0,1,0,0,1,1,0,1,0,0,0,1,0,1 ,1,1,1,0,1,1,0,1,1,1,0,1,1,1 ,1,1,1,1,0,0,0,0,1,0,1,0,1,1,0,0,0,1,0,0,1,1,1,1,0,0,1,0,1,0 ,0,1,0,0,1,0,1,1,0,1,0,1,0,1,0,0,0,0, 0,1,1,0,0,1,0,0,0,0,1,1,1,0,1,0,1,1,1,0,0,1,1,1,0,0,0,1,1,0, 1,1,0,0,1}.

The above formulation may be provided in the following recursive form;

s(n + 7) = (s(n + 3) + s(n + 2) + s(n + 1) + s(n))mod2, 0 < n < 127,

where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

When L = 255, s0(n) and s1(n) may be M-sequences generated from primitive polynomials, for example, G ₁ (x) = x ⁸ + x ⁷ + x ⁶ + x ⁵ + x ² + x +1, and G ₂ (x) = x ⁸ + x ⁷ + x ⁶ + x + 1, respectively. Both M-sequences may be generated with initial conditions

{0,0,0,0,0,0,1}.

The following may be the sequence s ₀ (n) of length 255:

{1,0,0,0,0,0,0,0,1,1,0,0,1,1,1,1,1,0,1,0,0,0,1,1,0,1,1,0,1,0 ,1,0,1,0,1,1,0,1,0,0,1,1,0,0 ,0,1,0,1,0,0,1,0,0,1,0,0,0,1,0,0,0,1,1,1,0,1,0,0,1,0,1,0,0,0 ,1,0,,1,1,1,1,0,1,0,1,1,1,1,1,0,0,1,0 ,0,0,0,1,0,0,0,0,0,1,0,0,1,1,0,1,1,1,0,0,1,1,0,1,0,0,0,0,0,0 ,1,0,1,0,1,0,0,0,0,1,1,1,0,0,1,0,1,1, 0,1,1,1,1,1,1,1,1,0,1,1,1,0,1,0,1,0,0,1,1,1,1,0,1,1,0,1,1,0, 0,1,1,0,0,1,0,0,1,1,1,0,1,1,1,1,0,0, 1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,0,1,1,0,0,0,1,1,0,0,0,0,1,1,0, 1,0,1,1,0,0,1,0,1,0,1,1,1,0,0,0,0,0, 1,1,1,1,1,1,0,0,0,1,0,0,1,0,1,1,1,0,1}.

The above formulation may be provided in the following recursive form:

s(n + 8) = (s(n + 7) + s(n + 6) + s(n +5) + s(n + 2) + s(n + 1) + s(n)) mod 2, 0≤ n≤ 255,

where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = s(7) = 0.

The sequence s ₁ (n) may be provided in the following recursive form:

s(n + 8) = (s(n + 7) + s(n + 6) + s(n +1) + s(n)) mod 2, 0≤ n≤ 255,

where s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = s(7) = 0,

which may result in the following sequence of length 255:

{1,0,0,0,0,0,0,0,1,1,0,1,1,0,1,0,1,0,0,0,1,0,0,1,0,1,1,1,1,0 ,0,1,0,1,0,0,0,1,0,0,0,1,1,0 ,0,1,1,0,0,0,1,1,1,0,0,0,0,1,1,0,0,0,0,0,1,1,1,0,1,1,0,0,0,0 ,1,0,1,0,1,1,0,0,1,0,0,1,1,1,0,0,1,1, 1,0,1,0,1,0,1,1,1,1,1,1,1,1,0,1,1,0,1,1,0,0,1,1,1,1,0,0,0,1, 1,0,1,0,1,1,1,0,0,1,0,0,0,0,1,1,1,1, 0,1,1,1,0,1,1,1,1,0,1,0,0,0,0,0,1,0,0,0,0,0,0,1,0,1,1,0,1,1, 1,1,1,0,0,1,1,0,1,1,1,0,0,0,1,0,1,1, 1,0,1,0,0,1,1,0,0,1,0,1,0,1,0,1,0,0,1,0,0,1,0,0,0,1,0,1,0,0, 0,0,1,0,0,1,1,0,1,0,0,0,1,1,1,1,1,0, 1,0,1,1,0,1,0,0,1,0,1,0,0,1,1,1,1,1}.

In another embodiment, an SSS may be composed of multiplication of two sequences. The first sequence may be determined by the sequence used for the PSS, the PSS index. For example, if 3 sequences may be used for PSS, the PSS index may be 0, 1, and 2. Based on the PSS index, the first sequence may be determined. For example, if the first sequence is based on M-sequence, the PSS index may determine the cyclic shift of the M-sequence (or equivalently the initial state of the M-sequence) for the first sequence. The second sequence, which may be bitwise XOR (or equivalently symbol wise multiplied when each bit is modulated by BPSK) computed with the first sequence, may be selected from a set of sequences that may be generated with one or more primitive polynomials. For example, for length 127 sequences for the second sequence, one or more primitive polynomial may be selected from Table 2. In an embodiment, when the first sequence and the second sequence are both M-sequences, the selected polynomial for the first sequence and the pool of polynomials for the second sequence may be different polynomials (all distinct primitive polynomials). Table 2. Primitive Polynomial for the M-Sequence

For example, three sets of polynomials, G0(x) = x ⁸ + x ⁷ + x ⁶ + x ¹ + 1, G1(x) = x ⁸ + x ⁷ + x ² + x ¹ + 1, and G ₂ (x) = x ⁸ + x ⁷ + x ⁵ + x ³ + 1 may be used. Polynomial G ₀ (x) may be used to generate a first sequence, where it is initialized by {0,0,0,0,0,0,0,1} and cyclically shifted by a PSS index. The polynomials G1(x) and G2(x) may be used to generate a set of sequences, where they may be initialized by {0,0,0,0,0,0,0,1}. Depending on the cell ID, one of the sequences generated from G1(x) and G2(x) may be selected. The cell ID may also be determined by the cyclic shift of the selected sequence.

In the example above, the cell ID, N _ID , may be computed by combination of two values PID, SID: NID = PID + 3*SID, where PID is the PSS index, and the SID is the SSS index. A group index, F, may determine the polynomial of the second sequence and may be computed by F = floor(SID/L), where L is the length of the second M- sequence. For above, L = 255. The second sequence may be generated by G _F (x) polynomial, and the cyclic shift value, CS, may be determined by CS = (SID) mod L. This can potentially support up to 2x255x3 = 1530 cell IDs. Embodiments herein may reduce peak-to-average-power ratio (PAPR) or the cubic metric (CM) of a transmit signal. Transmit signals in an OFDM system may experience high fluctuations in amplitude, which may impact the power capabilities of cellular network communication devices. The PAPR and the CM may be used to determine amplitude fluctuations in OFDM signal. The generation of an SSS in accordance with embodiments here may reduce the PAPR or the CM of a transmit signal.

Generation of an SSS, d(n), with two M-sequences, in accordance with embodiments herein, for example, as described in connection with Fig. 7, may be described as below:

or equivalently

The two sequences c ₀ (n) and c1(n) may be defined as two different cyclic shifts of the M-sequences s0(n) and s1(n) according to, for example,

c ^{(m )}

0 ₀ (n) = s0((n+ m ₀ )mod L)

c ^{(m )}

1 ₁ (n) = s ₁ ((n+ m ₁ )mod L),

where s0(n) and s1(n) are the M-sequences generated from the primitive polynomials G ₁ (x) and G ₂ (x), respectively. The initial state of the M-sequence may be set as s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0 for sequence length of 127, and s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = s(7) = 0 for sequence length of 255.

Physical cell ID, N _ID , may be determined by

In an embodiment, the first M-sequence generated by G ₁ (x) may use a limited set of cyclic shifts, while the second M-sequence generated by G2(x) may use all sets of cyclic shifts. If the first M-sequence uses a limited set of cyclic shifts, the PAPR or CM of the described SSS may be optimized based on, for example, selection of the primitive polynomial of the M-sequences and cyclic shifts of the first M-sequence. An SSS design for optimized PAPR or CM according to embodiments herein, including, for example, as described in connection with Fig. 7, may be described as:

or equivalently

The two sequences c ₀ (n) and c ₁ (n) may be defined as two different cyclic shifts of the M-sequences s0(n) and s1(n) according to

c ^{(m )}

0 ₀ (n) = s ₀ ((n + N _CS ∙ m ₀ + N _OFFSET )mod L)

c ^{(m )}

1 ₁ (n) = s ₁ ((n + m ₁ )mod L),

where s ₀ (n) and s ₁ (n) may be the M-sequences generated from the primitive polynomials G1(x) and G2(x), respectively.

Physical cell ID, N _ID , may be determined by

The N _CS and N _OFFSET values may be optimization parameters, where N _CS represents a gap between two cyclic shifts, and NOFFSET is the cyclic shift offset.

Table 3 includes a list of primitive polynomials and their mapping to polynomial index for M-sequence of length 127, in accordance with some embodiments. The polynomial index may be used in Table 4 and Table 5, in accordance with some embodiments.

Table 3. List of Candidate Primitive Polynomials for Length 127 M-Sequence

Table 4 shows an example list of maximum cubic metric (CM) value of the SSS with various values of N _CS , N _OFFSET , and primitive polynomials, in accordance with some embodiments. Table 4 lists sets of parameters from smallest maximum CM to the highest maximum CM from randomly selected set of parameters. In accordance with some embodiments, different selection of the primitive polynomials and NCS, NOFFSET parameters may result in a wide range of maximum CM values. Therefore, selection of the primitive polynomials and cyclic shift parameters may optimize the PAPR and CM of the SSS, in accordance with some embodiments.

Table 4. Maximum CM of SSS using two M-Sequences of Length 127

In some embodiments, an SSS may be optimized for the cross correlation profile between two SSS sequences that may belong to different cell identities for a sequence length of 127.

Table 5 shows the minimum and maximum cross correlation for a parameter set that may have low maximum CM and PAPR, in accordance with some embodiments. For example, Table 5 indicates that G1(x) = x ⁷ +x ⁶ +x ⁴ +x+1 and G2(x) = x ⁷ +x ⁵ +x ³ +x+1 with N _CS = 1 and N _OFFSET = 0, may result in a low PAPR and CM profile, while maintaining a low cross-correlation profile.

Table 5. Cross-Correlation Analysis of SSS Design of Length 127 with Different

Polynomials and N _CS and N _OFFSET Parameters

Table 6 includes primitive polynomials and mappings to a polynomial index for an M-sequence of length 127, in accordance with some embodiments. The polynomial index may be used in connection with Table 7 and Table 8, in accordance with some embodiments.

Table 6. List of Candidate Primitive Polynomials for Length 255 M-Sequence

Table 7 shows an example list of maximum CM value of the SSS with various values of NCS, NOFFSET, and primitive polynomials for sequence length of 255. The table includes sets of parameters from smallest maximum CM to highest maximum CM from randomly selected set of parameters, in accordance with some embodiments. Table 7 indicates that different selection of the primitive polynomials and NCS, NOFFSET parameters may result in wide range of maximum CM values, in accordance with some embodiments. Therefore, selection of the primitive polynomials and cyclic shift parameters may optimize the PAPR and CM of the SSS, in accordance with some embodiments.

Table 7. Maximum CM of SSS using Two M-Sequences of Length 255

In some embodiments, an SSS may be optimized for the cross correlation profile between two SSS sequences that may belong to different cell identities. Table 8 indicates the minimum and maximum cross correlation for a parameter set that may have low maximum CM and PAPR, in accordance with some embodiments. For example, Table 8 indicates that G1(x) = x ⁸ +x ⁷ +x ⁶ +x ⁵ +x ² +x+1 and G2(x) = x ⁸ +x ⁷ +x ⁶ +x ³ +x ² +x+1 with NCS = 7 and N _OFFSET = 11, may result in low PAPR and CM profile, while maintaining a low cross-correlation profile.

Table 8. Cross-Correlation Analysis of SSS Design of Length 255 with Different

Polynomials and N _CS and N _OFFSET Parameters

Fig.8 illustrates yet another example SSS sequence mapped within an SS bandwidth according to some embodiments. In an embodiment, an SSS sequence 804 may be a mix of SSS generation as described in connection with Fig.3 and SSS generation as described in connection with Fig.7, where a first M-sequence 800 may be generated based on a PSS index, and a second M-sequence 802 may be selected from a pool of M- sequences generated from primitive polynomials, and the two M-sequences may be bitwise XOR computed or modulated and symbol-wise multiplied.

Fig.9 illustrates an example SSS sequence mapping according to some embodiments. Downlink and uplink transmissions may be organized into frames, which may be divided into slots, which may include symbols. A symbol may include resource blocks, and a resource block may include resource elements. A resource element, which may also be referred to as a tone, may be the underlying data carrier in a frame and thus may include data from a signal.

A PSS and an SSS may be transmitted from a base station to a UE in a

synchronization signal and PBCH block, which may correspond to an SS bandwidth. A synchronization signal and PBCH block may include OFDM symbols and a number of contiguous subcarriers that correspond to the OFDM symbols, where the PSS and SSS may be spread across a number of subcarriers for transmission to the UE. A PSS and an SSS may have certain relationship in terms of their relative locations in the SS bandwidth. A base station may modulate data symbols for transmission on the PBCH.

Referring to Fig.9A, for a length 127 sequence, for example, the SSS sequence d(n) may be mapped to the resource elements, according to

a _{k, l + 1} = d(n), n = 0,…127

k = n– 64.

A PSS may be mapped to symbol l +1 of the SS block.

Resource elements (k, l) in OFDM symbols may be used for transmission of the PSS, where k = -72, -71,…, -65, 64, 65,…, 72, may be reserved and not used for transmission of the PSS, and may include 127 tones 900A, nine tones 902A prior to 127 tones 900A, and eight tones 904A following 127 tones 900A.

Referring to Fig.9B illustrates another example sequence mapping according to some embodiments. For example, for a length 255 sequence, the SSS sequence d(n) may be mapped to the resource elements according to

a _{k, l + 1} = d(n), n = 0,…255

k = n– 128. The PSS may be mapped to symbol l+1 of the SS block.

Resource elements (k, l) in OFDM symbols may be used for transmission of the PSS where k = -143, -142,…, -129, 128, 129,…, 143 may be reserved and not used for transmission of the PSS, and may include 255 tones 900B, nine tones 902B prior to 255 tones 900B, and eight tones 904B following 255 tones 900B.

An antenna port may be a logical entity, rather than a physical entity. For example, multiple antenna port signals may be transmitted on a single physical transmit antenna. Further, multiple antenna port signals may be transmitted across multiple physical transmit antennas. In an embodiment, the same antenna port may be used for both a PSS and an SSS.

Fig.10 illustrates an example operation flow/algorithmic structure of a base station according to some embodiments. In embodiments herein, a base station may be a gNB that is consistent with the 5G protocol or a base station that is consistent with generations in development or to be developed in the future, e.g., 6G, etc. However, embodiments herein are not limited to such base stations.

Operation flow/algorithmic structure 1000 may include, at 1002, determining, based on a primitive polynomial, an M-sequence that has a length. In an embodiment, determining, based on the primitive polynomial, the M-sequence that has the length, may include selecting the M-sequence from a set of M-sequences generated from a set of primitive polynomials. In another embodiment, determining, based on the primitive polynomial, the M-sequence that has the length, may include generating, based on the primitive polynomial, the M-sequence that has the length, where operation

flow/algorithmic structure 1000 may further include multiplying each of the central subcarriers by a repeated complex scrambling sequence. Operation flow/algorithmic structure 1000 may further include, at 1004, performing a cyclic shift of the M-sequence to generate a cyclic-shifted M-sequence. Operation flow/algorithmic structure 1000 may further include, at 1006, modulating, using BPSK modulation, the cyclic shifted M- sequence to generate BPSK-modulated bits of an SSS sequence. Operation

flow/algorithmic structure 1000 may further include, at 1008, mapping BPSK-modulated bits of the SSS sequence to central subcarriers of an SS bandwidth for transmission, where the number of the central subcarriers corresponds to the length of the M-sequence.

Fig.11 illustrates another example operation flow/algorithmic structure of a base station according to some embodiments. Operation flow/algorithmic structure 1100 may include, at 1102, generating, based on two distinct primitive polynomials, two M- sequences, where each M-sequence has a length. In an embodiment, operation flow/algorithmic structure 100 may further include receiving the two distinct primitive polynomials from a memory.

In an embodiment, the length may be, for example, 127. In another embodiment, the length may be, for example, 255.

Operation flow/algorithmic structure 1100 may further include, at 1104, performing a cyclic shift of the M-sequences to generate two cyclic-shifted M-sequences. In an embodiment, a cyclic shift may be based on an identity of a cellular network. In an embodiment, operation flow/algorithmic structure 1100 may further include performing a bitwise XOR operation on the two cyclic-shifted M-sequences. Operation

flow/algorithmic structure 1100 may further include, at 1106, modulating, using BPSK modulation, the two cyclic shifted M-sequences to generate BSPK-modulated bits of an SSS sequence. In an embodiment, operation flow/algorithmic structure 1100 may further include performing a modulated symbol-wise multiplication of the BPSK-modulated bits of the two cyclic-shifted M-sequences.

Operation flow/algorithmic structure 1100 may further include, at 1108, mapping BPSK-modulated bits of the SSS sequence to central subcarriers of an SS bandwidth for transmission, where the number of the subcarriers corresponds to the lengths of the M- sequences. In an embodiment, operating flow/algorithmic structure 1100 may further include multiplying a first M-sequence of the two M-sequences by a complex value, to provide a complex value M-sequence, and multiplying a second M-sequence of the two M-sequences by a real value, to provide a real value M-sequence multiplied sequence. In an embodiment, mapping the modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth may further include mapping the BPSK-modulated bits of the complex value M-sequence to an in-phase constellation of the central subcarriers of the SS bandwidth, and mapping the BPSK-modulated bits of the real value M-sequence to a quadrature constellation of central subcarriers of the SS bandwidth. In another embodiment, the BPSK-modulated bits of the real value M-sequence may be mapped to the in-phase constellation of the central subcarriers of the SS bandwidth, and the BPSK- modulated bits of the complex value M-sequence may be mapped to a quadrature constellation of central subcarriers of the SS bandwidth.

Fig.12 illustrates yet another example operation flow/algorithmic structure of a base station according to some embodiments. Operation flow/algorithmic structure 1200 may include, at 1202, multiplying two cyclically shifted, BPSK modulated M-sequences, to generate a sequence for an SSS, where the sequence has a length. Operation flow/algorithmic structure 1200 may further include, at 1204, mapping the sequence to a number N of central subcarriers of an SS bandwidth for transmission, where the number N of subcarriers corresponds to the length of the sequence. In an embodiment, the central subcarriers may be central continuous subcarriers.

In an embodiment, multiplying the two cyclically shifted, BPSK modulated M- sequences includes multiplying the two cyclically shifted, BPSK modulated M-sequences according to d(n) = (1-2∙ c ₀ ^(m ₀ ⁾ (n))∙ ((1-2∙ c ₁ ^(m ₁ ⁾ (n)), where d(n) is an SSS sequence, where c ₀ ^(m 0 ⁾ (n) = s0((n+ m0)mod L) is a cyclic shift of a first M-sequence s0 of the two cyclically shifted, BPSK-modulated M-sequences, and where c ₁ ^(m ₁ ⁾ (n) = s ₁ ((n+ m ₁ )mod L) is a cyclic shift of a second M-sequence s1 of the two cyclically shifted, BPSK-modulated M-sequences, where m ₀ is a first cyclic-shift value and m ₁ is a second cyclic shift value, where L is a length of the sequence, where is from 0 to L minus 1, where the first M- sequence s0(n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a first primitive polynomial, and where the second M-sequence s1(n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a second primitive polynomial. In an embodiment, L is the length that equals 127. In an embodiment, the M-sequence s0 is generated from a first primitive polynomial x ⁷ +x ⁴ +1, and the second M-sequence s ₁ is generated from a second primitive polynomial x ⁷ +x+1. In an embodiment, an initial state of the M-sequences is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0. In an embodiment, a first M-sequence s ₀ generated by the first polynomial may use a subset of available sets of cyclic shifts, and a second M-sequence s1 generated by the second primitive polynomial may use all of the available sets of cyclic shifts. In an embodiment, a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity. In an embodiment, the SSS may be mapped to a same antenna port as a corresponding PSS.

Fig.13 illustrates an example detected transmitted sequence according to some embodiments. In embodiments herein, length N of an M-sequence may be determined by the order of a polynomial used to generate the M-sequence. For example, if the order of the primitive polynomial is J, the length N may be to 2 ^J – 1. For example, a polynomial order of 7 may generate a sequence of length 127 (= 2 ⁷ – 1), and the sequence may be unique without repetition. Therefore, length N may be set to 127.

A receiver, such as, for example, a UE, may utilize differential cross correlation to detect a transmitted sequence. A length N of the M-sequence may be set to 2 ^J , which may repeat the first bit at the 2 ^J -th position of the sequence (i.e., at the last bit of the length N sequence). The differential correlation detection may use the fact that an M-sequence multiplied with a cyclically shifted version of itself results in the M-sequence with a specific cyclic shift. For example, using a primitive polynomial of x ⁷ + x + 1 to generate a length 127 M-sequence, a bitwise XOR of the generated M-sequence, for example, M- sequence 1300, and the same M-sequence cyclically right shifted by 1, for example, M- sequence 1302, may be performed. The resultant sequence, for example, sequence 1304, may be the same M-sequence cyclically right shifted by 8.

Using this property, a differential correlation detection of the received M-sequence may be performed. For example:

r _k = h _k x _k + n _k may be the received signal for subcarrier k, and hk may be the channel coefficient of subcarrier k. x _k may be the k-th value of the BPSK modulated M-sequence, and nk may be the noise for subcarrier k. Since the channel may be generally smooth and continuous, it may be assumed that h _k ≈ h _k+1 .

The receiver may perform a differential multiplication of the received signals rk and rk+1. The resultant signal, zk, may be a multiplication of two cyclically shifted M- sequences and some additive noise. An example is shown in Fig.13 and the derivation is shown below.

Because the result of the multiplication of two cyclically shifted M-sequences may be another M-sequence, the receiver may perform a fast Hadamard transform to perform a maximum likelihood (ML) detection. This detection algorithm may not require multiplication, and may be calculated using, for example, addition and subtraction operations. A Hadamard transform (which may also be referred to as the Walsh–

Hadamard transform, Hadamard–Rademacher-Walsh transform, Walsh transform, or Walsh–Fourier transform) may be an example of a generalized class of a Fourier transform. A Fourier transform may decompose a function of time (e.g., a signal) into the frequencies that make up the signal. The Hadamard transform Hm may be a

2 ^m × 2 ^m matrix that transforms 2 ^m real numbers x _n into 2 ^m real numbers X _k . The Hadamard transform may be defined in two ways: recursively, or by using the binary (base-2) representation of the indices n and k. A Hadamard transform may perform an orthogonal, symmetric, involutive, linear operation on 2 ^m real numbers (or complex numbers, although the Hadamard matrices themselves are real).

Fig.14 illustrates an example operation flow/algorithmic structure of a UE according to some embodiments. Operation flow/algorithmic structure 1400 may include, at 1402, receiving an SS block that includes an SSS sequence that indicates a cellular network identity. Operation flow/algorithmic structure 1400 may further include, at 1404, detecting the SSS sequence. In an embodiment, the SSS sequence may be based on a modulated symbol-wise multiplication of BPSK-modulated bits of cyclic-shifted versions of two M-sequences. In an embodiment, operation flow/algorithmic structure 1400 may include determining the cyclic-shifted versions of the two M-sequences. In an embodiment, a cyclic-shift parameter may be identified from a cyclic shift of an M- sequence used to generate the SSS sequence.

Operation flow/algorithmic structure 1400 may further include, at 1406, identifying a plurality of cyclic shift parameters, where the plurality of cyclic-shift parameters is based on M-sequences used to generate the SSS sequence. In an embodiment, identifying the plurality of cyclic-shift parameters may include performing one or more Hadamard transform functions on the SSS sequence, where a result of a Hadamard transform function is a cyclic shift parameter. Operation flow/algorithmic structure 1400 may further include, at 1408, determining, based on an application of the cyclic-shift parameters to cyclic-shifted versions of the M-sequences, the cellular network identity. The cellular network identity may be sent to a memory.

Fig.15 illustrates yet another example operation flow/algorithmic structure of a base station according to some embodiments. Operation flow/algorithmic structure 1500 may include, at 1502, mapping an M-sequence within an SS bandwidth. Operation flow/algorithmic structure 1500 may further include, at 1502, generating the SS.

Operation flow/algorithmic structure 1500 may further include, at 1506, transmitting the SS.

Fig.16 illustrates another example operation flow/algorithmic structure of a UE according to some embodiments. Operation flow/algorithmic structure 1600 may include, at 1602, receiving an SS. Operation flow/algorithmic structure 1600 may further include, at 1602, determining one or more maximum length sequences (M-sequences) based on the SS. Fig.17 illustrates an example architecture of a system 1700 of a network according to some embodiments. The system 1700 is shown to include a user equipment (UE) 1701 and a UE 1702. UE 1701 or UE 1702 may, for example, perform operation

flow/algorithmic processes 1400. The UEs 1701 and 1702 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but may also comprise any mobile or non-mobile computing device, such as Personal Data Assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets, or any computing device including a wireless communications interface.

In some embodiments, any of the UEs 1701 and 1702 can comprise an Internet of Things (IoT) UE, which can comprise a network access layer designed for low-power IoT applications utilizing short-lived UE connections. An IoT UE can utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), Proximity-Based Service (ProSe) or device-to-device (D2D) communication, sensor networks, or IoT networks. The M2M or MTC exchange of data may be a machine- initiated exchange of data. An IoT network describes interconnecting IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections. The IoT UEs may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the connections of the IoT network.

The UEs 1701 and 1702 may be configured to connect, e.g., communicatively couple, with a radio access network (RAN)— in this embodiment, an Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E- UTRAN) 1710. The UEs 1701 and 1702 utilize connections 1703 and 1704, respectively, each of which comprises a physical communications interface or layer (discussed in further detail below); in this example, the connections 1703 and 1704 are illustrated as an air interface to enable communicative coupling, and can be consistent with cellular communications protocols, such as a Global System for Mobile Communications (GSM) protocol, a code-division multiple access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular (POC) protocol, a Universal Mobile

Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation (5G) protocol, a New Radio (NR) protocol, and the like.

In this embodiment, the UEs 1701 and 1702 may further directly exchange communication data via a ProSe interface 1705. The ProSe interface 1705 may alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a Physical Sidelink Control Channel (PSCCH), a Physical Sidelink Shared Channel (PSSCH), a Physical Sidelink Discovery Channel (PSDCH), and a Physical Sidelink Broadcast Channel (PSBCH).

The UE 1702 is shown to be configured to access an access point (AP) 1706 via connection 1707. The connection 1707 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein the AP 1706 would comprise a wireless fidelity (WiFi®) router. In this example, the AP 1706 is shown to be connected to the Internet without connecting to the core network of the wireless system (described in further detail below).

The E-UTRAN 1710 can include one or more access nodes that enable the connections 1703 and 1704. These access nodes (ANs) can be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNB), RAN nodes, and so forth, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell). These ANs may, for example, perform operation flow/algorithmic process 1000, 1100, or 1200. The E- UTRAN 1710 may include one or more RAN nodes for providing macrocells, e.g., macro RAN node 1711, and one or more RAN nodes for providing femtocells or picocells (e.g., cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells), e.g., low power (LP) RAN node 1712.

Any of the RAN nodes 1711 and 1712 can terminate the air interface protocol and can be the first point of contact for the UEs 1701 and 1702. In some embodiments, any of the RAN nodes 1711 and 1712 can fulfill various logical functions for the E-UTRAN 1710 including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

In accordance with some embodiments, the UEs 1701 and 1702 can be configured to communicate using Orthogonal Frequency-Division Multiplexing (OFDM)

communication signals with each other or with any of the RAN nodes 1711 and 1712 over a multicarrier communication channel in accordance various communication techniques, such as, but not limited to, an Orthogonal Frequency-Division Multiple Access (OFDMA) communication technique (e.g., for downlink communications) or a Single Carrier Frequency Division Multiple Access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), although the scope of the embodiments is not limited in this respect. The OFDM signals can comprise a plurality of orthogonal subcarriers.

In some embodiments, a downlink resource grid can be used for downlink transmissions from any of the RAN nodes 1711 and 1712 to the UEs 1701 and 1702, while uplink transmissions can utilize similar techniques. The grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. Such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one slot in a radio frame. The smallest time-frequency unit in a resource grid is denoted as a resource element. Each resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block comprises a collection of resource elements; in the frequency domain, this may represent the smallest quantity of resources that currently can be allocated. There are several different physical downlink channels that are conveyed using such resource blocks.

The physical downlink shared channel (PDSCH) may carry user data and higher- layer signaling to the UEs 1701 and 1702. The physical downlink control channel (PDCCH) may carry information about the transport format and resource allocations related to the PDSCH channel, among other things. It may also inform the UEs 1701 and 1702 about the transport format, resource allocation, and H-ARQ (Hybrid Automatic Repeat Request) information related to the uplink shared channel. Typically, downlink scheduling (assigning control and shared channel resource blocks to the UE 102 within a cell) may be performed at any of the RAN nodes 1711 and 1712 based on channel quality information fed back from any of the UEs 1701 and 1702. The downlink resource assignment information may be sent on the PDCCH used for (e.g., assigned to) each of the UEs 1701 and 1702.

The PDCCH may use control channel elements (CCEs) to convey the control information. Before being mapped to resource elements, the PDCCH complex-valued symbols may first be organized into quadruplets, which may then be permuted using a sub-block interleaver for rate matching. Each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements known as resource element groups (REGs). Four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to each REG. The PDCCH can be transmitted using one or more CCEs, depending on the size of the downlink control information (DCI) and the channel condition. There can be four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, L=1, 2, 4, or 8).

Some embodiments may use concepts for resource allocation for control channel information that are an extension of the above-described concepts. For example, some embodiments may utilize an enhanced physical downlink control channel (EPDCCH) that uses PDSCH resources for control information transmission. The EPDCCH may be transmitted using one or more enhanced the control channel elements (ECCEs). Similar to above, each ECCE may correspond to nine sets of four physical resource elements known as an enhanced resource element groups (EREGs). An ECCE may have other numbers of EREGs in some situations.

The E-UTRAN 1710 is shown to be communicatively coupled to a core network — in this embodiment, an Evolved Packet Core (EPC) network 1720 via an S1 interface 1713. In this embodiment the S1 interface 1713 is split into two parts: the S1-U interface 1714, which carries traffic data between the RAN nodes 1711 and 1712 and the serving gateway (S-GW) 1722, and the S1-mobility management entity (MME) interface 1715, which is a signaling interface between the RAN nodes 1711 and 1712 and MMEs 1721.

In this embodiment, the EPC network 1720 comprises the MMEs 1721, the S-GW 1722, the Packet Data Network (PDN) Gateway (P-GW) 1723, and a home subscriber server (HSS) 1724. The MMEs 1721 may be similar in function to the control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN). The MMEs 1721 may manage mobility aspects in access such as gateway selection and tracking area list management. The HSS 1724 may comprise a database for network users, including subscription-related information to support the network entities’ handling of communication sessions. The EPC network 1720 may comprise one or several HSSs 1724, depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc. For example, the HSS 1724 can provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependencies, etc.

The S-GW 1722 may terminate the S1 interface 1713 towards the E-UTRAN 1710, and routes data packets between the E-UTRAN 1710 and the EPC network 1720. In addition, the S-GW 1722 may be a local mobility anchor point for inter-RAN node handovers and also may provide an anchor for inter-3GPP mobility. Other responsibilities may include lawful intercept, charging, and some policy enforcement.

The P-GW 1723 may terminate an SGi interface toward a PDN. The P-GW 1723 may route data packets between the EPC network 1723 and external networks such as a network including the application server 1730 (alternatively referred to as application function (AF)) via an Internet Protocol (IP) interface 1725. Generally, the application server 1730 may be an element offering applications that use IP bearer resources with the core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). In this embodiment, the P-GW 1723 is shown to be communicatively coupled to an application server 1730 via an IP communications interface 1725. The application server 1730 can also be configured to support one or more communication services (e.g., Voice- over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 1701 and 1702 via the EPC network 1720.

The P-GW 1723 may further be a node for policy enforcement and charging data collection. Policy and Charging Enforcement Function (PCRF) 1726 is the policy and charging control element of the EPC network 1720. In a non-roaming scenario, there may be a single PCRF in the Home Public Land Mobile Network (HPLMN) associated with a UE’s Internet Protocol Connectivity Access Network (IP-CAN) session. In a roaming scenario with local breakout of traffic, there may be two PCRFs associated with a UE’s IP-CAN session: a Home PCRF (H-PCRF) within a HPLMN and a Visited PCRF (V- PCRF) within a Visited Public Land Mobile Network (VPLMN). The PCRF 1726 may be communicatively coupled to the application server 1730 via the P-GW 1723. The application server 1730 may signal the PCRF 1726 to indicate a new service flow and select the appropriate Quality of Service (QoS) and charging parameters. The PCRF 1726 may provision this rule into a Policy and Charging Enforcement Function (PCEF) (not shown) with the appropriate traffic flow template (TFT) and QoS class of identifier (QCI), which commences the QoS and charging as specified by the application server 1730.

Fig.18 illustrates example components of a device 1800 according to some embodiments. In some embodiments, the device 1800 may include application circuitry 1802, baseband circuitry 1804, Radio Frequency (RF) circuitry 1806, front-end module (FEM) circuitry 1808, one or more antennas 1810, and power management circuitry (PMC) 1812 coupled together at least as shown. The components of the illustrated device 1800 may be included in a UE or a RAN node. In some embodiments, the device 1800 may include less elements (e.g., a RAN node may not utilize application circuitry 1802, and instead include a processor/controller to process IP data received from an EPC). In some embodiments, the device 1800 may include additional elements such as, for example, memory/storage, display, camera, sensor, or input/output (I/O) interface. In other embodiments, the components described below may be included in more than one device (e.g., said circuitries may be separately included in more than one device for Cloud-RAN (C-RAN) implementations).

The application circuitry 1802 may include one or more application processors. For example, the application circuitry 1802 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processors may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the device 1800. In some embodiments, processors of application circuitry 1802 may process IP data packets received from an EPC.

The baseband circuitry 1804 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The baseband circuitry 1804 may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry 1806 and to generate baseband signals for a transmit signal path of the RF circuitry 1806. Baseband processors may, for example, perform operation flow/algorithmic process 1000, 1100, 1200, or 1400. Baseband processing circuity 1804 may interface with the application circuitry 1802 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 1806. For example, in some embodiments, the baseband circuitry 1804 may include a third generation (3G) baseband processor 1804A, a fourth generation (4G) baseband processor 1804B, a fifth generation (5G) baseband processor 1804C, or other baseband processor(s) 1804D for other existing generations, generations in development or to be developed in the future (e.g., second generation (2G), si18h generation (6G), etc.). The baseband circuitry 1804 (e.g., one or more of baseband processors 1804A-D) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry 1806. In other embodiments, some or all of the functionality of baseband processors 1804A-D may be included in modules stored in the memory 1804G and executed via a Central Processing Unit (CPU) 1804E. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, etc. In some embodiments,

modulation/demodulation circuitry of the baseband circuitry 1804 may include Fast- Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality. In some embodiments, encoding/decoding circuitry of the baseband circuitry 1804 may include convolution, tail-biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality. Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

In some embodiments, the baseband circuitry 1804 may include one or more audio digital signal processor(s) (DSP) 1804F. The audio DSP(s) 1804F may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 1804 and the application circuitry 1802 may be implemented together such as, for example, on a system on a chip (SOC).

In some embodiments, the baseband circuitry 1804 may provide for

communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 1804 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 1804 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

RF circuitry 1806 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various

embodiments, the RF circuitry 1806 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network. RF circuitry 1806 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 1808 and provide baseband signals to the baseband circuitry 1804. RF circuitry 1806 may also include a transmit signal path which may include circuitry to up- convert baseband signals provided by the baseband circuitry 1804 and provide RF output signals to the FEM circuitry 1808 for transmission. In some embodiments, the receive signal path of the RF circuitry 1806 may include mixer circuitry 1806a, amplifier circuitry 1806b and filter circuitry 1806c. In some embodiments, the transmit signal path of the RF circuitry 1806 may include filter circuitry 1806c and mixer circuitry 1806a. RF circuitry 1806 may also include synthesizer circuitry 1806d for synthesizing a frequency for use by the mixer circuitry 1806a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 1806a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 1808 based on the synthesized frequency provided by synthesizer circuitry 1806d. The amplifier circuitry 1806b may be configured to amplify the down- converted signals and the filter circuitry 1806c may be a low-pass filter (LPF) or band- pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 1804 for further processing. In some embodiments, the output baseband signals may be zero-frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry 1806a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuitry 1806a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 1806d to generate RF output signals for the FEM circuitry 1808. The baseband signals may be provided by the baseband circuitry 1804 and may be filtered by filter circuitry 1806c.

In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and upconversion, respectively. In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a may be arranged for direct downconversion and direct upconversion, respectively. In some embodiments, the mixer circuitry 1806a of the receive signal path and the mixer circuitry 1806a of the transmit signal path may be configured for super-heterodyne operation.

In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, the RF circuitry 1806 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 1804 may include a digital baseband interface to communicate with the RF circuitry 1806.

In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.

In some embodiments, the synthesizer circuitry 1806d may be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 1806d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.

The synthesizer circuitry 1806d may be configured to synthesize an output frequency for use by the mixer circuitry 1806a of the RF circuitry 1806 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 1806d may be a fractional N/N+1 synthesizer.

In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 1804 or the applications processor 1802 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 1802.

Synthesizer circuitry 1806d of the RF circuitry 1806 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some embodiments, the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop. In these embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle. In some embodiments, synthesizer circuitry 1806d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be a LO frequency (fLO). In some embodiments, the RF circuitry 1806 may include an IQ/polar converter.

FEM circuitry 1808 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 1810, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 1806 for further processing. FEM circuitry 1808 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 1806 for transmission by one or more of the one or more antennas 1810. In various embodiments, the amplification through the transmit or receive signal paths may be done solely in the RF circuitry 1806, solely in the FEM 1808, or in both the RF circuitry 1806 and the FEM 1808.

In some embodiments, the FEM circuitry 1808 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include an LNA to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 1806). The transmit signal path of the FEM circuitry 1808 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 1806), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 1810).

In some embodiments, the PMC 1812 may manage power provided to the baseband circuitry 1804. In particular, the PMC 1812 may control power-source selection, voltage scaling, battery charging, or DC-to-DC conversion. The PMC 1812 may often be included when the device 1800 is capable of being powered by a battery, for example, when the device is included in a UE. The PMC 1812 may increase the power conversion efficiency while providing desirable implementation size and heat dissipation

characteristics. While Fig.18 shows the PMC 1812 coupled only with the baseband circuitry 1804. However, in other embodiments, the PMC 1812 may be additionally or alternatively coupled with, and perform similar power management operations for, other components such as, but not limited to, application circuitry 1802, RF circuitry 1806, or FEM 1808.

In some embodiments, the PMC 1812 may control, or otherwise be part of, various power saving mechanisms of the device 1800. For example, if the device 1800 is in an RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the device 1800 may power down for brief intervals of time and thus save power.

If there is no data traffic activity for an extended period of time, then the device 1800 may transition off to an RRC_Idle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc. The device 1800 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again. The device 1800 may not receive data in this state, in order to receive data, it must transition back to

RRC_Connected state.

An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.

Processors of the application circuitry 1802 and processors of the baseband circuitry 1804 may be used to execute elements of one or more instances of a protocol stack. For example, processors of the baseband circuitry 1804, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of the application circuitry 1804 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). As referred to herein, Layer 3 may comprise a radio resource control (RRC) layer, described in further detail below. As referred to herein, Layer 2 may comprise a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer, described in further detail below. As referred to herein, Layer 1 may comprise a physical (PHY) layer of a UE/RAN node, described in further detail below. Fig.19 illustrates example interfaces of baseband circuitry according to some embodiments. As discussed above, the baseband circuitry 1804 of Fig.18 may comprise processors 1804A-1804E and a memory 1804G utilized by said processors. Each of the processors 1804A-1804E may include a memory interface, 1904A-1904E, respectively, to send/receive data such as, for example, as may be described in connection with operation flow/algorithmic process 1000, 1100, 1200, or 1400, to/from the memory 1804G.

Baseband circuitry 1804 may include a memory interface to receive a primitive polynomial from memory 1804G.

The baseband circuitry 1804 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 1912 (e.g., an interface to send/receive data to/from memory external to the baseband circuitry 1804), an application circuitry interface 1914 (e.g., an interface to send/receive data to/from the application circuitry 1802 of Fig.18), an RF circuitry interface 1916 (e.g., an interface to send/receive data to/from RF circuitry 1806 of Fig.18), a wireless hardware connectivity interface 1918 (e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components), and a power management interface 1920 (e.g., an interface to send/receive power or control signals to/from the PMC 1812.

Fig.20 is a block diagram illustrating example components, according to some example embodiments, able to read instructions from a machine-readable or computer- readable medium (e.g., a non-transitory machine-readable storage medium) and perform any one or more of the methodologies discussed herein. Specifically, Fig.20 shows a diagrammatic representation of hardware resources 2000 including one or more processors (or processor cores) 2010, one or more memory/storage devices 2020, and one or more communication resources 2030, each of which may be communicatively coupled via a bus 2040. For embodiments where node virtualization (e.g., NFV) is utilized, a hypervisor 2002 may be executed to provide an execution environment for one or more network slices/sub-slices to utilize the hardware resources 2000.

The processors 2010 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, a processor 2012 and a processor 2014. Processors 2010 may, for example, perform operation flow/algorithmic process 1000, 1100, 1200, or 1400.

The memory/storage devices 2020 may include main memory, disk storage, or any suitable combination thereof. The memory/storage devices 2020 may include, but are not limited to any type of volatile or non-volatile memory such as dynamic random access memory (DRAM), static random-access memory (SRAM), erasable programmable read- only memory (EPROM), electrically erasable programmable read-only memory

(EEPROM), Flash memory, solid-state storage, etc.

The communication resources 2030 may include interconnection or network interface components or other suitable devices to communicate with one or more peripheral devices 2004 or one or more databases 2006 via a network 2008. For example, the communication resources 2030 may include wired communication components (e.g., for coupling via a Universal Serial Bus (USB)), cellular communication components, NFC components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi®

components, and other communication components.

Instructions 2050 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least any of the processors 2010 to perform any one or more of the methodologies discussed herein. The instructions 2050 may reside, completely or partially, within at least one of the processors 2010 (e.g., within the processor’s cache memory), the memory/storage devices 2020, or any suitable

combination thereof. Furthermore, any portion of the instructions 2050 may be transferred to the hardware resources 2000 from any combination of the peripheral devices 2004 or the databases 2006. Accordingly, the memory of processors 2010, the memory/storage devices 2020, the peripheral devices 2004, and the databases 2006 are examples of computer-readable and machine-readable media.

In some embodiments, the electronic devices, components, or systems, or portions or implementations thereof of Figure 17, 18, 19, or 20 may be configured to perform one or more processes, techniques, or methods as described herein, or portions thereof.

The description herein of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, a variety of alternate or equivalent embodiments or implementations calculated to achieve the same purposes may be made in light of the above detailed description, without departing from the scope of the present disclosure, as those skilled in the relevant art will recognize.

Some non-limiting examples are provided below. Examples

Example 1 may include one or more computer-readable media having instructions that, when executed by one or more processors, cause a base station to: multiply two cyclically shifted, binary phase shift keying (BPSK)-modulated M-sequences, to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a length; and map the sequence to a number of central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of central subcarriers corresponds to the length of the sequence.

Example 2 may include the one or more computer-readable media of Example 1 or some other example herein, wherein the central subcarriers are central continuous subcarriers.

Example 3 may include the one or more computer-readable media of Example 1 or 2 or some other example herein, wherein, to generate the sequence for the SSS, the instructions, when executed, further cause the base station to multiply the two cyclically shifted, BPSK modulated M-sequences, according to d(n) = (1-2∙ c ₀ ^(m ₀ ⁾ (n))∙ ((1-2∙ c1 ^(m 1 ⁾ (n)), wherein d(n) is an SSS sequence, and wherein c ₀ ^(m 0 ⁾ (n) = s0((n+ m0)mod L) is a cyclic shift of a first M-sequence s ₀ of the two cyclically shifted, BPSK-modulated M- sequences, and c1 ^(m 1 ⁾ (n) = s1((n+ m1)mod L) is a cyclic shift of a second M-sequence s1 of the two cyclically shifted, BPSK-modulated M-sequences, wherein m ₀ is a first cyclic- shift value and m ₁ is a second cyclic shift value, wherein L is a length of the sequence, wherein n is from 0 to L minus 1, wherein the first M-sequence s ₀ (n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a first primitive polynomial, and wherein the second M-sequence s ₁ (n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a second primitive polynomial.

Example 4 may include the one or more computer-readable media of Example 3 or some other example herein, wherein L equals 127.

Example 5 may include the one or more computer-readable media of Example 3 or some other example herein, wherein the first M-sequence s0 is generated from a first primitive polynomial x ⁷ +x ⁴ +1, and wherein the second M-sequence s1 is generated from a second primitive polynomial x ⁷ +x+1. Example 6 may include the one or more computer-readable media of Example 4 or 5, wherein an initial state of the M-sequences is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

Example 7 may include the one or more computer-readable media of Example 4 or 5 or some other example herein, wherein the first M-sequence s0(n) generated by the first primitive polynomial uses a subset of available sets of cyclic shifts, and wherein the second M-sequence s1(n) generated by the second primitive polynomial uses all of the available sets of cyclic shifts.

Example 8 may include the one or more computer-readable media of Example 7 or some other example herein, wherein a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity.

Example 9 may include the one or more computer-readable media of Example 1, 2, 4, 5, or 8 or some other example herein, wherein the SSS is mapped to a same antenna port as a primary synchronization signal.

Example 10 may include one or more computer-readable media having instructions that, when executed by one or more processors, cause a base station to: determine, based on a primitive polynomial, a maximum length sequence (M-sequence) that has a length; perform a cyclic shift of the M-sequence to generate a cyclic-shifted M-sequence;

modulate, using binary phase shift keying (BPSK) modulation, the cyclic-shifted M- sequence to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and map the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein a number of the central subcarriers corresponds to the length of the M-sequence.

Example 11 may include the one or more computer-readable media of Example 10 or some other example herein, wherein, to determine the M-sequence, the instructions, when executed, further cause the base station to select the M-sequence from a set of M- sequences generated from a set of primitive polynomials.

Example 12 may include the one or more computer-readable media of Example 10 or some other example herein, wherein, to determine the M-sequence, the instructions, when executed, further cause the base station to generate, based on the primitive polynomial, the M-sequence that has the length.

Example 13 may include the one or more computer-readable media of Example 12 or some other example herein, wherein the instructions, when executed, further cause the base station to multiply each of the central subcarriers by a repeated complex scrambling sequence.

Example 14 may include an apparatus for a base station, comprising: processing circuitry to: generate, based on two distinct primitive polynomials, two maximum length sequences (M-sequences), wherein each M-sequence has a length; perform a cyclic shift of the two M-sequences to generate two cyclic-shifted M-sequences; modulate, using binary phase shift keying (BPSK) modulation, the two cyclic-shifted M-sequences to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and map the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the lengths of the M-sequences; and interface circuitry, coupled with the processing circuitry, to receive the two distinct primitive polynomials from a memory.

Example 15 may include the apparatus of Example 14 or some other example herein, wherein the processing circuitry is further to: multiply a first M-sequence of the two M-sequences by a complex value, to provide a complex value M-sequence; and multiply a second M-sequence of the two M-sequences by a real value, to provide a real value M-sequence.

Example 16 may include the apparatus of Example 15 or some other example herein, wherein, to map the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth, the processing circuitry is further to: map BPSK- modulated bits of the complex value M-sequence to an in-phase constellation of the central subcarriers of the SS bandwidth; and map the BPSK-modulated bits of the real value M-sequence to a quadrature constellation of central subcarriers of the SS bandwidth.

Example 17 may include the apparatus of Example 14 or some other example herein, wherein the processing circuitry is further to perform a bitwise exclusive-or (XOR) operation on the two cyclic-shifted M-sequences.

Example 18 may include the apparatus of Example 14 or some other example herein, wherein the processing circuitry is further to perform a modulated symbol-wise multiplication of the BPSK-modulated bits of the two cyclic-shifted M-sequences.

Example 19 may include the apparatus of Example 14, 15, 16, 17, or 18 or some other example herein, wherein a cyclic shift is based on a cell identity.

Example 20 may include the apparatus of Example 14, 15, 16, 17, or 18 or some other example herein, wherein the length is selected from one of 127 or 255. Example 21 may include an apparatus for a user equipment (UE), comprising: processing circuitry to: receive a synchronization signal (SS) block that includes a secondary synchronization signal (SSS) sequence; detect the SSS sequence; identify a plurality of cyclic-shift parameters, wherein the plurality of cyclic-shift parameters is based on maximum length sequences (M-sequences) used to generate the SSS sequence; determine, based on application of the cyclic-shift parameters to cyclic-shifted versions of the M-sequences, a cellular network identity; and interface circuitry, coupled with the processing circuitry, to send the cellular network identity to a memory.

Example 22 may include the apparatus of Example 21 or some other example herein, wherein the SSS sequence is based on a modulated symbol-wise multiplication of BPSK-modulated bits of cyclic-shifted versions of two M-sequences.

Example 23 may include the apparatus of Example 22 or some other example herein, wherein the processing circuitry is further to determine the cyclic-shifted versions of the two M-sequences.

Example 24 may include the apparatus of Example 21, 22, or 23 or some other example herein, wherein a cyclic-shift parameter is identified from a cyclic shift of an M- sequence used to generate the SSS sequence.

Example 25 may include the apparatus of Example 21, 22, or 23 or some other example herein, wherein, to identify the plurality of cyclic shift parameters, the processing circuitry is further to perform one or more Hadamard transform functions on the SSS sequence, wherein a result of a Hadamard transform function is the cyclic shift parameter.

Example 26 may include a method of signal generation, comprising: multiplying two cyclically shifted, binary phase shift keying (BPSK)-modulated M-sequences, to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a length; and mapping the sequence to a number of central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of central subcarriers corresponds to the length of the sequence.

Example 27 may include the method of Example 26 or some other example herein, wherein the central subcarriers are central continuous subcarriers.

Example 28 may include the method of Example 26 or 27 or some other example herein, wherein, generating the sequence for the SSS includes multiplying the two cyclically shifted, BPSK modulated M-sequences, according to d(n) = (1-2∙ c ₀ ^(m 0 ⁾ (n))∙ ((1-2∙ c1 ^(m 1 ⁾ (n)), wherein d(n) is an SSS sequence, and wherein c ₀ ^(m 0 ⁾ (n) = s0((n+ m0)mod L) is a cyclic shift of a first M-sequence s ₀ of the two cyclically shifted, BPSK-modulated M-sequences, and c1 ^(m 1 ⁾ (n) = s1((n+ m1)mod L) is a cyclic shift of a second M-sequence s1 of the two cyclically shifted, BPSK-modulated M-sequences, wherein m ₀ is a first cyclic- shift value and m ₁ is a second cyclic shift value, wherein L is a length of the sequence, wherein n is from 0 to L minus 1, wherein the first M-sequence s ₀ (n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a first primitive polynomial, and wherein the second M-sequence s ₁ (n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a second primitive polynomial.

Example 29 may include the method of Example 28 or some other example herein, wherein L equals 127.

Example 30 may include the method of Example 29 or some other example herein, wherein the first M-sequence s0 is generated from a first primitive polynomial x ⁷ +x ⁴ +1, and wherein the second M-sequence s ₁ is generated from a second primitive polynomial x ⁷ +x+1.

Example 31 may include the method of Example 29 or 30, wherein an initial state of the M-sequences is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

Example 32 may include the method of Example 29 or 30 or some other example herein, wherein the first M-sequence s ₀ (n) generated by the first primitive polynomial uses a subset of available sets of cyclic shifts, and wherein the second M-sequence s1(n) generated by the second primitive polynomial uses all of the available sets of cyclic shifts.

Example 33 may include the method of Example 32 or some other example herein, wherein a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity.

Example 34 may include the method of Example 26, 27, 29, 30, or 33 or some other example herein, wherein the SSS is mapped to a same antenna port as a primary synchronization signal.

Example 35 may include a method of signal generation, comprising: determining, based on a primitive polynomial, a maximum length sequence (M-sequence) that has a length; performing a cyclic shift of the M-sequence to generate a cyclic-shifted M- sequence; modulating, using binary phase shift keying (BPSK) modulation, the cyclic- shifted M-sequence to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein a number of the central subcarriers corresponds to the length of the M-sequence. Example 36 may include the method of Example 35 or some other example herein, wherein, determining the M-sequence includes selecting the M-sequence from a set of M- sequences generated from a set of primitive polynomials.

Example 37 may include the method of Example 35 or some other example herein, wherein, determining the M-sequence includes generating, based on the primitive polynomial, the M-sequence that has the length.

Example 38 may include the method of Example 37 or some other example herein, further comprising instructions that, when executed, cause the base station to multiply each of the central subcarriers by a repeated complex scrambling sequence.

Example 39 may include an apparatus for a base station comprising: processing circuitry to: multiply two cyclically shifted, binary phase shift keying (BPSK)-modulated M-sequences, to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a length; and map the sequence to a number of central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of central subcarriers corresponds to the length of the sequence; and interface circuitry, coupled with the processing circuitry, to send the sequence for the SSS to a memory.

Example 40 may include the apparatus of Example 39 or some other example herein, wherein the central subcarriers are central continuous subcarriers.

Example 41 may include the apparatus of Example 39 or 40 or some other example herein, wherein, to generate the sequence for the SSS, the processing circuitry is further to multiply the two cyclically shifted, BPSK modulated M-sequences, according to d(n) = (1- 2∙ c ₀ ^(m ₀ ⁾ (n))∙ ((1-2∙ c ₁ ^(m ₁ ⁾ (n)), wherein d(n) is an SSS sequence, and wherein c ₀ ^(m ₀ ⁾ (n) = s0((n+ m0)mod L) is a cyclic shift of a first M-sequence s0 of the two cyclically shifted, BPSK-modulated M-sequences, and c ₁ ^(m ₁ ⁾ (n) = s ₁ ((n+ m ₁ )mod L) is a cyclic shift of a second M-sequence s1 of the two cyclically shifted, BPSK-modulated M-sequences, wherein m ₀ is a first cyclic-shift value and m ₁ is a second cyclic shift value, wherein L is a length of the sequence, wherein n is from 0 to L minus 1, wherein the first M-sequence s ₀ (n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a first primitive polynomial, and wherein the second M-sequence s1(n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a second primitive polynomial.

Example 42 may include the apparatus of Example 41 or some other example herein, wherein L equals 127. Example 43 may include the apparatus of Example 41 or some other example herein, wherein the first M-sequence s ₀ is generated from a first primitive polynomial x ⁷ +x ⁴ +1, and wherein the second M-sequence s1 is generated from a second primitive polynomial x ⁷ +x+1.

Example 44 may include the apparatus of Example 42 or 43, wherein an initial state of the M-sequences is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0.

Example 45 may include the apparatus of Example 42 or 43 or some other example herein, wherein the first M-sequence s ₀ (n) generated by the first primitive polynomial uses a subset of available sets of cyclic shifts, and wherein the second M-sequence s1(n) generated by the second primitive polynomial uses all of the available sets of cyclic shifts.

Example 46 may include the apparatus of Example 45 or some other example herein, wherein a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity.

Example 47 may include the apparatus of Example 39, 40, 43, 44, or 46 or some other example herein, wherein the SSS is mapped to a same antenna port as a primary synchronization signal.

Example 48 may include an apparatus for a base station comprising: processing circuitry to: determine, based on a primitive polynomial, a maximum length sequence (M- sequence) that has a length; perform a cyclic shift of the M-sequence to generate a cyclic- shifted M-sequence; modulate, using binary phase shift keying (BPSK) modulation, the cyclic-shifted M-sequence to generate BPSK-modulated bits of a secondary

synchronization signal (SSS) sequence; and map the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein a number of the central subcarriers corresponds to the length of the M-sequence; and interface circuitry, coupled with the processing circuitry, to send the SSS sequence to a memory.

Example 49 may include the apparatus of Example 48 or some other example herein, wherein, to determine the M-sequence, the processing circuitry is further to select the M-sequence from a set of M-sequences generated from a set of primitive polynomials.

Example 50 may include the apparatus of Example 48 or some other example herein, wherein, to determine the M-sequence, the processing circuitry is further to generate, based on the primitive polynomial, the M-sequence that has the length. Example 51 may include the apparatus of Example 50 or some other example herein, wherein the processing circuitry is further to multiply each of the central subcarriers by a repeated complex scrambling sequence.

Example 52 may include an apparatus for a base station, comprising: a means for multiplying two cyclically shifted, binary phase shift keying (BPSK)-modulated M- sequences, to generate a sequence for a secondary synchronization signal (SSS), wherein the sequence has a length; and a means for mapping the sequence to a number of central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of central subcarriers corresponds to the length of the sequence.

Example 53 may include the apparatus of Example 52 or some other example herein, wherein the central subcarriers are central continuous subcarriers.

Example 54 may include the apparatus of Example 52 or 53 or some other example herein, wherein, the means for generating the sequence for the SSS, includes a means for multiplying the two cyclically shifted, BPSK modulated M-sequences, according to d(n) = (1-2∙ c ₀ ^(m 0 ⁾ (n))∙ ((1-2∙ c1 ^(m 1 ⁾ (n)), wherein d(n) is an SSS sequence, and wherein c ₀ ^(m 0 ⁾ (n) = s0((n+ m0)mod L) is a cyclic shift of a first M-sequence s0 of the two cyclically shifted, BPSK-modulated M-sequences, and c ₁ ^(m ₁ ⁾ (n) = s ₁ ((n+ m ₁ )mod L) is a cyclic shift of a second M-sequence s1 of the two cyclically shifted, BPSK-modulated M-sequences, wherein m ₀ is a first cyclic-shift value and m ₁ is a second cyclic shift value, wherein L is a length of the sequence, wherein n is from 0 to L minus 1, wherein the first M-sequence s ₀ (n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a first primitive polynomial, and wherein the second M-sequence s1(n) of the two cyclically shifted, BPSK-modulated M-sequences is generated from a second primitive polynomial.

Example 55 may include the apparatus of Example 54 or some other example herein, wherein L equals 127.

Example 56 may include the apparatus of Example 54 or some other example herein, wherein the first M-sequence s0 is generated from a first primitive polynomial x ⁷ +x ⁴ +1, and wherein the second M-sequence s ₁ is generated from a second primitive polynomial x ⁷ +x+1.

Example 57 may include the apparatus of Example 55 or 56 or some other example herein, wherein an initial state of the M-sequences is s(0) = 1, s(1) = s(2) = s(3) = s(4) = s(5) = s(6) = 0. Example 58 may include the apparatus of Example 55 or 56 or some other example herein, wherein the first M-sequence s ₀ (n) generated by the first primitive polynomial uses a subset of available sets of cyclic shifts, and wherein the second M-sequence s1(n) generated by the second primitive polynomial uses all of the available sets of cyclic shifts.

Example 59 may include the apparatus of Example 58 or some other example herein, wherein a combination of a first cyclic shift value and a second cyclic shift value provides a cell identity.

Example 60 may include the apparatus of Example 52, 53, 55, 56, or 59 or some other example herein, wherein the SSS is mapped to a same antenna port as a primary synchronization signal.

Example 61 may include an apparatus for a base station, comprising: a means for determining, based on a primitive polynomial, a maximum length sequence (M-sequence) that has a length; a means for performing a cyclic shift of the M-sequence to generate a cyclic-shifted M-sequence; a means for modulating, using binary phase shift keying (BPSK) modulation, the cyclic-shifted M-sequence to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and a means for mapping the BPSK- modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein a number of the central subcarriers corresponds to the length of the M-sequence.

Example 62 may include the apparatus of Example 61 or some other example herein, wherein, the means for determining the M-sequence includes selecting the M- sequence from a set of M-sequences generated from a set of primitive polynomials.

Example 63 may include the apparatus of Example 61 or some other example herein, wherein, the means for determining the M-sequence includes generating, based on the primitive polynomial, the M-sequence that has the length.

Example 64 may include the apparatus of Example 63 or some other example herein, further comprising a means for multiplying each of the central subcarriers by a repeated complex scrambling sequence.

Example 65 may include one or more computer-readable media having instructions that, when executed, cause a base station to: generate, based on two distinct primitive polynomials, two maximum length sequences (M-sequences), wherein each M-sequence has a length; perform a cyclic shift of the two M-sequences to generate two cyclic-shifted M-sequences; modulate, using binary phase shift keying (BPSK) modulation, the two cyclic-shifted M-sequences to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and map the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for

transmission, wherein the number of the central subcarriers corresponds to the lengths of the M-sequences.

Example 66 may include the one or more computer-readable media of Example 65 or some other example herein, wherein the instructions, when executed, further cause the base station to: multiply a first M-sequence of the two M-sequences by a complex value, to provide a complex value M-sequence; and multiply a second M-sequence of the two M- sequences by a real value, to provide a real value M-sequence.

Example 67 may include the one or more computer-readable media of Example 66 or some other example herein, wherein, to map the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth, the instructions, when executed, further cause the base station to: map BPSK-modulated bits of the complex value M- sequence to an in-phase constellation of the central subcarriers of the SS bandwidth; and map the BPSK-modulated bits of the real value M-sequence to a quadrature constellation of central subcarriers of the SS bandwidth.

Example 68 may include the one or more computer-readable media of Example 65 or some other example herein, wherein the instructions, when executed, further cause the base station to perform a bitwise exclusive-or (XOR) operation on the two cyclic-shifted M-sequences.

Example 69 may include the one or more computer-readable media of Example 65 or some other example herein, wherein the instructions, when executed, further cause the base station to perform a modulated symbol-wise multiplication of the BPSK-modulated bits of the two cyclic-shifted M-sequences.

Example 70 may include the one or more computer-readable media of Example 65, 66, 67, 68, or 69 or some other example herein, wherein a cyclic shift is based on a cell identity.

Example 71 may include the one or more computer-readable media of Example 65, 66, 67, 68, or 69 or some other example herein, wherein the length is selected from one of 127 or 255.

Example 72 may include a method of signal generation, comprising: generating, based on two distinct primitive polynomials, two maximum length sequences (M- sequences), wherein each M-sequence has a length; performing a cyclic shift of the two M-sequences to generate two cyclic-shifted M-sequences; modulating, using binary phase shift keying (BPSK) modulation, the two cyclic-shifted M-sequences to generate BPSK- modulated bits of a secondary synchronization signal (SSS) sequence; and mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the lengths of the M-sequences.

Example 73 may include the method of Example 72 or some other example herein, further comprising: multiplying a first M-sequence of the two M-sequences by a complex value, to provide a complex value M-sequence; and multiplying a second M-sequence of the two M-sequences by a real value, to provide a real value M-sequence.

Example 74 may include the method of Example 73 or some other example herein, wherein, mapping the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth, includes: mapping BPSK-modulated bits of the complex value M- sequence to an in-phase constellation of the central subcarriers of the SS bandwidth; and mapping the BPSK-modulated bits of the real value M-sequence to a quadrature constellation of central subcarriers of the SS bandwidth.

Example 75 may include the method of Example 72 or some other example herein, further comprising performing a bitwise exclusive-or (XOR) operation on the two cyclic- shifted M-sequences.

Example 76 may include the method of Example 72 or some other example herein, further comprising performing a modulated symbol-wise multiplication of the BPSK- modulated bits of the two cyclic-shifted M-sequences.

Example 77 may include the method of Example 72, 73, 74, 75, or 76 or some other example herein, wherein a cyclic shift is based on a cell identity.

Example 78 may include the method of Example 72, 73, 74, 75, or 76 or some other example herein, wherein the length is selected from one of 127 or 255.

Example 79 may include an apparatus for a base station, comprising: a means for generating, based on two distinct primitive polynomials, two maximum length sequences (M-sequences), wherein each M-sequence has a length; a means for performing a cyclic shift of the two M-sequences to generate two cyclic-shifted M-sequences; a means for modulating, using binary phase shift keying (BPSK) modulation, the two cyclic-shifted M- sequences to generate BPSK-modulated bits of a secondary synchronization signal (SSS) sequence; and a means for mapping the BPSK-modulated bits of the SSS sequence to central subcarriers of a synchronization signal (SS) bandwidth for transmission, wherein the number of the central subcarriers corresponds to the lengths of the M-sequences. Example 80 may include the apparatus of Example 79 or some other example herein, further comprising: a means for multiplying a first M-sequence of the two M- sequences by a complex value, to provide a complex value M-sequence; and a means for multiplying a second M-sequence of the two M-sequences by a real value, to provide a real value M-sequence.

Example 81 may include the apparatus of Example 80 or some other example herein, wherein the means for mapping the BPSK-modulated bits of the SSS sequence to the central subcarriers of the SS bandwidth, includes: a means for mapping BPSK- modulated bits of the complex value M-sequence to an in-phase constellation of the central subcarriers of the SS bandwidth; and a means for mapping the BPSK-modulated bits of the real value M-sequence to a quadrature constellation of central subcarriers of the SS bandwidth.

Example 82 may include the apparatus of Example 79 or some other example herein, further comprising a means for performing a bitwise exclusive-or (XOR) operation on the two cyclic-shifted M-sequences.

Example 83 may include the apparatus of Example 79 or some other example herein, further comprising a means for performing a modulated symbol-wise

multiplication of the BPSK-modulated bits of the two cyclic-shifted M-sequences.

Example 84 may include the apparatus of Example 79, 80, 81, 82, or 83 or some other example herein, wherein a cyclic shift is based on a cell identity.

Example 85 may include the apparatus of Example 79, 80, 81, 82, or 83 or some other example herein, wherein the length is selected from one of 127 or 255.

Example 86 may include one or more computer-readable media having instructions that, when executed, cause a user equipment (UE) to: receive a synchronization signal (SS) block that includes a secondary synchronization signal (SSS) sequence; detect the SSS sequence; identify a plurality of cyclic-shift parameters, wherein the plurality of cyclic-shift parameters is based on maximum length sequences (M-sequences) used to generate the SSS sequence; and determine, based on application of the cyclic-shift parameters to cyclic-shifted versions of the M-sequences, a cellular network identity.

Example 87 may include the one or more computer-readable media of Example 86 or some other example herein, wherein the SSS sequence is based on a modulated symbol- wise multiplication of BPSK-modulated bits of cyclic-shifted versions of two M- sequences. Example 88 may include the one or more computer-readable media of Example 87 or some other example herein, wherein the instructions, when executed, further cause the UE to determine the cyclic-shifted versions of the two M-sequences.

Example 89 may include the one or more computer-readable media of Example 86, 87, or 88 or some other example herein, wherein a cyclic-shift parameter is identified from a cyclic shift of an M-sequence used to generate the SSS sequence.

Example 90 may include the one or more computer-readable media of Example 86, 87, or 88 or some other example herein, wherein, to identify the plurality of cyclic shift parameters, the instructions, when executed, further cause the UE to perform one or more Hadamard transform functions on the SSS sequence, wherein a result of a Hadamard transform function is the cyclic shift parameter.

Example 91 may include a method of signal detection, comprising: receiving a synchronization signal (SS) block that includes a secondary synchronization signal (SSS) sequence; detecting the SSS sequence; identifying a plurality of cyclic-shift parameters, wherein the plurality of cyclic-shift parameters is based on maximum length sequences (M-sequences) used to generate the SSS sequence; and determining, based on application of the cyclic-shift parameters to cyclic-shifted versions of the M-sequences, a cellular network identity.

Example 92 may include the method of Example 91 or some other example herein, wherein the SSS sequence is based on a modulated symbol-wise multiplication of BPSK- modulated bits of cyclic-shifted versions of two M-sequences.

Example 93 may include the method of Example 92 or some other example herein, further comprising determining the cyclic-shifted versions of the two M-sequences.

Example 94 may include the method of Example 91, 92, or 93 or some other example herein, wherein a cyclic-shift parameter is identified from a cyclic shift of an M- sequence used to generate the SSS sequence.

Example 95 may include the method of Example 91, 92, or 93 or some other example herein, wherein identifying the plurality of cyclic shift parameters includes performing one or more Hadamard transform functions on the SSS sequence, wherein a result of a Hadamard transform function is the cyclic shift parameter.

Example 96 may include an apparatus for a user equipment (UE), comprising: a means for receiving a synchronization signal (SS) block that includes a secondary synchronization signal (SSS) sequence; a means for detecting the SSS sequence; a means for identifying a plurality of cyclic-shift parameters, wherein the plurality of cyclic-shift parameters is based on maximum length sequences (M-sequences) used to generate the SSS sequence; and a means for determining, based on application of the cyclic-shift parameters to cyclic-shifted versions of the M-sequences, a cellular network identity.

Example 97 may include the apparatus of Example 96 or some other example herein, wherein the SSS sequence is based on a modulated symbol-wise multiplication of BPSK-modulated bits of cyclic-shifted versions of two M-sequences.

Example 98 may include the apparatus of Example 97 or some other example herein, further comprising a means for determining the cyclic-shifted versions of the two M-sequences.

Example 99 may include the apparatus of Example 96, 97, or 98 or some other example herein, wherein a cyclic-shift parameter is identified from a cyclic shift of an M- sequence used to generate the SSS sequence.

Example 100 may include the apparatus of Example 96, 97, or 98 or some other example herein, wherein the means for identifying the plurality of cyclic shift parameters includes a means for performing one or more Hadamard transform functions on the SSS sequence, wherein a result of a Hadamard transform function is the cyclic shift parameter.

Example 101 may include a signal, comprising a secondary synchronization signal based on a modulated cyclic-shifted version of an M-sequence generated from a primitive polynomial.

Example 102 may include a signal, comprising a secondary synchronization signal based on a first M-sequence of two M-sequences multiplied by a complex value and a second M-sequence of the two M-sequences multiplied by a real value.

Example 103 may include a signal, comprising a secondary synchronization signal based on a bitwise exclusive-or (XOR) operation on cyclic-shifted versions of two M- sequences generated from two distinct primitive polynomials.

Example 104 may include a signal, comprising a secondary synchronization signal based on a modulated symbol-wise multiplication of BPSK-modulated bits of cyclic- shifted versions of two M-sequences generated from two distinct primitive polynomials. Various embodiments may include any suitable combination of the above- described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the“and” may be“and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.