CURRENT IN DC LINK

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims priority to U.S. Provisional Application No. 63/053,127, filed on July 17, 2020, incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

[0002] The present disclosure generally relates to inverters, more specifically to circuit systems with multiple inverters that convert electrical energy between a power source and multiple motor-generators.

BACKGROUND OF THE DISCLOSURE

[0003] An inverter converts electrical energy between direct current (DC) and alternating current (AC). In an electric system, the inverter can connect to an electric machine such as a motor-generator (MG) or any other three-phase load or source. Shown in FIGs. 1 and 2 are the electric system 100 where a load 102 is connected to a DC voltage source 104 and a capacitor 106 through an inverter 108. The inverter 108 includes six power switches (SI through S6) to form a three-phase inverter where the control signal for each power switch is generated by a controller 200. Three types of current pass through the system, one being a DC current Z ^' DC passing through the DC voltage source 104, the other being Z ^' AC passing through the capacitor 106, and lastly the inverter current Z ^' INV which is the sum of the other two currents Z ^' DC and Z ^' AC. The inverter output currents i _a , h, (shown collectively as i _abc in FIG. 1) are the currents passing through the load 102 when the appropriate switches are activated. The AC portion of the inverter current, Z ^' AC, is referred to as ripple current.

[0004] In capacitors, power loss and internal heating are dependent on the current passing through it. In this case, it is the ripple current that passes through the capacitor. Where there is more ripple current, the capacitor degradation is greater because of the rising internal temperature. In some examples, as shown in the ratio curve 300 of FIG. 3, the root mean square (rms) value for the AC portion Z ^' AC can be as high as 65% of the rms value of the inverter output current i _a t _>c depending on the modulation index (M) of the control signal when a three-phase pulse width modulation (PWM) is used. When there are multiple inverters sharing a common DC-link capacitor, the ripple current generated by all inverters can add up to an even higher value. As such, there is a need to reduce the ripple current to improve the power loss and internal heating of the capacitor, improving the functionality of the capacitor and therefore the inverter overall.

SUMMARY OF THE DISCLOSURE

[0005] The present disclosure provides inverter systems that include a direct-current (DC) voltage supply electrically coupled with a DC link, a plurality of inverters each electrically coupled with the DC link, a plurality of electric machines each electrically coupled with one of the inverters, and a controller coupled with each of the inverters. The controller can control carrier signals of the inverters such that the carrier signals are synchronized and interleaved at an angle (Q) that is determined based on the waveform type of the carrier signals and the number of inverters in the system. In some examples, the carrier signals have a triangular waveform and Q = (180 / n)°, where n is the number of inverters. In some examples, the carrier signals have a sawtooth waveform and Q = (360 / n)°, where n is the number of inverters.

[0006] In some examples, the controller applies a discontinuous pulse width modulation

(PWM) to obtain switch control signals for the inverters. In some examples, the controller applies a continuous PWM when modulation index is within a predetermined range. In some examples, the predetermined range is between 0.3 and 0.9, 0.4 and 0.9, or 0.4 and 0.8. In some examples, the controller applies a continuous PWM to obtain switch control signals for the inverters. In some examples, the carrier signals for the plurality of inverters have the same frequency.

[0007] Also disclosed herein are methods or processes of generating a plurality of carrier signals for a plurality of inverters. The method includes determining a number of the plurality of inverters and a waveform type for the plurality of carrier signals, calculating an interleaving angle for the plurality of carrier signals based on the number of inverters and the waveform type, and controlling a carrier signal generator to generate the plurality of carrier signals for the plurality of inverters based on the calculated interleaving angle.

[0008] In some examples, responsive to determining that the waveform type is a triangular waveform, the interleaving angle (Q) is calculated such that Q = (180 / n)°, where n is the determined number of inverters. In some examples, responsive to determining that the waveform type is a sawtooth waveform, the interleaving angle (Q) is calculated such that Q = (360 / n)°, where n is the determined number of inverters.

[0009] In some examples, the method further includes applying a discontinuous pulse width modulation (PWM) to generate switch control signals for the plurality of inverters. In some examples, the method includes applying a continuous PWM when modulation index is within a predetermined range. The predetermined range is between 0.3 and 0.9, between 0.4 and 0.9, or between 0.4 and 0.8, in some examples.

[0010] While multiple embodiments are disclosed, still other embodiments of the present disclosure will become apparent to those skilled in the art from the following detailed description, which shows and describes illustrative embodiments of the present disclosure. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above-mentioned and other features of this disclosure and the manner of obtaining them will become more apparent and the disclosure itself will be better understood by reference to the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, wherein:

[0012] FIG. l is a schematic diagram of an inverter system as known in the art;

[0013] FIG. 2 is a block diagram of an inverter system with a controller as known in the art;

[0014] FIG. 3 is graph illustrating the changes in the ratio of AC portion of the inverter current to the inverter output current for different modulation indices;

[0015] FIG. 4 is a schematic diagram of an inverter system including two inverters, each coupled with a motor-generator and separately controlled via a controller, in accordance with embodiments of the present disclosure;

[0016] FIG. 5A shows a switch control signal formed by comparing a carrier signal and a reference signal;

[0017] FIG. 5B shows a switch control signal formed using triangular waveform carrier signal;

[0018] FIG. 5C shows a switch control signal formed using sawtooth waveform carrier signal; [0019] FIG. 6 shows a graph comparing various modulation methods and the effect of carrier signal interleaving on ripple current ratio, in accordance with embodiments of the present disclosure;

[0020] FIG. 7 A shows a graph comparing various modulation methods and the effect of a

90° interleaving in triangular waveform carrier signals on the ratio of capacitor peak-to-peak voltage ripple to DC voltage, in accordance with embodiments of the present disclosure;

[0021] FIG. 7B shows a graph comparing various modulation methods and the effect of a

180° interleaving in sawtooth waveform carrier signals on the ratio of capacitor peak-to-peak voltage ripple to DC voltage, in accordance with embodiments of the present disclosure;

[0022] FIG. 8 shows an exemplary controller operable to generate the switch control signals for the different sets of inverter switches, in accordance with embodiments of the present disclosure; and

[0023] FIG. 9 shows an exemplary method as implemented by the controller to generate the switch control signals for the inverter switches, in accordance with embodiments of the present disclosure.

[0024] While the present disclosure is amenable to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the present disclosure to the particular embodiments described. On the contrary, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure as defined by the appended claims.

DETAILED DESCRIPTION OF THE DISCLOSURE [0025] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the present disclosure is practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure, and it is to be understood that other embodiments can be utilized and that structural changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and their equivalents. [0026] FIG. 4 shows a schematic diagram of synchronized multi-inverter system 400 with two inverters 402 and 404 coupled with two electric machines such as motor-generators 406 and 408, respectively, where each of the inverters 402 and 404 is parallel to each other with respect to the shared capacitor 106. A controller 407 controls the control signals provided to the switches of the inverters 402 and 404. Each motor-generator has a one-to-one connection with a corresponding inverter. In addition to the switches SI through S6 included in the first inverter 402, there are switches S7 through S12 included in the second inverter 404. In some examples, more inverters and motor-generators may be implemented in parallel to the inverters 402 and 404 mentioned. Because there are two inverters, the inverter current Z ^' INV has two components: Z ^' INVI and Z ^' INV2. The inverter output currents i _a i, hi, hi (shown collectively as hbci in FIG. 4) are the currents passing through the motor-generator 406 when the appropriate switches in switches SI through S6 are activated. Similarly, the inverter output currents i _a 2, ib2, ic2 (shown collectively as i _a bc2 in FIG. 4) are the currents passing through the motor-generator 408 when the appropriate switches in switches S7 through S12 are activated. A DC link is configured to electrically couple both the inverters 402 and 404 with the DC voltage source 104, which may be a battery. Nodes A and B are the common nodes of the DC link to which the inverters 402 and 404 are electrically coupled. [0027] Each of the switches SI through S12 is paired with another switch such that each switch is complementary to the other switch in the same pair. The two switches that share the same node with the motor-generator are paired, for example SI and S2, S3 and S4, and so on. Any suitable power switch may be employed, as known in the art, including but not limited to metal- oxide-semiconductor field-effect transistors (MOSFET), insulated-gate bipolar transistors (IGBT), thyristors, and diodes, among others. Each pair in the same inverter is controlled via a different reference signal such that each reference signal is separated 120° apart from another reference signal, thus creating the three-phase inverter for the motor-generator. Specifically, each switch is controlled using a control signal from the controller 407 that is generated by comparing a carrier signal and a reference signal using a comparator. A comparator outputs a digital signal such that the output is 1 if voltage of the reference signal is greater than voltage of the carrier signal, and 0 if otherwise. The carrier signal may be a sawtooth or triangular waveform signal as suitable, and the controller or processing unit may use this information to determine the amount of interleaving between the reference signals. As such, the inverter system of 400 is synchronized in that the controller 407 operates to ensure that the inverters 402 and 404 have an identical switching frequency (a.k.a. carrier signal frequency). Other factors of the inverters, such as their output voltages, output currents, and power factors, may vary from each other.

[0028] Examples of multi-inverter systems include electric vehicles each having a front machine and a rear machine (requiring two inverters), power-split hybrid vehicles each having a motor and a generator (also requiring two inverters), or vehicles with wheel-hub machines where one inverter is assigned to the operation of each pair of wheels, which may include any suitable number of inverters as determined by the number of wheels.

[0029] FIG. 5A illustrates an example of the reference signal 500 being compared with the carrier signal 502 to generate the switch control signal 504. In this example, the reference signal 500 being used is a continuous sinusoidal signal, and the carrier signal 502 is a triangular waveform signal with a higher frequency than the reference signal 500. The voltage range of the carrier V _carrier is greater than the voltage range of the sinusoidal reference signal Y _sm ·

[0030] FIG. 5B shows an example where two switch control signals 504A and 504B are formed as disclosed herein, according to some embodiments. The first switch control signal 504A is generated by comparing the first reference signal 500A to the first carrier signal 502A, and the second switch control signal 504B is generated by comparing the second reference signal 500B to the second carrier signal 502B. Both the first and second carrier signals 502A and 502B are triangular waveform signals, and the second carrier signal 502B has an offset angle 506 (also referred to as phase shifting or interleaving the carrier signals) of 90° (electrical degree) from the first carrier signal 502A. Therefore, when the first carrier signal 502A is at its peak, the second carrier signal 502B is in the midpoint between its peak and nadir.

[0031] FIG. 5C shows an example where two switch control signals 504C and 504D are formed as disclosed herein, according to some embodiments. The first switch control signal 504C is generated by comparing the first reference signal 500C to the first carrier signal 502C, and the second switch control signal 504D is generated by comparing the second reference signal 500D to the second carrier signal 502D. Both the first and second carrier signals 502C and 502D are sawtooth waveform signals, and the second carrier signal 502D has a 180° offset 508 from the first carrier signal 502C. Therefore, when the first carrier signal 502C is experiencing the drop in voltage, the second carrier signal 502D is in the midpoint between two drops, i.e. halfway up the “ramp” in the sawtooth waveform. [0032] FIG. 6 is a graph showing the experimental results of applying the method of interleaving or offsetting carrier signals as explained above (that is, 90° interleaving for a triangular waveform and 180° interleaving for a sawtooth waveform). A normalized DC-link ripple current is calculated by dividing the value of the current from the shared capacitor 106 by the value of the inverter output current. The graph compares the different pulse width modulation (PWM) methods and shows how interleaving the carrier signals affects the ratio of ripple current to inverter output current for a range of modulation indices when power factor is 1. For comparison, the data curve 300 from FIG. 3, where no interleaving is performed on the carrier signal, is inserted into the graph. The value of the data curve 300 is doubled as compared to the values in FIG. 3 due to the presence of two inverters instead of just one. This is because when two inverters operate exactly in the same way and share a common DC link, the current ripple doubles compared to when only one inverter is in the system.

[0033] The dotted lines represent the data curves for discontinuous PWM, such as

DPWM0, DPWM1, DPWM2, DPWM3, and generalized discontinuous PWM (GDPWM), all of which are performed using modulation waveforms as known in the art. The continuous lines represent the data curves for continuous PWM including sinusoidal PWM (SPWM), third harmonic injection PWM (TfflPWM) with an amplitude of either 1/4 or 1/6 of the fundamental reference voltage, and space vector PWM (SVPWM), all of which are also performed using modulation waveforms as known in the art described in A. M. Hava, R. J. Kerkman and T. A. Lipo, “A high-performance generalized discontinuous PWM algorithm,” in IEEE Transactions on Industry Applications, vol. 34, no. 5, pp. 1059-1071, Sept.-Oct. 1998, doi: 10.1109/28.720446. [0034] As can be observed from FIG. 6, the presence of interleaving carrier signals lower the current ripple ratio (the ratio of ripple current to load current) from 1.3 when there is no interleaving (300) to less than 1 when there is interleaving, or even less, as further explained herein. The ripple current reduction in discontinuous PWMs differs from continuous PWMs in that the continuous PWMs tend to have greater reduction in a range of modulation index of between M = 0.4 and M = 0.9. For example, focusing on this specific range of modulation indices, it is observed that in this range, the continuous PWMs maintain lower current ripple ratios than the discontinuous PWMs. For example, at the modulation index of M = 0.6, when the non-interleaved model experiences the highest ripple current, the SVPWM and both THIPWMs achieve the lowest current ripple ratio of 0.3, thereby achieving approximately 77% reduction in ratio compared to the peak at 1.3 at the same modulation index when no interleaving is applied. Even for SPWM, the ripple current ratio is 0.5 at M = 0.6, which is still lower than any of the discontinuous PWMs. The actual ratio values may change depending on the number of inverters that are implemented.

[0035] FIGs. 7 A and 7B show the voltage ratio curves of the aforementioned types of continuous and discontinuous PWMs, where the voltage ratio is calculated by dividing the capacitor peak-to-peak voltage ripple by the DC voltage assuming a certain DC-link capacitance. The percentage of the capacitor voltage ripple is preferably low to ensure a stable DC-bus voltage. The capacitor voltage ripple is proportional to the integral of the ripple current passing through the capacitor. FIG. 7A shows the voltage ratio curves measured when the 90° interleaving is applied to the triangular waveform carrier signals, and FIG. 7B shows the voltage ratio curves measured when the 180° interleaving is applied to the sawtooth waveform carrier signals.

[0036] The interleaving of certain degrees between the two or more carrier signals is shown to be beneficial in reducing the ripple current passing through the capacitor in the inverter system. Although the amount of reduction in the ripple current may vary depending on the type of modulation that is being applied, such as continuous or discontinuous, generally the reduction is the greatest for continuous PWMs within the modulation index range of between M = 0.4 and M = 0.9. In some examples, the continuous PWMs may be TfflPWM or SVPWM.

[0037] In some examples, the controller switches between continuous and discontinuous

PWMs when the modulation index that is being used is within the range of between M = 0.4 and M = 0.9. Advantages in switching from a discontinuous PWM to a continuous PWM during a specific range of modulation index include the ability to keep using discontinuous PWM when there is only a small difference in the ratio of ripple current to load current between using discontinuous PWM and continuous PWM. In some examples, using a discontinuous PWM reduces losses during switching, for example in IGBT switches or any other suitable types of switches as known, therefore operate at a higher efficiency than when a continuous PWM is employed. In some examples, the use of a discontinuous PWM allows the switch to operate at a higher frequency before reaching the same internal temperature as when a continuous PWM is used; that is, the switch which uses the discontinuous PWM may operate at a lower internal temperature than the same switch when using the continuous PWM, if the current through the switch remains the same during both PWMs. [0038] FIG. 6 shows the continuous PWMs and most of the discontinuous PWMs (the notable exception being the GDPWM which appears to have lower ratio than the other discontinuous PWMs between M = 0.1 and M = 0.7 according to the graph) having similar current ratio in the modulation index range of less than M = 0.3 or greater than M = 0.9. The similar ratios may be defined as the ratios having a difference of less than 10% or 5% from each other, for example. Therefore, the controller may switch from discontinuous PWM to continuous PWM in certain predetermined ranges as theoretically determined or experimentally measured. In some examples, the predetermined ranges may be any one of the following ranges: from M = 0.3 to M = 0.9, from M = 0.4 to M = 0.9, and from M = 0.4 to M = 0.8.

[0039] Although the synchronized inverter system 400 is shown with two inverters, there may be any additional number of inverters that are implemented parallel to the two inverters, as previously explained. When the number of inverters increases, the offset or interleaving angle 506 or 508 shown in FIGs. 5B and 5C that achieves low ripple current also changes according to the following formulas:

For triangular waveform carrier signals, Interleaving Angle (Q) =

For sawtooth waveform carrier signals, Interleaving Angle (Q) = where n = the number of inverters in the system that share the common DC link and therefore are parallel to each other. As such, when there are three inverters, the interleaving angle (Q) is 60° for the triangular waveform and 120° for the sawtooth waveform, and when there are four inverters, the interleaving angle (Q) is 45° for the triangular waveform and 90° for the sawtooth waveform, etc. These inverters, regardless of the number of inverters, can have different current, voltage, power factor, and functions (that is, whether the motor-generator that is coupled with the inverter is being used as a motor or generator), so long as the carrier signal frequency remains the same amongst all the inverters.

[0040] FIG. 8 is a high-level block diagram of an exemplary controller 407 as illustrated in FIG. 4. The activation of the switches SI through S12 of the inverters 402 and 404 is regulated using PWM control implemented by the controller 407. The controller 407 has a switching regulator that generates switch control signals 504 that can be used to turn switches SI through S12 on and off. Specifically, the switching regulator includes a plurality of comparators 800, a reference signal generator 802, and a carrier signal generator 804.

[0041] The carrier signal generator 804 receives or detects the number of inverters (n) that are implemented in the multi-inverter system 400. In the example shown, there are two inverters 402 and 404 sharing the common DC link, so the carrier signal generator 804 calculates the interleaving angle (Q) using the formulas as explained herein, where the angle is dependent upon the waveform type (that is, sawtooth or triangular) of the carrier signal, which is also detected or received. Any suitable method of detection of the number of inverters and the waveform type may be implemented, for example via sensors.

[0042] In the example shown, the reference signal generator 802, which may be any suitable signal generating device, receives or detects the inverter output currents i _a bd and i _a bc2 as previous discussed, as well as motor position angles qi and Q2 of the motor being driven by inverters 402 and 404, respectively. Based on these inputs, the reference signal generator 802 generates a reference signal 806 for each pair of switches in the inverters. The exemplary system 400 includes two inverters with three pairs of switches, therefore there are a total of six comparators 800A through 800F, each receiving corresponding one of the reference signals V _ai , Vbi, Vci, Va2, Vb2, and V _C 2, as input.

[0043] At the same time as the reference signals 806 are generated by the reference signal generator 802, the carrier signal generator 804 generates two carrier signals 808A and 808B, where the two signals differ from each other by the interleaving angle Q as calculated based on the inputted number of inverters and the type of waveform signal being implemented. The first carrier signal 808A is inputted into the comparators 800A, 800B, and 800C of the first inverter 402, and the second carrier signal 808B is inputted into the comparators 800D, 800E, and 800F of the second inverter 404.

[0044] Each of the comparators 800 subsequently compares the inputted reference signal

806 with the inputted carrier signal 808 and outputs switch control signals 810 for each pair of switches, such that one switch of the pair receives the switch control signal 810 as is and the other switch of the pair receives the inverted signal after the switch control signal 810 passes through a corresponding inverter logic gate 812, as shown. As the number of inverters increases, the number of comparators 800, the number of different reference signals generated by the reference signal generator 802, and the number of different carrier signals generated by the carrier signal generator 804 may also increase accordingly. It is to be understood that FIG. 8 is shown as an illustrative example only, and some examples or embodiments of the controller may include additional components as suitable to facilitate synchronized controlling of the inverters with respect to the determined interleaving angle.

[0045] FIG. 9 illustrates an exemplary process 900 as implemented by the controller 407 to generate the switch control signals 810 as shown in FIG. 8. In step 902, the controller determines the number of inverters that are being operated in the system as well as the type of waveform of the carrier signal that is to be generated. In step 904, the controller calculates the interleaving angle based on the number of inverters and the type of waveform as determined in step 902. For example, when the waveform type is a triangular waveform, the interleaving angle Q is calculated such that Q = (180 / n)°, where n is the determined number of inverters; alternatively, when the waveform type is a sawtooth waveform, the interleaving angle Q is calculated such that Q = (360 / n)°. Then, in step 906, the controller controls the carrier signal generator to generate interleaved carrier signals for the determined number of inverters based on the determined interleaving angle. Therefore, each of the interleaved carrier signals are offset by the interleaving angle before being input into the comparator as disclosed herein.

[0046] In some examples, the process 900 also includes applying a discontinuous PWM to generate the switch control signals for the plurality of inverters, and in some cases applying a continuous PWM when modulation index is within a predetermined range. The predetermined range of modulation index may be between 0.3 and 0.9, between 0.4 and 0.9, or between 0.4 and 0.8, for example, as explained herein.

[0047] The disclosure pertains to any system with a plurality of inverters, where each inverter is coupled with the common DC link (and therefore, a common DC voltage source) to convert the DC voltage from the DC link to AC voltage for a motor-generator (which may be a motor, a generator, or both). In some examples, each inverter is coupled to one and only one motor-generator, and the motor-generators operate independently of each other but are synchronized by a common controller that operates to adjust the carrier signals of the inverters. The synchronized inverter system may be employed in vehicles such as electric or hybrid vehicles, power generators such as backup electric generators for emergency power systems, and any other electrical application which involves two or more motor-generators. Additionally, the controller may include any suitable electronic device such as a microcontroller, processing unit, or computing device, among others, that is capable of synchronizing the inverters using switch control signals produced as explained above.

[0048] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. For example, it is contemplated that features described in association with one embodiment are optionally employed in addition or as an alternative to features described in association with another embodiment. The scope of the present disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.