Title:
SYNCHRONIZER WITH ZERO METASTABILITY
Document Type and Number:
WIPO Patent Application WO2002015403
Kind Code:
A9
Abstract:
A synchronizer eliminates metastability due to violation of either the setup time or the hold time of a circuit. The input of a first flip-flop (12a) is tied to a constant logic level (VDD or ground). The first flip-flop receives an asynchronous signal into the reset (preset or clear) input of the flip-flop. No violation of the setup or hold times of the flip-flop can occur. The second flip-flop (12c) receives the output of the first flip-flop as its clock input. The second flip-flop (12c) is configured as a toggler. The second flip-flop produces a synchronized partial signal (18a) of the original asynchronous signal (10a). Third and fourth flip-flops (12b,12d) may similarly be configured to produce a second synchronized partial signal (18b) of the asynchronous signal recovery and may prevent runt pulses from being received by the flip-flops.
Inventors:
CAVAZOS JOSE ALBERTO (US)
SIMLE ROBERT MAURISE (US)
SIMLE ROBERT MAURISE (US)
Application Number:
PCT/US2001/025401
Publication Date:
March 27, 2003
Filing Date:
August 14, 2001
Export Citation:
Assignee:
CAVAZOS JOSE ALBERTO (US)
SIMLE ROBERT MAURISE (US)
SIMLE ROBERT MAURISE (US)
International Classes:
H03K3/037; H03K5/125; H03K5/135; H03L7/00; H04L7/02; (IPC1-7): H03L7/00
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