Title:
SYNCHRONIZING LOOP CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2012/077249
Kind Code:
A1
Abstract:
Provided is a synchronizing loop circuit capable of effectively reducing quantization noise even when the cutoff frequency of a loop filter is not set to be low. A phase comparator (2) is configured so as to detect and compare a first state transition when the voltage level of each of an input signal (Fin1) and a feedback signal (Fin2) transitions from a predetermined first voltage level to a second voltage level higher than the first voltage level, and to detect and compare a second state transition from the second voltage level to the first voltage level. The sampling frequency (fs) of a delta-sigma modulator (4) is set to a higher frequency than the phase comparison frequency (fa) of a case where the phase of the input signal (Fin1) and the phase of the feedback signal (Fin2) have been synchronized.
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Inventors:
INUKAI FUMIHITO
Application Number:
PCT/JP2011/002785
Publication Date:
June 14, 2012
Filing Date:
May 19, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
INUKAI FUMIHITO
INUKAI FUMIHITO
International Classes:
H03L7/085; H03K5/26; H03L7/08; H03L7/081; H03L7/183; H03L7/197; H03M3/02
Foreign References:
| JP2005236536A | 2005-09-02 | |||
| JP2003273651A | 2003-09-26 | |||
| JP2000049579A | 2000-02-18 | |||
| JPH10126263A | 1998-05-15 | |||
| JP2006303663A | 2006-11-02 |
Attorney, Agent or Firm:
PATENT CORPORATE BODY ARCO PATENT OFFICE (JP)
Patent business corporation Owner old patent firm (JP)
Patent business corporation Owner old patent firm (JP)
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Claims:
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