Title:
SYNTHESIZER WITH LOCK DETECTOR, LOCK ALGORITHM, EXTENDED RANGE VCO, AND A SIMPLIFIED DUAL MODULUS DIVIDER
Document Type and Number:
WIPO Patent Application WO2002052728
Kind Code:
A3
Abstract:
The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
Inventors:
SU DAVID K
YUE CHIK PATRICK
WEBER DAVID J
ZARGARI MASOUND
YUE CHIK PATRICK
WEBER DAVID J
ZARGARI MASOUND
Application Number:
PCT/US2001/048874
Publication Date:
November 20, 2003
Filing Date:
December 17, 2001
Export Citation:
Assignee:
ATHEROS COMM INC (US)
International Classes:
H03K23/66; H03L7/095; H03L7/099; H03L7/10; H03L7/183; H03L7/193; H03L7/089; (IPC1-7): H03L7/095; H03L7/099; H03L7/193; H03K23/66
Foreign References:
| US4751469A | 1988-06-14 | |||
| GB2120478A | 1983-11-30 | |||
| US5648744A | 1997-07-15 | |||
| US4403342A | 1983-09-06 |
Other References:
CHARASKA J: "A DIGITAL METHOD OF CONTROLLING ADAPT MODE AND DETECTING PHASE LOCK IN A FREQUENCY SYNTHESIZER", MOTOROLA TECHNICAL DEVELOPMENTS, MOTOROLA INC. SCHAUMBURG, ILLINOIS, US, vol. 38, June 1999 (1999-06-01), pages 7 - 9, XP000906012, ISSN: 0887-5286
PATENT ABSTRACTS OF JAPAN vol. 007, no. 148 (E - 184) 29 June 1983 (1983-06-29)
PATENT ABSTRACTS OF JAPAN vol. 007, no. 148 (E - 184) 29 June 1983 (1983-06-29)
Download PDF:
Previous Patent: DELAY CIRCUIT HAVING ADJUSTABLE DELAY
Next Patent: DECODER, SYSTEM AND METHOD FOR DECODING TURBO BLOCK CODES
Next Patent: DECODER, SYSTEM AND METHOD FOR DECODING TURBO BLOCK CODES