Title:
SYSTEM FOR AIDING DEBUGGING OF INTEGRATED CIRCUIT MICROPROCESSOR
Document Type and Number:
WIPO Patent Application WO/1993/025967
Kind Code:
A1
Abstract:
In the system, a machine instruction fetched by an instruction fetching unit (3) is transferred to an instruction recognizing unit (6) as well as to an instruction decoding unit (4). The instruction recognizing unit (6) judges whether or not the operation-code part of the transferred machine instruction is the operation-code to generate a break operation. When an affirmative decision is made, the instruction decoding unit (4) is informed of the message to that effect. The instruction decoding unit (4) transfers a predefined decode result instructing the break operation instead of the decode result of the fetched instruction to an instruction executing unit (5). Thereby, the break operation is started by the instruction executing unit. Therefore, without sensing the address generated with the execution of the instruction, a break is caused at the time intended by the program, and the debugging can be performed.
Inventors:
MATSUMOTO YUUKOU (JP)
Application Number:
PCT/JP1992/000743
Publication Date:
December 23, 1993
Filing Date:
June 08, 1992
Export Citation:
Assignee:
V M TECHNOLOGY CORP (JP)
MATSUMOTO YUUKOU (JP)
MATSUMOTO YUUKOU (JP)
International Classes:
G06F11/36; G06F11/00; (IPC1-7): G06F11/28
Foreign References:
| JPS58165148A | 1983-09-30 | |||
| JPS63163543A | 1988-07-07 |
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