The present invention relates to chip processors. More particularly, the invention relates to+ hip processors for wireless baseband processing.

BACKGROUND ART

Advances in semiconductor technology have provided high performance, miniaturized processors coupled with wireless communications connectivity. SoC (System-on-chip) architecture refers to an integrated circuit formed on a single chip substrate which consists of a plurality of processors, system buses, hardware accelerators, interface controller and other necessary elements of a desired electronic system where it may contain digital, analog, mixed-signal, or radio-frequency functions. SoC technology is integrated into the wireless communications systems such as baseband processing system.

Baseband processing refers to the execution of digital communication functions that occur within the frequency range around zero before modulation during transmission and after demodulation during reception.

Good desirable SoC architecture for wireless applications such as baseband processing has to be flexible and possess powerful real-time processing capabilities.

However, existing SoC architecture for wireless applications has a fixed structure which only enables certain wireless applications and not flexible for multiple wireless system solutions. Existing SoC architecture uses shared memory and system bus to connect processors and external peripherals which results bottleneck and contentions in data flow which affects the prompt response to real-time data and is not suitable for real-time signal processing.

The present invention is made in view of the problems cited. It is an object of the invention to provide an improved SoC architecture for wireless applications by improving prompt response real-time data.

SUMMARY OF INVENTION The present invention provides a SoC architecture which is capable of eliminating the contentions in data flow and flexible for multiple wireless system solutions. The SoC architecture consists of a DSP (Digital-Signal-Processors) subsystem in which consist of a plurality of DSPs coupled with a plurality of hardware accelerators, capable of providing high performance computational function and flexibility for future updates. The SoC architecture also consists of dedicated connections between its components on the critical data path to avoid contentions. An embodiment of the SoC architecture according to the present invention includes a DSP (Digital-Signal-Processors) subsystem in which consists of a master processor, two secondary processors, a crypto engine, FEC (Forward-Error-Correction) engine, FFT (Fast-Fourier-Transform) engine, ADC (Analog-to-Digital converter) interface, DAC (Digital-to-Analog converter) interface, and RF (Radio-frequency) interface; a peripheral subsystem in which consist of a plurality of controllers connected through system bus; and a DSP-to-Peripheral bridge which is coupled to master processor and the peripheral subsystem wherein said bridge is responsible for critical protocol conversion and eliminates contention in data path. Master processor is coupled directly with secondary processors to improve responsiveness of real-time data between the DSPs. Master processor functions to coordinate the whole chip operation and MAC (Media Access Control) layer operation. Both secondary processors are configured to be slave processors, each performing PHY (Physical) layer frequency domain operation, or performing the PHY layer time domain operation. The dedicated channels that links the modules together, enables a seamless data flow for both the transmitter and receiver flows.

BRIEF DESCRIPTION OF DRAWINGS Further characteristics and advantages of the present invention will become better apparent from the following detail description of a preferred but not exclusive embodiment thereof, illustrated by way of non-limiting example in the accompanying drawings, wherein: FIG. 1 is a top level block diagram of the SoC architecture for wireless applications according to the invention;

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FIG. 2 is a flow chart showing a typical data transmission and reception flow of a typical wireless system; and

FIG. 3 is a diagram showing the processing task distribution between DSPs through the connections of DSPs as shown in FIG. 1.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to the preferred embodiments of the invention which is intended to provide a thorough understanding of the present invention. However, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

In an embodiment of the present invention, a block diagram of SoC architecture [10] fabricated on a single integrated chip such as silicon is as shown in FIG. 1. A SoC architecture [10] comprising a DSP (Digital Signal Processor) subsystem [12] includes a master processor DSP-1 [14], a first secondary processor DSP-2 [16], a second secondary processor DSP-3 [18], a crypto engine [20], a FEC (Forward-Error-Correction) engine [22], a FFT (Fast-Fourier-Transform) engine [24], an ADC (Analog-to-Digital converter) interface [26], a DAC (Digital-to-Analog converter) interface [28], and a RF (Radio-frequency) interface [30]; a peripheral subsystem [32] includes a plurality of controllers [34] connected through system bus [36]; and a DSP-to-Peripheral bridge [38] which coupled to DSP-1 [14] and the peripheral subsystem [32] where said bridge [38] is responsible for critical protocol conversion. DSP-1 [14] is in direct connection with secondary processors such as DSP-2 [16] and DSP-3 [18] and is supported by accelerators such as crypto engine [20] and FEC engine [22]. The crypto engine [20] encrypts higher layer data into MAC layer data, as well as decrypts MAC layer data into higher layer data. FEC engine [22] transfers encoded data from master processor DSP-1 to first secondary processor DSP-2, as well as transfers error corrected data from first secondary processor DSP-2 to master processor DSP-1. The first secondary processor DSP-2 [16] provides PHY layer frequency domain operation; and the second secondary processor DSP-3 [18] provides PHY layer time domain operation. DSP-2 [16] is coupled to fast-Fourier-transform (FFT) engine [24], said engine perform frequency domain processing for transmission of MAC protocol. Fast Fourier Transform operation is performed on frequency domain signal or frequency domain signal is delivered from Inverse Fast Fourier Transform. DSP-3 [18] is coupled to a fast-Fourier-transform (FFT) engine [24], said engine perform time domain processing for transmission of MAC protocol. Inverse Fourier Transform operation is performed on time domain signal or time domain signal is delivered from Fast Fourier Transform operation. This configuration of the DSP subsystem [10] component result in a faster processing speed compared to existing system solution. DSP-1 [14] is also in direct connection with peripheral subsystem [32] via DSP-to-Peripheral bridge [38] and this provides a dedicated path for critical protocol conversion and eliminates the problem of contentions in data path occurred in system bus connections.

A method of SoC architecture for wireless application involves transforming data from MAC layer [44] to PHY layer [50] for transmission and from PHY layer [50] to MAC layer [44] for reception.

FIG. 2 shows a typical data transmission flow [40] and reception flow [42] of a typical system. The data transmission flow [40] starts from the DSP-1 [14] wherein DSP-1 [14] collects higher layer data from peripheral subsystem [32] via DSP-to-Peripheral Bridge [38]. The higher layer data is transformed to MAC protocol data units by executing stored program at DSP-1 and encryption at crypto engine [20]. The MAC protocol data units are then transferred to FEC engine [22] for transformation of data to the frequency domain data and are then transferred to DSP-2 [16] for executing stored program. The frequency domain data is then transfered to FFT engine [24] to be transformed to time domain data. DSP-3 [18] collects and processes the time domain data from FFT engine [24] by means of stored program before transferring the binary encoded air interface data to DAC interface [28]. Reception flow [42] follows the reverse path of transmission flow [40] where the binary encoded air interface data is collected at ADC interface [26]. The dedicated channels that link the components together provide a capability of seamless data flow in the SoC architecture [10]. FIG. 3 shows the equal distribution of MAC layer [44] and PHY layer [50] operations from DSP-1 [14] to DSP-2 [16] and DSP-3 [18]. The distributed processing capability doubles the processing power and enables a particular task can be completed in half the time.

Accordingly, this solution reduces the problems related to inflexible of SoC architecture for multiple wireless system solutions, bottlenecks and contentions in data flow which affects the prompt response to real-time data.