Title:
SYSTEM AND METHOD FOR GENERATING RANDOM BIT STRING IN AN INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/180743
Kind Code:
A3
Abstract:
Embodiments herein provide a system and a method for generating a random bit string in an Integrated Circuit. Predefined number of One-time Programmable Memory (OTPM) devices are connected in parallel with each OTPM device configured for producing a random bit-string. Current limiting circuit is connected in series with the at least two OTPM devices. Voltage source supplies a predefined voltage to the at least two OTPM devices for producing a breakdown in one of an OTPM device of the at least two OTPM devices resulting in a broken OTPM device while leaving remaining OTPM devices of the at least two OTPM devices unbroken. The random bit string is generated through at least one of the broken OTPM device and a remaining unbroken OTPM device of the at least two OTPM devices.
Inventors:
GANGULY UDAYAN (IN)
SADANA SUNNY (IN)
SANJAY LELE ASHWIN (IN)
SADANA SUNNY (IN)
SANJAY LELE ASHWIN (IN)
Application Number:
PCT/IN2019/050229
Publication Date:
November 14, 2019
Filing Date:
March 20, 2019
Export Citation:
Assignee:
INDIAN INST TECHNOLOGY BOMBAY (IN)
International Classes:
G06F21/60; G06F21/44; G06F21/70; G06F21/71; G06F21/72; G06F21/73; G06F21/75; G06F21/76; G06F21/77
Domestic Patent References:
| WO2008015603A1 | 2008-02-07 |
Foreign References:
| US20170024339A1 | 2017-01-26 | |||
| US20120110676A1 | 2012-05-03 | |||
| US20140327468A1 | 2014-11-06 | |||
| US20100085075A1 | 2010-04-08 |
Attorney, Agent or Firm:
NARASANI, Arun Kishore (IN)
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