SYSTEM AND METHOD FOR MANAGING PEAK POWER DEMAND AND NOISE IN NON-VOLATILE MEMORY ARRAY

Title:

SYSTEM AND METHOD FOR MANAGING PEAK POWER DEMAND AND NOISE IN NON-VOLATILE MEMORY ARRAY

Document Type and Number:

WIPO Patent Application WO/2019/182684

Kind Code:

A3

Abstract:

A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

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Inventors:

TIWARI VIPIN (US)
TRAN HIEU (US)
DO NHAN (US)
REITEN MARK (US)

Application Number:

PCT/US2019/015369

Publication Date:

May 14, 2020

Filing Date:

January 28, 2019

Export Citation:

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Assignee:

SILICON STORAGE TECH INC (US)

International Classes:

G11C8/08; G11C7/12; G11C8/12; G11C16/08; G11C16/24

Foreign References:

US8305806B2	2012-11-06
US5602784A	1997-02-11
US7382657B2	2008-06-03
US8400864B1	2013-03-19

Other References: