Title:
SYSTEM AND METHOD FOR STORE INSTRUCTION FUSION IN A MICROPROCESSOR
Document Type and Number:
WIPO Patent Application WO/2020/024759
Kind Code:
A1
Abstract:
The disclosure relates to technology executing store and load instructions in a processor. Instructions are fetched, decoded and renamed. When a store instruction is fetched, the instruction is cracked into two operation codes in which a first operation code is a store address and a second operation code is a store data. When a fusion condition is detected, the second operation code is fused or merged with an arithmetic operation instruction for which a source register of a store instruction matches a destination register of the arithmetic operation instruction. The first operation code is then dispatched/issued to a first issue queue and the second operation code, fused with the arithmetic operation instruction, is dispatched/issued to a second issue queue.
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| JP3641448 | ARITHMETIC PROCESSOR |
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Inventors:
WANG QIAN (US)
MA XIAOHAN (US)
JIANG XINGYU (US)
MA XIAOHAN (US)
JIANG XINGYU (US)
Application Number:
PCT/CN2019/094494
Publication Date:
February 06, 2020
Filing Date:
July 03, 2019
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F9/30
Foreign References:
| US20180095761A1 | 2018-04-05 | |||
| CN102163139A | 2011-08-24 | |||
| CN101178644A | 2008-05-14 | |||
| CN102193775A | 2011-09-21 |
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