Title:
MULTILANE/MULTICORE SYSTEM AND METHOD
Document Type and Number:
WIPO Patent Application WO/2016/091164
Kind Code:
A1
Abstract:
A multilane/multicore system and method. The multilane/multicore system comprises a plurality of lanes/processor cores (80, 81, 82, 83), with each being capable of executing the same or different instructions and accessing a memory. The multilane/multicore system may also comprise a loop controller and a data engine, which are used to perform memory read or write data operations during execution of a loop program, in order to avoid the explicit appearance of data access instructions in the loop program. The system may also perform a post-processing operation on the execution result of the plurality of lanes/processor cores, and access the memory. The post-processing operation can be realized by the lanes/processor cores or dedicated post-processors (84, 85, 86). Map/reduce operations using the multilane/multicore system having the post-processors can avoid a large amount of memory access operations in conventional multilane/multicore systems, and accordingly performances are improved significantly.
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Inventors:
LIN KENNETH CHENGHAO (CN)
Application Number:
PCT/CN2015/096769
Publication Date:
June 16, 2016
Filing Date:
December 09, 2015
Export Citation:
Assignee:
SHANGHAI XINHAO MICROELECTRONICS CO LTD (CN)
International Classes:
G06F15/167; G06F9/38
Foreign References:
| CN101299199A | 2008-11-05 | |||
| CN102880594A | 2013-01-16 | |||
| CN101477512A | 2009-07-08 | |||
| US7535844B1 | 2009-05-19 | |||
| CN102362256A | 2012-02-22 |
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