Scope of the invention

The present invention relates to the domain of video equipment.

The present invention relates more specifically to a system for transmission of a synchronization signal between two items of equipment connected by a communications network. The invention is particularly useful when the items of equipment are video equipment, for example a video source and a display device, both using a common video frequency, for example 27MHz, the synchronization signal being realized from a frequency signal at 1 GHz. The communications network is a packet switching network, for example of IP (Internet Protocol) type, whether the network is wired (for example Ethernet (IEEE802.3)) or wireless (for example IEEE 802.16 D-

2004).

Prior art

Progress in the ability of IP networks to transport all types of signal

(data or video) has made it possible to use these networks as the "backbone" architecture for video studios. Of capital importance to this evolution is therefore having a single infrastructure for the transport of data. Whereas in the past, several media were necessary to transport different signal types between items of equipment, the multiplexing properties offered by the IP layer enable a reduction in the number of media necessary: an IP network that links the different items of equipment.

In the prior art, the synchronisation of items of video equipment (cameras, etc.) in a studio is carried out by the transmission of a synchronisation signal commonly called "Genlock" or "Black burst". For example, the Genlock signal comprises two synchronisation signals, one is repeated every 40 ms and indicates the start of the video frame, the other is repeated every 64 μs (for a standard format and less for an HD format) and indicates the start of lines in the video frame. The waveforms of synchronisation signals are a function of the format of the image transmitted on the network. For example, for a high definition image, the signal synchronisation has a tri-level form (-30OmV, OV, +300 mV).

When a synchronisation signal is routed to different items of equipment to be synchronised by a dedicated coaxial cable, a constant transmission time, without jitter is ensured. From such a signal, all items of equipment are able to reconstruct a timing clock that is specific to its functioning, which guarantees that its functioning is rigorously in phase with all the equipment connected to the same network. For example, two cameras synchronised by a Genlock signal circulating on a dedicated coaxial cable each generate a video with different contents but rigorously in frequency and in phase with one another.

A known disadvantage presented by an IP/Ethernet network is that it introduces a strong jitter in a transmission of signals, and particularly for the transmission of a synchronisation signal. When such a signal is routed by an IP/Ethernet connection to different items of equipment for synchronising, this jitter results in fluctuations in the length of time required for the information carried by the synchronisation signal to reach the equipment.

In the prior art, for a set of devices, for example cameras, connected to an IP network, devices are known to reconstruct at the level of each camera, a timing clock specific to this camera enabling it to overcome jitter. The underlying principle of these devices is a high attenuation of the synchronisation signal jitter amplitude at the level of reception. In such a way, it can be guaranteed that an image generated by a camera is rigorously in phase with all of the images generated by neighbouring cameras connected to the same network.

Examples of such video synchronisation devices for jitter attenuation are described in the international PCT application FR2007/050918, they act on program clock reference (PCR) signals that represent reference clock signals. These very precise digital signals are provided to cameras via a network so that they can locally reconstruct clock signals that are in phase with the reference clock. The creation of the digital signal transported on the network and the reconstruction of clock signals are realised by a sampling clock CLKech common to the transmission device and the reception devices. Specifically this clock CLKech must be perfectly identical for the transmission device and all the reception devices. A disadvantage of the systems of the prior art is that the transported digital signal of the transmission device to the reception devices is created from a counting ramp comprising temporal steps whose duration correspond to the frequency of the clock signal of the synchronization signal.

However it can be shown that this counting ramp can also be used to carry out a time labelling service and transmit temporal markers from the transmission side to the reception side: an example of such a transmission application is described in the French patent application FR 0852687. In this case, the minimum precision that can be expected on the temporal marker also corresponds to the duration of a counting ramp step. For a video application where the clock frequency transmitted in the synchronization signal is equal to 27MHz, the duration of the step corresponds to 37 nanoseconds. It is therefore not possible to transmit a temporal marker with a better temporal precision than 37 ns: This can constitute an inconvenient restriction. Moreover, some users prefer to work with standard temporal references of a period equal to one second, one microsecond, or one nanosecond. In this case, remaining in the context of a video application there is an interest in finding a means of working with a frequency decoupled from the video frequency (27 MHz), for example a frequency equal to 1 GHz, to create a counting ramp while ensuring a correct and synchronous synchronization transmission of a 27 MHz clock

One of the purposes of the present invention is to overcome this disadvantage in or to create counting ramps for which the steps have a duration that is different to the period of the clock frequency of the synchronization signal to be transmitted.

Summary of the invention The technical problem that the present invention proposes to resolve is to ensure a decoupling between the duration of steps of the counting ramps used to create a synchronization signal between a transmission device and a reception device and the working frequency of said devices. For this purpose, the present invention relates to, according to a first aspect, a transmission device able to transmit packets in a packet communication network, said device comprising the means (EXS) to extract clock signals (CLK) and pulses (IMP1 ) at frequency FV synchronous with signals (CLK) from a synchronization signal (SGO). According to the invention the device also comprises:

- the means (DIVP) to produce, from the pulses (IMP1 ) and said clock signals (CLK), a signal (SA) at frequency FA such that FA = FV/P where P is an integer number,

- the means (LFVO1 ) to produce from a signal (SCOMP1 ) a signal (SB) at frequency FB greater than FA,

- the means (DIVQ) to produce, from the signal (SB), a signal (SC) at frequency FC so that FC = FB/Q where Q is an integer number,

- the means (DIVR) to produce, from the signal (SC), a signal (CLR) at frequency FCLR so that FCLR = FC/R where R is an integer number, - the means (COMP1 ) to compare the signal (SA) with the signal (SC), said means (COMP1 ) delivering a comparison signal (SCOMP1 ),

- a counter (CPT_PCR1 ) whose rate is determined by the signal (SB) and initialized by the signal (CLR), said counter (CPT_PCR1 ) produced from counting ramps (CSE_PCR), - the means (LATCH1 ) to realize the samples (PCR _e ) of ramps

(CSE_PCR) via a signal (CLKech) from a time base synchronized on all the devices connected to said network, and

- the means (INTE) to transmit a packet comprising the sample (PCR _e ) in the communications network.

The present invention relates to, according to a second aspect, a reception device able to receive packets in a packet communication network, said device comprising the means (REC) to receive packets from said network, said packets comprising the samples (PCR ₁ -), said samples (PCR ₁ -) coming from data sampled by a signal (CLKech) from a time base synchronized on all the devices connected to said network, the means (REC) extracting said samples (PCR ₁ -) from packets received. According to the invention the device also comprises:

- the means (LFVCO2) to produce from a comparison signal (SCOMP2) a signal (SRA) at frequency FRA,

- a counter (CPT_PCR2) cadenced by the signal (SRA), said counter (CPT_PCR2) produced by counting ramps (CSR_PCR2),

- the means (LATCH2) to realize the local samples (PCR_Loc) of ramps (CSR_PCR2) via the signal (CLKech), and

- the means (COMP2) to compare said samples (PCR ₁ -) with said local samples (PCR_Loc), said means of comparison (COMP2) delivering the comparison signal (SCOMP2),

- the means (DIVJ) to produce from the signal (SRA) and the counting ramps (CSR_PCR2), a signal (SRB) at frequency FRB such that FRB = FRA/J where J is an integer number,

- the means (LFVCO3) to produce from a signal (SCOMP3) a signal (SRC) at frequency FRC,

- the means (DIVK) to produce, from the signal (SRC), a signal (SRD) at frequency FRD so that FRD = FRC/K where K is an integer number,

- the means (COMP3) to compare the signal (SRD) with the signal (SRB), said comparison means (COMP3) delivering a comparison signal (SCOMP3),

- the means (EMS) to produce pulses (IMP2) at a frequency (FV) from the signal (SRC) and the signal (SRD),

- the means to reconstitute a synchronization signal from said pulses (IMP2) and the signal (SRD). The present invention relates to, according to a third aspect, a synchronization system comprising a transmission device as defined earlier and at least one reception device as described previously.

Advantageously, the frequency FRA of the signal SRA of the reception device or devices is identical to the frequency FB of the transmission device.

Advantageously, the frequency FRC of the reception device or devices is identical to the frequency FV of the pulses IMP1 of the transmission device.

According to an embodiment, the frequency FB of the transmission device of a synchronization system according to the invention is identical to the frequency FRA of the signal SRA of the reception device or devices.

Brief description of the drawings

The invention will be better understood from the following description of an embodiment of the invention provided as an example by referring to the annexed figures, wherein:

- figure 1 shows the transmission of genlock information between two cameras linked via an IP/Ethernet network,

- figure 2 shows the interfacing between the analogue domain and the IP/Ethernet network, - figure 3 shows the regeneration of the Genlock signal on the reception side according to the prior art,

- figure 4 diagrammatically shows a phase-locked loop architecture of a reception device according to the prior art,

- figure 5 shows the interfacing between the analogue domain and an IP/Ethernet network according to the invention,

- figure 6 shows the regeneration of the Genlock signal on the reception side according to the invention.

Detailed description of the embodiments of the invention The current analogue domain is interfaced with the IP/Ethernet network on the transmission side, and the IP/Ethernet network is interfaced with the analogue domain on the reception side, as illustrated in figure 1.

In the same figure, the transmission side comprises a "Genlock master" MGE that is connected to an IP/Analogue interface I AIP. The Genlock master MGE sends a Genlock signal SGO to the interfaces I AIP.

The reception side comprises two cameras (CAM1 , CAM2) each connected to an IP/Analogue interface IJPA. The interfaces MPA that will eventually be included in the cameras themselves are responsible for reconstructing the Genlock signals SG1 , SG2 intended for cameras CAM1 , CAM2. The cameras CAM1 , CAM2 each produce a video signal SV1 , SV2 that is required to be synchronised perfectly.

The transmission and reception sides are linked together by a packet switching network that is the source of a jitter occurring in the Genlock signal SGO.

A sampling clock, CLKech, with a T _ΘC h period, is generated from a first synchronisation layer, for example IEEE1588, and is sent to the transmission and reception sides. Indeed, the PTP protocol (Precision Time Protocol) based on IEEE1588 enables synchronisation to be obtained between the equipment connected on the Ethernet network to an order of microseconds. In other words, the time bases of each item of equipment progress at the same time with a precision close to the order of the microsecond. Each of these time bases can be used in this case to generate its own sampling clock CLKech with a period T _ΘC h- Use of the IEEE1588 layer is not a required route.

Any system capable of providing a sampling clock of period T _ΘC h on the various items of equipment connected on the network could be suitable. For example, a sampling clock with a period of 5ms from a wireless transmission physical layer can be used. Figure 2 details the processing of the Genlock signal SGO from MGE, within the interface I AIP. First, a module EXS extracts the synchronisation information from the signal SGO in order to recover a video timing clock (noted as CIk on figure 2). More specifically, the module EXS is responsible for the generation of a pulse (or "top") triggering each image start. In addition, the module EXS comprises an image counter, for example a 40 ms counter, which is not shown in Figure 2. The output of this image counter progresses according to the counting ramp, crossing 0 at each image start, that is, every 40 ms in the case of the image counter cited in the aforementioned example.

"Counting ramp" designates a stair-step signal. The steps have a unitary height. The "counting ramp range" is the term applied to the difference in level between the highest steps and the lowest steps.

For example the counting ramp range delivered by the image counter is equal to 40ms. F _ou t, where F _ou t is the frequency of the video clock CLK. The image counter successively delivers all of the integer values from 0 to 40 .

The timing video clock is used to determine the rhythm of a counter CPT_PCR. The output of the counter CPT_PCR is a counting ramp, CSE_PCR whose period is m image periods. Every "m" image, the counter CPT_PCR is reset, that is to say that the counting ramp CSE_PCR is reset to 0.

The counting ramp range delivered by the image counter is equal to m.40ms.Fout The counter CPT_PCR delivers successively all of the integer values from 0 to m.40 ms.F _0U t-1 ■

Next, a module LCH samples the counting ramp CSE_PCR at a rate provided by the sampling clock CLKech, that is to say with a period T _ΘC h and thus produces the samples PCR _e that are sent on the network and circulate via an interface the network (block INTE) to the reception side.

Figure 3 shows the reception side according to the prior art. The interface MPA recovers the PCR _e samples that have been sent on the network. These samples PCR _e are received by a network interface (module

INTR) with a delay linked to the transport between the transmission device and the reception device: the module INTR produces the samples PCR ₁ -. The samples PCR _e , which are produced at regular T _ΘC h intervals on the transmission side, arrive at irregular intervals on the reception side: this is largely due to the jitter introduced during transport on the network. The samples PCR _r are taken into account at regular T _ΘC h intervals and hence, the majority of the jitter introduced during packet transport is eliminated.

The imprecision between the transmission and reception sampling times is absorbed by a phase-locked loop PLI_i whose bandwidth is appropriated. The characteristics of the phase-locked loop PLI_i guarantee a reconstituted clock generation CLK_outi with a reduced jitter. The phase-locked loop PLI_i acts as a system receiving PCR _r samples and delivering:

- a reconstituted clock CLK_outi,

- a counting ramp CSR_PCRi and,

- local samples PCRJoci. When the loop PLI_i operates in a steady state, the samples PCR _r are noticeably equal to the samples PCRJoci.

The reconstituted clock CLK_outi determines the timing of a CPT image counter similar to the image counter on the transmission side, for example a 40 ms counter. The image counter CPT is reset each time the counting ramp CSR_PCRi crosses 0. Between two successive initialisations, the image counter CPT progresses freely and produces top image that supplies a local Genlock generator, GEG to produce a reconstructed Genlock signal SG1 , SG2 designed to synchronise the cameras CAM1 , CAM2.

The reconstructed Genlock signal SG1 , SG2 that is generated from the counting ramp CSR_PCRi and the reconstituted clock CLK_outi is in phase with the Genlock signal SGO on the transmission side, to the nearest clock pulse.

Figure 4 diagrammatically shows a PLI_i phase-locked loop architecture used in an IJPA interface according to the prior art. As shown in figure 4, the phase locking loop PLI_i comprises: - a sample comparator CMPi that compares the samples PCR _r and local samples delivering a comparison result of the samples , or an error signal ERR,

- a corrector COR ₁ receiving the signal ERR and delivering a corrected error signal ERC,

- a configurable oscillator VCO1 receiving the corrected error signal ERC and delivering a reconstituted clock CLK_outi, the clock CLK_outi has a frequency F _ou t that depends on the signal ERC,

- a counter CPT_PCRi that produces a counting ramp CSR_PCRi according to a rate that is printed by the reconstituted clock CLK_outi and having a rage of m.40 ms.F _0U t,

- a value maintenance system LATCHi that generates local samples PCRJ0C1 from the values of the counting ramp CSR_PCRi at the instants defined by the sampling clock CLK _ΘC h- Figure 5 shows in simplified form the different components constituting the transmission device I AIP according to the invention assuring the interface between the analogue domain and an IP/Ethernet network.

The device I AIP comprises the means EXS to extract clock signals CLK and pulses IMP1 at frequency FV, synchronous with signals CLK from a synchronization signal SGO.

To simplify the explanation, the frequency of the clock signal CLK is equal to 27MHz and the frequency FV is equal to 25 Hz. The device I AIP comprises:

- the means DIVP to produce, from the pulses IMP1 and clock signals CLK, a signal SA at frequency FA such that FA = FV/P where P is an integer number,

- the means LFVO1 to produce from a signal SCOMP1 a signal SB at frequency FB greater than FA, the means LFVO1 have a function similar to the blocks COR1 and VCO1, - the means DIVQ to produce, from the signal SB, a signal SC at frequency FC so that FC = FB/Q where Q is an integer number, - the means COMP1 to compare the signal SA with the signal SC, said means COMP1 delivering a comparison signal SCOMP1 ,

Signals for which the frequency has a value facilitating the calculations are selected. For example, a frequency value FA equal to one second is selected and the value 1 GHz is imposed for FB. This imposes P = 25 and Q

= 10 ⁹ in such a way that a comparison between the signal SA and the signal

SB is possible.

In an established regime, the signals SA and SB are both constituted of pulses at 1 Hz and are equal. From these selections, the period of the counting ramp CPT_PCT1 is defined, preferably in such a way that it is different than the period of pulses IMP1. To do this are used:

- a counter CPT_PCR1 whose rate is determined by the signal SB, at 1 GHz in the example. The counter CPT_PCR1 is initialized by a signal CLR and produces counting ramps CSE_PCR, of unitary steps,

- the means DIVR to produce, from the signal SC, a signal CLR at frequency FCLR so that FCLR = FC/R where R is an integer number. Following the previous example R defines in seconds the period of the counting ramp, for example R = 1001 , - the means LATCH1 to realize the samples PCR _e of ramps CSE_PCR via a signal CLKech from a time base synchronized on all the devices connected to said network, and

- the means INTE to transmit a packet comprising the sample PCR _e in the communications network. Figure 6 shows in a simplified way the different components constituting a reception device of an interface MPA according to the invention. As in the prior art, the reception device comprises the means REC to receive packets from the network. The packets comprise samples PCR _r from data sampled by a signal CLKech from a time base synchronized on all the devices connected to said network. The means REC extract the samples PCR _r from received packets. The device MPA comprises a first stage operating at the frequency FB. This first stage is constituted of:

- the means LFVCO2 to produce from a comparison signal SCOMP2 a signal SRA at frequency FRA, A frequency FRA equal to FB, or 1 GHz is selected for example,

- a counter CPT_PCR2 whose rate is determined by the signal SRA at frequency FRA. The counter CPT_PCR2 produces counting ramps (CSR_PCR2), and of a range determined as a function of m of FRB and FV. For example the range EXC of the counter is selected to be equal to m.FB/FV,

- the means LATCH2 to realize the local samples PCR_Loc of ramps CSR_PCR2 via the signal CLKech, and

- the means COMP2 to compare the samples PCR _r to local samples PCRJ-OC. The comparison means COMP2 deliver a comparison signal SCOMP2.

The device MPA also comprises the means DIVJ to produce from the signal SRA and the counting ramps CSR_PCR2, a signal SRB at frequency FRB such that FRB = FRA/J where J is an integer number, In particular the means DIVJ have their rate determined by the signal SRA and reset at each passage of the counting ramp CPT_PCR2 by a specific value PCR_REF comprised between 0 and ECC-1. The means DIJ deliver a synchronous pulse at the instant where the remainder of the division of CSR_PCR2 by J equals 0. For example J = 10 ⁹

- the means LFVCO3 to produce from a comparison signal SCOMP3 a signal SRC of period FRC equal to FV. For example FRC = 25Hz,

- the means DIVK to produce, from the signal SRC, a signal SRD at frequency FRD so that FRD = FRC/K where K is an integer number, For example K = 25, thus FRD equals 1 Hz and the comparison between SRB and SRD can be operated, - the means COMP3 to compare the signal SRD with the signal SRB, said comparison means COMP3 delivering a comparison signal SCOMP3. The device also comprises the means EMS to produce pulses IMP2 at a frequency FV from the signal SRC and the signal SRD. In particular the means EMS have their rates determined by the signal SRTD and the signal SRC constitutes a reset signal or a reset to 0. The device also comprises the means GEG to reconstruct a synchronization signal from the pulses IMP2 and the signal SRD.

The invention is described in the preceding text as an example. It is understood that those skilled in the art are capable of producing variants of the invention without leaving the scope of the patent.