BACKGROUND

[0001] The subject matter disclosed herein relates to semiconductor devices (e.g., semiconductor switches), and more specifically to estimating a junction temperature of a semiconductor switch. Semiconductor based systems may be used in a vast range of applications, including power electronics converters (e.g., for transportation equipment, construction equipment, mining equipment, oil and gas equipment, etc.), solar power converters, computing devices, variable frequency drives, electric cars, trains, refrigeration systems, HVAC systems (e.g., air conditioners), audio equipment (e.g., amplifiers, public address systems, etc.), and so forth. In such systems, the junction temperature of a semiconductor switch (e.g., an average temperature of an active semiconductor area) may be indicative of how the semiconductor switch is operating. However, direct measurement of the junction temperature (e.g., via optical measurement or direct contact measurement) may not be practical. For example, systems for directly measuring junction temperature may compromise the packaging of the semiconductor switch or increase the footprint of the packaging of the semiconductor switch.

BRIEF DESCRIPTION

[0002] Certain embodiments commensurate in scope with the original claims are summarized below. These embodiments are not intended to limit the scope of the claims, but rather these embodiments are intended only to provide a brief summary of possible forms of the claimed subject matter. Indeed, the claims may encompass a variety of forms that may be similar to or different from the embodiments set forth below.

[0003] In one embodiment, a system for estimating a junction temperature of a semiconductor switch assembly includes a gate drive unit electrically coupled to a control terminal of a semiconductor switch assembly and a reference terminal of the semiconductor switch assembly. The semiconductor switch assembly includes at least one semiconductor switch. The gate drive unit applies an input voltage across the control terminal and the reference terminal to turn the semiconductor switch on and off, initiates a timer at a start of a turn on event, a turn off event, or both, stops the timer upon an occurrence of a specified event, logs an elapsed time between when the timer is initiated and when the timer is stopped, and estimates the junction temperature of the semiconductor switch based on the elapsed time.

[0004] In a second embodiment, a system for estimating a junction temperature of a semiconductor switch includes a semiconductor switch and a gate drive unit. The semiconductor switch includes a control terminal and a reference terminal. The gate drive unit is electrically coupled to the control terminal of the semiconductor switch and the reference terminal of the semiconductor switch. The gate drive unit applies an input voltage across the control terminal and the reference terminal to turn the semiconductor switch on and off, initiates a timer at a start of a turn on event, a turn off event, or both, stops the timer upon an occurrence of a specified event, logs an elapsed time between when the timer is initiated and when the timer is stopped, and estimates the junction temperature of the semiconductor switch based on the elapsed time.

[0005] In a third embodiment, a method of estimating a junction temperature of a semiconductor switch includes applying an input voltage across the control terminal and the reference terminal to turn the semiconductor switch on and off, initiating a timer at a start of a turn on event, a turn off event, or both, stopping the timer upon an occurrence of a specified event, logging an elapsed time between when the timer is initiated and when the timer is stopped, and estimating the junction temperature of the semiconductor switch based on the elapsed time.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

[0007] FIG. 1 is a schematic of an embodiment of a propulsion system, in accordance with an embodiment;

[0008] FIG. 2 is a detail view of an embodiment of an inverter and a motor of the propulsion system of FIG. 1, taken within line 2-2, in accordance with an embodiment;

[0009] FIG. 3 is a schematic of a semiconductor based system having one or more semiconductor switches and a gate driver, in accordance with an embodiment;

[0010] FIG. 4A is a detail view of the schematic of a semiconductor switch of the semiconductor based system of FIG. 3, wherein the semiconductor switch is an insulated gate bipolar transistors (IGBT) with an antiparallel diode, in accordance with an embodiment;

[0011] FIG. 4B is a detail view of the schematic of the semiconductor switch of FIG. 3, wherein the semiconductor switch is an IGBT with a sensing collector terminal, illustrating the effect of parasitic inductance, in accordance with an embodiment;

[0012] FIG. 4C is a schematic a detail view of the schematic of the semiconductor switch of FIG. 3, wherein the semiconductor switch is a MOSFET, in accordance with an embodiment;

[0013] FIG. 4D is a schematic detail view of the semiconductor system of FIG. 3 having a semiconductor switch assembly with multiple semiconductor switches 12;

[0014] FIG. 5 is a graph of a gate-emitter voltage, VGE synchronized with, and disposed above a graph of a current running through the semiconductor device, ICE , and a voltage across the semiconductor device, VCE·, during an on-off cycle of the semiconductor device, in accordance with an embodiment; [0015] FIG. 6 is a schematic of an embodiment of the semiconductor based system of FIG. 3 in which junction temperature, 7), is estimated based on gate-emitter voltage, VGE and device current, ICE , in accordance with an embodiment;

[0016] FIG. 7 is a schematic of an embodiment of the semiconductor based system of FIG. 3 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VCE·, device current, ICE , and device voltage, VCE·, in accordance with an embodiment;

[0017] FIG. 8 is a flow chart of a process for estimating junction temperature, 7 _/ , of a semiconductor device based upon gate-emitter voltage, VCE·, sampled upon the expiration of a timer, in accordance with an embodiment;

[0018] FIG. 9 shows the graphs of the gate-emitter voltage, VCE·, device current, ICE , and device voltage, VCE·, during an on-off cycle of FIG. 5, and times at which gate-emitter voltage, VGE’ may be sampled based on the device saturation, in accordance with an embodiment;

[0019] FIG. 10 is a schematic of an embodiment of the semiconductor based system of FIG. 3 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE sampled based on the device saturation, in accordance with an embodiment;

[0020] FIG. 11 is a schematic of an embodiment of the semiconductor based system of FIG. 10 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VCE·, device current, ICE , and device voltage, VCE·, sampled based on the device saturation, in accordance with an embodiment;

[0021] FIG. 12 is a flow chart of a process for estimating junction temperature, 7 _/ , of a semiconductor device based upon gate-emitter voltage, VCE·, sampled when the device enters and/or exits saturation, in accordance with an embodiment;

[0022] FIG. 13 shows the graphs of the gate-emitter voltage, VCE·, device current, ICE , and device voltage, VCE·, during an on-off cycle of FIG. 5, and the time at which gate- emitter voltage, VGE· may be sampled when current begins to flow through the semiconductor device, in accordance with an embodiment;

[0023] FIG. 14 is a schematic of an embodiment of the semiconductor based system of FIG. 3 in which junction temperature, 7), is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor device, in accordance with an embodiment;

[0024] FIG. 15 is a schematic of an embodiment of the semiconductor based system of FIG. 14 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor device, and the device voltage, VCE·, in accordance with an embodiment;

[0025] FIG. 16 is a schematic of an embodiment of the semiconductor based system of FIG. 14 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor device, in accordance with an embodiment;

[0026] FIG. 17 is a schematic of an embodiment of the semiconductor based system of FIG. 14 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor device, and the device voltage, VCE, in accordance with an embodiment;

[0027] FIG. 18 is a flow chart of a process for estimating junction temperature, 7/, of a semiconductor device based upon gate-emitter voltage, VGE·, sampled when current starts flowing through the semiconductor device, in accordance with an embodiment;

[0028] FIG. 19 shows the graphs of the gate-emitter voltage, VGE·, device current, ICE , and device voltage, VCE·, during an on-off cycle of FIG. 9, and the times at which the device enters and exits saturation, in accordance with an embodiment; [0029] FIG. 20 is a schematic of an embodiment of the semiconductor based system of FIG. 10 in which junction temperature, Tj, is estimated based on time to device saturation and/or desaturation, in accordance with an embodiment;

[0030] FIG. 21 is a schematic of an embodiment of the semiconductor based system of FIG. 11 in which junction temperature, Tj, is estimated based on time to device saturation and/or desaturation, device current, ICE , and device voltage, VCE\ sampled when the device is in an off state, in accordance with an embodiment;

[0031] FIG. 22 is a flow chart of a process for estimating junction temperature, Tj, of a semiconductor device based upon time to device saturation and/or desaturation, in accordance with an embodiment;

[0032] FIG. 23 shows the graphs of the gate-emitter voltage, VGE\ device current, ICE , and device voltage, VCE\ during an on-off cycle of FIG. 13, and the time at which current begins to flow through the semiconductor device, in accordance with an embodiment;

[0033] FIG. 24 is a schematic of an embodiment of the semiconductor based system of FIG. 14 in which junction temperature, Tj, is estimated based on time for current to flow through the semiconductor device, in accordance with an embodiment;

[0034] FIG. 25 is a schematic of an embodiment of the semiconductor based system of FIG. 24 in which junction temperature, Tj, is estimated based on time for current to flow through the semiconductor device, and device voltage, VCE, during an off state, in accordance with an embodiment;

[0035] FIG. 26 is a schematic of an embodiment of the semiconductor based system of FIG. 16 in which junction temperature, Tj, is estimated based on time for current to flow through the semiconductor device, in accordance with an embodiment;

[0036] FIG. 27 is a schematic of an embodiment of the semiconductor based system of FIG. 24 in which junction temperature, Tj, is estimated based on time for current to flow through the semiconductor device, and device voltage, VCE, during an off state, in accordance with an embodiment; and

[0037] FIG. 28 is a flow chart of a process for estimating junction temperature, Tj, of a semiconductor device based upon time for current to start flowing through the device, in accordance with an embodiment.

DETAILED DESCRIPTION

[0038] One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers’ specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0039] When introducing elements of various embodiments of the present disclosure, the articles“a,”“an,”“the,” and“said” are intended to mean that there are one or more of the elements. The terms“comprising,”“including,” and“having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Furthermore, any numerical examples in the following discussion are intended to be non limiting, and thus additional numerical values, ranges, and percentages are within the scope of the disclosed embodiments.

[0040] FIG. 1 is a schematic of an embodiment of a propulsion system 1. In the propulsion system, an engine (e.g., a diesel engine 2) converts a fuel (e.g., diesel fuel) into mechanical energy. For example, the diesel engine 2 may rotate a drive shaft. An alternator 3 receives the mechanical power (e.g., via the drive shaft) and converts the mechanical power to AC electrical power (e.g., 3-phase AC power). A rectifier 4 converts the AC electrical power into DC electrical power. For example, the rectifier may output DC electrical power via a DC bus 5. The tension of the DC bus is regulated via the alternator’s 3 excitation field. One or more inverters 6 may be electrically coupled to the DC bus 5. The inverters 6 each independently control a motor 7 (e.g., induction motor) via a 3 -phase power signal output to each respective motor 7.

[0041] FIG. 2 is a detail view of an embodiment of the inverter 6 and motor 7 of FIG. 1, within line 2-2. As shown, the inverter 6 includes an array of semiconductor switches 8. In the illustrated embodiment, the semiconductor switches 8 all represent insulated gate bipolar transistors (IGBTs) with separate antiparallel diodes. However, in other embodiments, the semiconductor switches may also include metal oxide semiconductor field effect transistors (MOSFETs), silicon carbide (SiC) semiconductors, any other semiconductor device controlled by a voltage applied to a gate terminal, or combinations thereof. Switches with diodes embedded in the main junction of the device, such as body diodes in MOSFETs are also encompassed. As illustrated, the inverter 6 includes six pair of semiconductor switches in parallel with one another, each pair outputting a phase to the motor 7. As such, the inverter is said to have three phase legs, one leg for each phase, each leg having two IGBTs (e.g., a positive and a negative). It should be understood, however, that the architecture shown in FIG. 2 may be scaled up or down dependent upon the number of phases of the signal and current to be supplied.

[0042] FIG. 3 is a schematic of a semiconductor based system 10 having one or more semiconductor devices (e.g., semiconductor switches 12) and a gate driver 14. The gate driver 14 is an electronic circuit interfacing the logical signal outputs of a main converter controller and the command inputs of the semiconductor switch. The gate driver 14 receives external commands, in embodiment shown in FIG. 3 from a pair of fiber optic transceivers, and produces voltage and current signals of the levels to turn on and off the switch, letting current flow through the main power terminals (52 and 54 in FIG. 4A) unobstructed when on, and preventing current flow when off. The gate driver may be mounted in close proximity of the semiconductor switch, or it may be mounted remotely and connected through cables, harnesses, flat-wires or other means to the semiconductor. As will be described in more detail below, the semiconductor switch may be a single semiconductor switch (e.g., one or the semiconductor switches 8 of FIG. 2) or a group of semiconductor switches (e.g., all of or a portion of the inverter 6 of FIG. 2). The semiconductor based system 10 may be used in vast range of applications, such as the propulsion system on FIG. 1. In other embodiments, the semiconductor based system 1- may be utilized in power electronics converters (e.g., for transportation equipment, construction equipment, mining equipment, oil and gas equipment, etc.), solar power converters, computing devices, variable frequency drives, electric cars, trains, refrigeration systems, HVAC systems (e.g., air conditioners), audio equipment (e.g., amplifiers, public address systems, etc.), and so forth. In the present embodiment, the semiconductor switch 12 may be one or more IGBTs, one or more MOSFETs, one or more silicon carbide (SiC) semiconductors, or one or more of any other semiconductor device. It should be understood, however, that various levels of integration may be possible. Accordingly, one IGBT may mean one IGBT module, meaning the encapsulation of one or several IGBT chips interconnected inside with a few external terminals for the user. The packaging defines whether IGBT, MOSFET, with antiparallel diodes or with intrinsic diodes, dual switches, switches with control electronics integrated, etc. Each of the one or more semiconductor switches 12, should operate below a maximum junction temperature, 7}·, max, to ensure for a sufficiently long life (usually many years) of operation. Operating above the maximum junction temperature, Tj, _ma x, may cause immediate damage to the semiconductor switches 12, or to slow degradation of the semiconductor switches 12 inside the module 10 or the interconnecting elements inside the module. Because the modules are typically large area devices, there is not a unique temperature associated to the module in operation, but an entire temperature field. However, it may be beneficial to bound the temperature field within an interval so that all parts of the switch behave approximately uniformly. It is then useful to attribute a single ” junction temperature” to the semiconductor as an average temperature across the active semiconductor area, where the area refers to the semiconductor being an extensive body. Averaging the temperature can be conducted in several ways, as a geometrical surface area, or as an electrical averaging (e.g., a compound scalar electrical signal, which is designated as temperature). Further, the junction temperature, 7), may provide useful information about the state of the semiconductor switch 12. However, direct measurement of the junction temperature, 7/, (e.g., via optical measurement or direct contact measurement) may compromise the integrity of the device packaging and/or greatly expand the footprint of the packaging. However, sampled electrical parameters, when used in combination with experimental models or lookup tables, may be used to estimate the junction temperature, 7}, of the one or more semiconductor switches 12 of the semiconductor based system 10.

[0043] As illustrated, the gate driver 14 includes an electronic control unit (ECU) 16, such as a field programmable gate array (FPGA), a microcontroller, or other processing device with or without a memory component, a digital signal processor (DSP), etc. The ECU 16 provides a control signal to gate driving circuitry 18. Based on the control signal received from the ECU 16, the gate driving circuitry 18 applies a voltage (e.g., gate-emitter voltage, VGE’) across a control terminal 20 and a reference terminal 22 of the semiconductor switch 12. Reference terminals are usually the control terminals of the semiconductor switch or module, as opposed to the power terminals used to lead the load currents. A signal conditioner 24 samples the gate-emitter voltage, VGE at a set frequency and conditions the raw signal, for example by applying one or more filters. An analog to digital converter (ADC) 26 converts the conditioned signal from an analog signal to a digital signal and provides the conditioned digital signal to the ECU 16.

[0044] As illustrated, the ECU 16 includes a timer 28. The timer is triggered by a state machine 30 upon reception of an external command input (illustrated), which also generates the control signal output to the gate driving circuitry 18. When the timer 28 expires, the gate-emitter voltage, VGE is sampled from the conditioned digital signal received from the ADC 26. One or more models and/or lookup tables 32 are then referenced to estimate the junction temperature, 7). The translation of sampled voltage to average temperature is based on previous one-time characterization under controlled conditions of the type of semiconductor used. Basically, VGE’ is a function of 7}. In some cases it may be possible to exactly calibrate the lookup table for the pair semiconductor- ECU at assembly time. This gives the best possible accuracy in the temperature estimates. The ECU 16 may then take the junction temperature, 7} into consideration when controlling the semiconductor switch. For example, if the junction temperature, 7} exceeds the specified maximum junction temperature, 7), _max , or exceeds an expected junction temperature, 7} at a given time, the ECU 16 may shutdown the semiconductor switch 12 or prevent it from operating.

[0045] FIGS. 4A-4D illustrate several different embodiments of the semiconductor switch 12 of FIG. 3. It should be understood, however that the embodiments shown in FIGS. 4A-4D are merely a few of many possible envisaged embodiments, and thus are not intended to be limiting. FIG. 4A is a detail view of the schematic of the semiconductor switch 12 of FIG. 3. In this embodiment, the semiconductor switch 12 is a single IGBT. However, other embodiments may include multiple semiconductor switches. For example, the semiconductor switch 12 may include the inverter from FIG. 2, a leg of the inverter from FIG. 2, or some other combination of switches. Further, as previously described, in other embodiments, the semiconductor switch may also be one or more MOSFETs, one or more SiC semiconductors, or one or more of some other fast-switching semiconductor switch. The IGBT 12 includes four alternating doped layers (e.g., P-N-P-N), which are controlled by a metal oxide semiconductor (MOS) gate structure. The IGBT can be seen as a bipolar PNP transistor controlled by a MOSFET. When the IGBT conducts (UCE > 0, VGE > Uth), instead of a unipolar current, as in the MOSFET, there is mixed unipolar and bipolar current, because the first P-N junction is polarized and injects holes into the n-base. Together with the electrons of the MOSFET channel, these holes build a diffusion zone in the N base, which increases the carrier concentration and reduces the conduction losses as compared to the MOSFET (conductivity modulation). At turn-off of the IGBT, the diffusion zone of the n-base is depleted via extraction and recombination. Extraction takes place during the voltage build up phase when the space charge zone extends in the n- base. Due to the relatively fast switching speed of the IGBT 12, complex waveforms may be synthesized via pulse-width modulation and/or low pass filters. As shown, the IGBT 12 includes a gate terminal 50 as the control terminal 20, a collector terminal 52, an emitter terminal 54, which may include a sensing emitter terminal, and a reference emitter terminal 56 as the reference terminal 22. As previously described, the control terminal (e.g., the gate terminal 50) controls the device 12. When the device is on (e.g., a positive voltage is applied across the gate terminal 50 and the reference emitter terminal 56), current can flow from the collector terminal 52 to the emitter terminal 54 partly determined by the applied voltage difference and partly by the external circuit. When device is off (e.g., a negative voltage is applied across the gate terminal 50 and the reference emitter terminal 56), no current flows through the device 12. The high voltage capability, low resistance when the device is on, and relatively fast switching speed make IGBTs suitable for pulse-width modulation, variable speed control, switch-mode power supplies, solar powered devices, DC-AC converters, frequency converters, etc. The static output characteristic of the IGBT is similar to that of the MOSFET, with the main difference in the existence of a threshold region, i.e. the I _C /UCE characteristic starts at about Eke = 0.6 (for Silicon IGBTs) with a typical diode behavior, whereas the ID/UDS characteristic of a MOSFET is linear and starts at the origin. During the switching transients for both IGBTs and MOSFET s, the quasi- stationary current is a consequence of the MOSFET pinch-off behavior and is given by:

Where k is a parameter that depends on the geometric and material properties of the MOSFET , and Uth is the threshold voltage which is a strong function of the temperature. The current to voltage slope is defined as: [0046] FIG. 4B is a schematic a detail view of the schematic of the semiconductor switch 12 of FIG. 3, wherein the semiconductor switch 12 is an IGBT with a sensing collector terminal C’ . Under blocking conditions, or in general when no current flows from C to E, the voltage across the sensed or reference terminals VC E’ is equal to the voltage across the power terminals VCE. During transient conditions, while current builds up or falls down, there may be a difference between those two voltages mainly caused by the parasitic inductive elements inside the package, or due to mutual coupling across different current traces. In the illustrated embodiment, the schematic depicts a parasitic module inductance, L _ee and a sensing collector terminal 58 C’ for measuring the voltage across the semiconductor switch (i.e., the voltage across the sensing collector terminal 58 and the reference emitter terminal 56.

[0047] FIG. 4C is a schematic detail view of the schematic of the semiconductor switch 12 of FIG. 3, wherein the semiconductor switch is an n-channel MOSFET. The first terminal 20 corresponds to a gate terminal 60, and the reference terminal corresponds to a source terminal 62. The MOSFET also includes a drain terminal 64.

[0048] FIG. 4D is a schematic detail view of the semiconductor system 10 of FIG. 3 that includes a semiconductor switch assembly 80 having multiple semiconductor switches 12. As shown, the semiconductor switch assembly 80 includes a plurality (e.g., n-number) of semiconductor switches 12. Each semiconductor switch 12 is coupled to a respective interface board 82 (e.g., a high voltage board). As shown, the various semiconductor switches 12 and respective interface boards 82 are disposed parallel to one another. The term“high voltage” is suitable here especially when these embodiments are used with high blocking voltage semiconductors (e.g. 600V, 1200V, 1700V, 2500V, 3300V or more). These interface boards can be mounted directly on top of the free surfaces of the semiconductors, and scaled down signals sent to the low voltage electronics. As shown, the semiconductor switch assembly 80 is coupled to the gate driver via a control terminal 20 (e.g., first terminal 84), and a reference terminal 22 (e.g., second terminal 86). In some embodiments, voltages may be sampled at the C terminals (e.g., Ci, C2, C3. . . CN, etc.) to determine the gate-emitter voltage, VCE·, or each semiconductor switch 12.

[0049] For simplicity, many of the embodiments shown and described herein include a single IGBT as the semiconductor switch 12. However, it should be understood that in any of the illustrated embodiments, a single IGBT may be replaced with one or more MOSFETs, one or more SiC semiconductor switches, or any combination thereof. The semiconductor switch 12 operates in a non-degrading fashion if it is below a specified maximum junction temperature, Tj,max. . Direct measurement of the junction temperature, Tj, (e.g., via optical measurement or direct contact measurement) may not be practical (e.g., direct measurement of the junction temperature, Tj, may compromise the integrity of the device packaging and/or greatly expand the footprint of the packaging or may be representative of a local point and not a wide area average). However, sampled electrical parameters, when used in combination with experimental models or lookup tables, may be indicative of a junction temperature, Tj, which provides useful information about the state of the semiconductor switch 12.

[0050] FIG. 5 is a graph 100 of the gate-emitter voltage, VGE\ synchronized with, and disposed above a graph 102 of the current flowing through the IGBT, ICE , and the voltage across the device, VCE·, during an on-off-on cycle of the IGBT. In each graph 100, 102, the horizontal axes 104, 106 represent time. In the first graph 100, the vertical axis 108 represents voltage, while in the second graph 102, the vertical axis represents voltage or current. The scales of the horizontal axes 104, 106 of the respective graphs 100, 102 are the same, however, the scales for the vertical axes 108, 110 are quite different. For example, the IGBT may switch from on to off and back to on again over the span of microseconds (ps), milliseconds (ms), or seconds (s). In the illustrated embodiment, the gate-emitter voltage, VGE\ ranges from +15 volts to -15 volts. However, the device voltage, VCE·, may reach up to 1,000 volts or more and the device current, ICE , may reach up to 100 amperes or more. In the first graph 100, the gate-emitter voltage, VCE·, is represented by a line 112. In the second graph 102, the device current, ICE , is represented by a first line 114 and the device voltage, VCE is represented by a second line 116.

[0051] As shown, during an on phase 118, the gate-emitter voltage, VGE is stable at an on gate-emitter voltage, VGE’.ON (e.g., +15 volts), the device current, ICE , is constant at an on device current, ICE, ON, and the device voltage, VCE·, is constant at approximately zero. The IGBT works in saturation, the parasitic heat losses are minimal too. This is usually the desired quasi-stationarity operating condition of semiconductors operated as switches and not as gate-voltage controlled elements in the so called“active” region. At a first point in time 120, the IGBT enters a turn-off phase 122 and the gate-emitter voltage, VGE begins to fall from the on gate-emitter voltage, VGEON (e.g., +15 volts) to an off gate-emitter voltage, VGE’.OFF (e.g., -15 volts). However, the gate-emitter voltage, VGE does not transition from the on gate-emitter voltage, VGEON to the off gate-emitter voltage, VGE’.OFF , linearly. Instead, the gate-emitter voltage, VGE falls, plateaus, and then falls again. The plateau is referred to as a Miller plateau. This plateau will be further explained below with reference to the turn on event where a similar plateau occurs. As the gate-emitter voltage, VGE falls and plateaus, the device voltage, VCE·, increases slowly first. However, when the gate-emitter voltage, VGE continues to fall, the device voltage, VCE·, quickly increases to a peak voltage and then falls slightly before reaching steady state. The sudden voltage increase is called the IGBT desaturation and takes place as the drift layer of IGBT is emptied of carriers and the IGBT (or MOSFET) enters the linear region before reaching the blocking state in the off interval. The device current, ICE , remains relatively constant during the initial parts of the turn off period and the Miller plateau, because the current is imposed by the external loads and as long as the device forward drop is below the external link voltage. However, as the gate-emitter voltage, VGE decreases below the threshold voltage (of the MOSFET part of the IGBT), the device current, ICE , falls to zero with a possible tail current present while recombination of minority carriers in the drift region takes place (in the case of the IGBT). At a second point in time 124 the device enters an off phase 126. During the off phase 126, the gate-emitter voltage, VGE is stable at an off gate-emitter voltage, VGE’.OFF (e.g., -15 volts), the device current, ICE , is constant at approximately zero, and the device voltage, VCE·, is possibly constant at an off device voltage, VCE’.OFF determined by the external circuit. Often this voltage equals the DC-link voltage from where the voltage source converter is fed.

[0052] At a third point in time 128, the IGBT enters a turn-on phase 130 and the gate- emitter voltage, VGE’, begins to climb from the off gate-emitter voltage, VGEOFF (e.g·, -15 volts) to the on gate-emitter voltage, VGE’.ON (e.g., +15 volts). As with the turn off phase 122, during the turn on phase 130, the gate-emitter voltage, VGE does not transition from the off gate-emitter voltage, VGEOFF to the on gate-emitter voltage, VGE ON, linearly. Instead, the gate-emitter voltage, VGE climbs as determined by the parasitic capacitances of the switch, reaches a peak (if the commutation is taking place from a diode which is reverse recovering), falls briefly (once the diode reverse recovery extinguishes), plateaus, and then climbs again toward the on gate-emitter voltage, VGE’.ON (e.g., +15 volts). The plateau is referred to as a Miller plateau. The value of the Miller voltage is approximately that of the MOSFET internal V _gs (gate source) voltage, required by the I _c ,sat equation (1) of paragraph 44 to sustain the externally imposed load current Ice, as represented by the equation:

[0053] It can be seen that this voltage depends on temperature through Uth and gm,sat in a complex way, and on the flowing current as well. The VGE’ voltage externally measured may differ due to resistive and inductive voltage drops, which appear when gate current flows. As the gate-emitter voltage, VGE climbs, the device voltage, VCE holds steady and then begin to fall as the gate-emitter voltage, VGE·, approaches the on gate-emitter voltage, VGE’.ON. The device voltage, VCE then quickly decreases to approximately zero. The device saturates. At the beginning of the turn on event, the device current, ICE , remains relatively constant at zero as the gate-emitter voltage, VGE increases but is below the threshold voltage 142. As the gate-emitter voltage, VGE approaches the on gate-emitter voltage, VGE’.ON , the device current, ICE , climbs, peaks (when commuting from a diode with reverse recovery), decreases slightly, and then settles at a steady state on device current, ICE, ON. In some cases, there may be oscillations in currents and voltages due to the interaction of parasitic inductances and typically switch parasitic capacitances, which are not shown. At a fourth point in time 132 the device enters another on phase 134. During the on phase 134, the gate-emitter voltage, VGE is stable at the on gate-emitter voltage, VGE’.ON (e.g., +15 volts), the device current, ICE , is constant at an on device current, ICE, ON, and the device voltage, VCE is constant at approximately zero. Though the graphs 100, 102 of FIG. 3 show a single on-off-on cycle, it should be understood that in operation, the semiconductor switch goes through many repeated cycles.

[0054] Monitoring the junction temperature, 7}, of the one or more semiconductor switches during operation may help to achieve efficient operation of the semiconductor switch. For example, monitoring the junction temperature, 7}, over time during the operation of the semiconductor switch may help provide an indication of how the device is operating. Further, monitoring the junction temperature, 7}, during operation will help keep track of whether semiconductor switch is operating below a specified maximum junction temperature, Tj.max , and allow the device to go into a different mode of operation if the maximum junction temperature, Tj.max, is exceeded. However, direct measurement of the junction temperature, 7}, of a semiconductor switch is not presently practical. That is, direct measurement of the junction temperature, 7/, (e.g., via optical measurement or direct contact measurement) may compromise the integrity of the device packaging and/or greatly expand the footprint of the packaging. However, sampled electrical parameters, when used in combination with experimental models or lookup tables, may be used to estimate the junction temperature, 7}, of the one or more semiconductor switches of the semiconductor based system.

[0055] As described above with regard to FIG. 3, the ECU 16 of the semiconductor system 10 may include one or more timers 28. Upon expiration of the one or more timers, the ECU 16 may sample the gate-emitter voltage, VGE of the one or more semiconductor switches 12. By synchronizing the timer 28 with the known frequency of the on-off cycle of the semiconductor switch 12, the point in time of the on-off cycle at which the gate- emitter voltage, VGE is sampled is known. The gate-emitter voltage, VGE samples may be logged over multiple cycles and the junction temperature, 7), may be estimated based on the sampled gate-emitter voltage, VGE using a lookup table or model. The one or more timers 28 may be setup to expire, triggering a sample of the gate-emitter voltage, VGE at known points in the device’s 12 on-off cycle. For example, the timer 28 may be set to expire at a point 136 during the Miller plateau during the turn-off phase 122 or at a point 138 during the Miller plateau during the turn-on phase 130. The duration of the Miller plateau depends on intrinsic capacitances and the rate of charge or discharge of the gate as supplied by the gate driver. Practice shows that it is possible to find a time point which is guaranteed to be inside the Miller plateau irrespective of temperature, voltage and operating current. In other embodiments, the timer 28 may be configured to expire, triggering a sample of the gate-emitter voltage, VGE at a point 142 when the gate-emitter voltage, VGE reaches a threshold value at which the device current, ICE , begins to flow.

[0056] FIG. 6 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 1 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE’, (e.g., the voltage across the control terminal 20 and the reference terminal 22), and device current, ICE. In many respects, the system 10 of FIG. 6 is very similar to the system 10 of FIG. 3, except that when the timer 28 expires, the gate-emitter voltage, VGE is sampled and retained, and the device current, ICE during an on phase of the semiconductor switch is estimated. Alternatively, the estimate ICE during a transient can be used. The device current, ICE , 148 and the sampled gate-emitter voltage, VGE are then used as inputs to the look up table or model 32 to derive the junction temperature, 7}. Use of the device current, ICE , 148 may further refine the estimation of the junction temperature, 7}, based on the following equation: j, V ge_Miller V xa ₂ I ^{c a} 1 ^a o

Ixb ₁ +b ₀ (4)

[0057] FIG. 7 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 3 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VCE·, device current, ICE , during an on state or a switching transient, and device voltage, VCE’, during an off state. As illustrated, the system 10 includes a voltage divider 150, which is electrically coupled to a sensing collector terminal 58 and the reference emitter terminal 56 of the semiconductor switch 12. The voltage divider 150 is used to sample the device voltage, VCE· (i.e., the voltage across the collector 52 and reference emitter 56) during the off state and outputs a reduced amplitude of the raw device voltage, VCE·, signal. As suggested by the figure (e.g. element 150), elements of the system may be arranged at different physical locations. For example, most of the low voltage, signal processing and other components of the ECU may reside on a printed circuit board positioned at a certain distance from the main semiconductor switch, whereas the high voltage interfaces, signal conditioners, and the like, may be assembled on an interface adapter board (e.g., high voltage board). The term “high voltage” is suitable here especially when these embodiments are used with high blocking voltage semiconductors (e.g. 600V, 1200V, 1700V, 2500V, 3300V or more). These interface boards can be mounted directly on top of the free surfaces of the semiconductors, and scaled down signals sent to the low voltage electronics. In some embodiments, the system 10 includes an additional signal conditioner 24 through which the device voltage, VCE· mm before going through the analog to digital converter 26 and being input to the ECU 16. In other embodiments, the device voltage, VCE·, signal may be conditioned by the same signal conditioner 24 as the gate-emitter voltage, VCE·, or may not be conditioned at all. In the illustrated embodiment, upon expiration of the timer 28, the gate-emitter voltage, VCE·, device current, ICE , during an on state, and device voltage, VCE·, are used as inputs to the table or model 32 to estimate the junction temperature, 7}.

[0058] FIG. 8 is a flow chart of a process 200 for estimating junction temperature, 7}, of a semiconductor switch based upon gate-emitter voltage, VCE·, sampled upon the expiration of the timer. At block 202, a turn on or turn off of the semiconductor switch is initiated. As discussed above, the semiconductor switch may run for a period of time (e.g., 20-30 seconds or more) to warm up before junction temperature, 7), may be estimated based on the sampled gate-emitter voltage, VCE·. At block 204, the timer is initiated. Upon expiration of the timer (block 206), the gate-emitter voltage, VCE·, is sampled. As discussed above with regard to FIG. 5, the timer may be set to expire at a certain point or region of the on-off cycle of the semiconductor switch. For example, the timer may be set to expire during the turn-on Miller plateau, the turn-off Miller plateau, and/or at a point in the on/off cycle when the gate-emitter voltage, VCE·, reaches a threshold value. In some embodiments, other values, such as device current, ICE , during an on state or a switching transient, and/or device voltage, VCE·, during an off state, may be sampled or estimated in addition to the gate-emitter voltage, VCE·. At block 208, the sampled values are logged. At block 210, the junction temperature, 7}, is estimated based on the sampled or estimated values. Specifically, the sampled or estimated values (e.g., emitter voltage, VCE·, device current, ICE , and/or device voltage, VCE·) may be inputs for a look-up table or model that estimates junction temperature, 7}, based on the input values. The look-up table or model could be based on theoretical and/or empirical characterization data obtained during controlled experiments. The process 200 returns to block 202 and initiates turn on or turn off of the switch.

[0059] FIG. 9 shows the graphs 100, 102 of the gate-emitter voltage, VCE·, device current, ICE , and device voltage, VCE·, during an on-off cycle of FIG. 3, and times at which gate-emitter voltage, VCE· may be sampled based on the device saturation. Rather than sampling the gate-emitter voltage, VCE·, upon the expiration of a timer, in some embodiments, the gate-emitter voltage, VCE· may be sampled or estimated when the device enters or exits saturation. For example, the ECU may monitor the device voltage, VCE·, during operation of the semiconductor switch. During the turn-off phase 122, the device voltage, VCE·, begins at or near zero, and then, at a first point in time 250, begins to increase as the device exits saturation, as indicated by circle 252. The ECU may recognize that the device has exited saturation and samples the gate-emitter voltage, VCE· (indicated by circle 254). This can be done with the help of a fast comparator. Similarly, during the turn-on phase 130, the device voltage, VCE begins at an off device voltage, VCE’.OFF , and then, begins to fall to zero. At a second point in time 256 the device enters saturation, for example with the help of a comparator, as indicated by circle 258. The ECU may recognize that the device has entered saturation and samples the gate-emitter voltage, VGE’ (indicated by circle 260). As with the embodiments described above, other values (e.g., device current, ICE , in an on state and device voltage, VCE in an off state) may also be sampled or estimated. The gate-emitter voltage, VGE’ and other sampled values may then be logged and input to a model or lookup table to estimate junction temperature, 7).

[0060] FIG. 10 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 3 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE’, sampled based on the device saturation. The device voltage, VCE signal is sampled and passed through a decoupling circuit 300 to the signal conditioner 24. The decoupling circuit 300 isolates the low voltage electronics of the gate driver 14 from the high voltages that can be present at the terminals of the semiconductor switch 12 when the switch is in an off state. The decoupling circuit 300 may include, for example, a clamp circuit, a MOSFET, etc. The signal conditioner 24 conditions the signal by applying one or more filters. The conditioned signal is then output to a saturation detection circuit 302, which determines when the device voltage, VCE·, enters and/or exits saturation. For example, the saturation circuit 302 may send a notification signal to the ECU 16 when the device enters and/or exits saturation. The saturation state of the device is output to the ECU 16. The ECU 16 samples the gate-emitter voltage, VGE when the device enters and/or exits saturation (e.g., as determined by the saturation detection circuit 302). The sampled gate- emitter voltage, VGE’, and in some cases an estimation of the device current, ICE , during an on state are logged and input to the look up table or model 32 to estimate the junction temperature, 7}.

[0061] FIG. 11 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 10 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE’, sampled based on the device saturation, device current, ICE , during an on state, and device voltage, VCE·, during an off state. As shown, the system 10 includes the voltage divider 150, which is electrically coupled to the sensing collector terminal 58 and the reference emitter terminal 56, to sample the device voltage, VCE·. AS discussed above, the voltage divider 150 samples the device voltage, VCE· (i.e., the voltage across the sensing collector and reference emitter terminals) and outputs a reduced value of the device voltage, VCE·. Though the decoupling circuit 300 and the voltage divider 150 are shown in FIG. 11 as part of the gate driver 14, in some embodiments, the decoupling circuit 300 and the voltage divider 150 may be mounted remotely from the semiconductor switch 12 such that the decoupling circuit 300 and the voltage divider 150 may be disposed on an interface adapter board in close proximity to the semiconductor switch. In some embodiments, the system 10 includes an additional signal conditioner 24 through which the device voltage, VCE· runs before going through the analog to digital converter 26 and being input to the ECU 16. In the illustrated embodiment, when the device enters and/or exits saturation (e.g., as determined by the saturation circuit), the gate-emitter voltage, VGE·, is sampled and combined with the device current, ICE , during an on state and device voltage, VCE·, during an off state as inputs to the table or model 32 to estimate the junction temperature, 7).

[0062] FIG. 12 is a flow chart of a process 350 for estimating junction temperature, Tj, of a semiconductor switch based upon gate-emitter voltage, VGE·, sampled when the device enters and/or exits saturation. At block 352, a turn on or turn off of the semiconductor switch is initiated. At block 204, the device voltage, VCE·, is monitored. The device voltage, VCE·, signal may then be run through one or more signal conditioners, which may apply one or more filters to the signal. The saturation detection circuit determines when the device enters and exits saturation. In block 356, if the device is not entering or exiting saturation, the process 350 returns to block 354 and continues monitoring the device voltage, VCE·. If the device is entering or exiting saturation, the gate-emitter voltage, VGE·, is sampled (block 358). In some embodiments, other values, such as device current, ICE, during an on state and/or device voltage, VCE·, during an off state may be logged or estimated in addition to the gate-emitter voltage, VGE·. At block 360, the sampled values are logged. At block 362, the junction temperature, 7), is estimated based on the logged values. Specifically, the sampled or estimated values (e.g., emitter voltage, VGE device current, ICE , during an on state and/or device voltage, VCE during an off state) may be inputs for a look-up table or model that estimates junction temperature, 7}, based on the input values. The process 350 returns to block 352 and initiates turn on or turn off of the semiconductor switch.

[0063] FIG. 13 shows the graphs 100, 102 of the gate-emitter voltage, VGE device current, ICE , and device voltage, VCE·, during an on-off cycle of FIG. 5, and the time 400 at which gate-emitter voltage, VGE’ may be sampled when current begins to flow through the semiconductor switch. During the turn on phase 130, the gate-emitter voltage, VGE climbs from an off gate-emitter voltage, VGE·, OFF (e.g., -15 volts) toward an on gate-emitter voltage, VGE ON (e.g., +15 volts). When the gate-emitter voltage, VGE reaches a threshold voltage, Vth, current begins to flow through the device (indicated by circle 402). Accordingly, the gate-emitter voltage, VGE may be sampled at time 400, logged, and input to the model or look up table to estimate junction temperature, 7}. As is described in more detail below, the presence of current flowing through the device may be determined by monitoring the voltage across the parasitic inductance between the emitter terminal and the reference emitter terminal, VEE which is indicative of the derivative of the current flowing through the device. In one embodiment, a sample of the gate-emitter voltage, VGE may be triggered when the voltage across the emitter terminals, VEE·, exceeds a configurable reference level. In another embodiment, the voltage across the emitter terminals, VEE·, may be integrated by an integrator circuit and a sample of the gate-emitter voltage, VGE·, may be triggered when the output of the integrator circuit exceeds a configurable reference level. As with the embodiments described above, other values (e.g., device current, ICE , during an on state and device voltage, VCE·, during an off state) may also be sampled or estimated. The gate-emitter voltage, VGE· and other sampled values may then be logged and input to a model or lookup table to estimate junction temperature, 7}. [0064] FIG. 14 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 3 in which junction temperature, 7), is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor switch 12. As illustrated, in addition to the gate-emitter voltage, VGE·, the voltage across the parasitic inductance between the emitter terminals, VEE·, is also measured. The voltage across the emitter terminals, VEE·, is sent through a signal conditioner 24, which may apply one or more filters, and then fed to a scaling stage 450. The scaling stage 450 then provides the signal to the ECU 16. In the instant embodiment, when the voltage across the emitter terminals, VEE·, exceeds a threshold value, indicating that current is flowing through the device, the system samples the gate-emitter voltage, VGE·, which is logged and used as an input to the look-up table or model to estimate the junction temperature, 7}.

[0065] FIG. 15 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 14 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor switch 12, and the device voltage, VCE·, during an off state. Current is determined to be flowing through the device when the voltage across the emitter terminals, VEE·, exceeds the threshold value. As shown, the voltage divider 150 is electrically coupled to the sensing collector terminal 58 and the reference emitter terminal 56. The voltage divider 150 samples the device voltage, VCE’, reduces the amplitude of the signal, and passes the signal to the signal conditioner 24, which may apply one or more filters. The device voltage, VCE·, also passes through an analog to digital converter 26 before being provided to the ECU 16. The gate-emitter voltage, VGE·, and the device voltage, VCE·, then act as inputs to the look-up table or model to estimate the junction temperature, 7}.

[0066] FIG. 16 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 14 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor switch 12. In the illustrated embodiment, an integrator circuit 452 is disposed between the signal conditioner 24 and the scaling stage 450. Because the voltage across the emitter terminals, VEE·, is representative of the derivative of the device current, ICE , the integrator circuit integrates the sampled emitter terminals, VEE·, to determine or estimate the device current, ICE. Once the device current, ICE , exceeds a threshold value, the ECU 16 samples the gate-emitter voltage, VGE·, which is then logged and used as an input to a lookup table or model 32 to estimate the junction temperature, 7).

[0067] FIG. 17 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 14 in which junction temperature, 7}, is estimated based on gate-emitter voltage, VGE·, sampled when current begins to flow through the semiconductor switch 12, and the device voltage, VCE during an off state. In the illustrated embodiment, an integrator circuit 452 is disposed between the signal conditioner 24 and the scaling stage 450. Because the voltage across the emitter terminals, VEE·, is representative of the derivative of the device current, ICE , the integrator circuit integrates the sampled emitter terminals, VEE·, to determine the device current, ICE. AS shown, the voltage divider 150 is electrically coupled to the sensing collector terminal 58 and the reference emitter terminal 56. The voltage divider 150 samples the device voltage, VCE reduces the amplitude of the signal, and passes the signal to the signal conditioner 24, which may apply one or more filters. The device voltage, VCE also passes through an analog to digital converter 26 before being provided to the ECU 16. Once the device current, ICE , exceeds a threshold value, the ECU 16 samples the gate-emitter voltage, VGE·, and which, along with the device voltage, Vac, during an off stateis then logged and used as an input to a lookup table or model 32 to estimate the junction temperature, 7}.

[0068] FIG. 18 is a flow chart of a process 500 for estimating junction temperature, 7j, of a semiconductor switch based upon gate-emitter voltage, VGE·, sampled when current starts flowing through the semiconductor switch. At block 502, a turn on of the semiconductor switch is initiated. At block 504, the parasitic inductance voltage (e.g., the voltage across the emitter terminals, VEE) is monitored. As discussed with regard to FIGS. 14 and 15, in some embodiments, the parasitic inductance voltage (e.g., the voltage across the emitter terminals, VEE) may be monitored directly. In other embodiments, the parasitic inductance voltage (e.g., the voltage across the emitter terminals, l ⁷ EE) may also be integrated to determine or estimate the device current, ICE. In decision 506, if current has started flowing through the device or if current has stopped flowing through the device, the process 500 returns to block 504 and continues monitoring the voltage across the emitter terminals, VEE·. If current is flowing through the device, the gate-emitter voltage, VGE·, is sampled (block 508). In some embodiments, other values, such as device current, ICE , and/or device voltage, VCE·, may be sampled or estimated in addition to the gate-emitter voltage, VGE At block 510, the sampled values are logged. At block 512, the junction temperature, 7), is estimated based on the sampled values. Specifically, the sampled values (e.g., emitter voltage, VGE·, device current, ICE , and/or device voltage, VCE·) may be inputs for a look-up table or model that estimates junction temperature, 7}, based on the input values. The process 500 returns to block 502 and initiates turn on of the semiconductor device.

[0069] FIG. 19 shows the graphs 100, 102 of the gate-emitter voltage, VGE·, device current, ICE , and device voltage, VCE·, during an on-off cycle of FIG. 9, and the times 250, 256 at which the device exits and enters saturation. However, rather than sampling the gate-emitter voltage, VGE·, when the device enters or exits saturation, the time to saturation and/or desaturation may be used to estimate junction temperature, 7}. For example, the ECU may monitor the device voltage, VCE·, during operation of the semiconductor switch. At time 550 the device starts the turn-off phase 122. During the turn-off phase 122, the device voltage, VCE·, begins at or near zero at the saturated voltage level, and then, at the first point in time 250, begins to increase as the device exits saturation, as indicated by circle 252. The ECU may recognize that the device has exited saturation and log the time to desaturation 552 (i.e., the time elapsed between point 550 and point 250). Similarly, at time 554 the device starts the turn-on phase 130. During the turn-on phase 130, the device voltage, VCE·, begins at an on device voltage, VCE·, OFF, and then, begins to fall to zero. At a second point in time 256 the device enters saturation, as indicated by circle 258. The ECU may recognize that the device has entered saturation and log the time to saturation 556 (i.e., the time elapsed between point 554 and point 256). The times to saturation and/or desaturation may be input to a model or lookup table to estimate junction temperature, 7}. It should be understood, however, that some embodiments may monitor only time to saturation 556, while other embodiments may monitor only time to desaturation 552. Further, some embodiments may monitor both time to saturation 556 and time to desaturation 552.

[0070] FIG. 20 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 10 in which junction temperature, 7}, is estimated based on time to device saturation and/or desaturation. The saturation state of the device is output to the ECU 16. The ECU 16 tracks and logs the time to saturation and/or desaturation (e.g., as determined by the saturation circuit 302). The time to saturation and/or desaturation are input to the look up table or model 32 to estimate the junction temperature, 7}. In some embodiments, other values, such as the device current, ICE , may also be input to the look up table or model 32 to estimate the junction temperature, 7}. It should be noted that, relative to the system 10 shown in FIG. 10, one of the signal conditioners 24 and the ADC 26 have been omitted because in the instant embodiment, the gate-emitter voltage, VGE·, is not sampled.

[0071] FIG. 21 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 11 in which junction temperature, 7}, is estimated based on time to device saturation and/or desaturation, device current, ICE , during an of phase, and device voltage, VCE·, during an off phase. As shown, the system 10 includes the voltage divider 150, which is electrically coupled to the sensing collector terminal 58 and the reference emitter terminal 56, to sample the device voltage, VCE·. AS discussed above, the voltage divider 150 samples the device voltage, VCE· (i.e., the voltage across the collector 52 and emitter 54) and outputs a reduced value of the device voltage, VCE·. In some embodiments, the system 10 includes an additional signal conditioner 24 through which the device voltage, VCE· runs before going through the analog to digital converter 26 and being input to the ECU 16. In the illustrated embodiment, when the device enters and/or exits saturation (e.g., as determined by the saturation circuit), the time to saturation and/or desaturation, device current, ICE , and device voltage, VCE·, are used as inputs to the table or model 32 to estimate the junction temperature, 7). A possible embodiment using the device current Ice to refine the estimate of the junction temperature of the semiconductor switch further than using only the time to desaturation is given by the model described by the equation below:

Where A(I) and B(I) are specific functions of the device current, I _ce.

[0072] FIG. 22 is a flow chart of a process 600 for estimating junction temperature, 7/, of a semiconductor switch based upon time to device saturation and/or desaturation. At block 602, a turn on or turn off of the semiconductor switch is initiated. As discussed above, the semiconductor switch may run for a period of time (e.g., 20-30 seconds or more) to warm up before junction temperature, 7}, may be estimated based on time to device saturation and/or desaturation. At block 604, the timer is initiated. At block 605, device voltage, VCE’, is monitored. The device voltage, VCE·, signal may then be run through one or more signal conditioners, which may apply one or more filters to the signal. The saturation detection circuit determines when the device enters and exits saturation. In decision 606, if the device is not entering or exiting saturation, the process 600 returns to block 605 and continues monitoring the device voltage, VCE·. If the device is entering or exiting saturation, the timer is stopped (block 608) and the time to saturation or desaturation is logged (block 610). In some embodiments, other values, such as device current, ICE , during an on state or a determined during a switching transient, and/or device voltage, VCE·, during an off state, may be logged in addition to time to saturation and/or desaturation. At block 612, the junction temperature, 7}, is estimated based on time to saturation and/or desaturation, and in some embodiments, the other values. Specifically, the time to saturation and/or desaturation and the other sampled or estimated values (e.g., device current, ICE , during an on state, and/or device voltage, VCE·, during an off state) may be inputs for a look-up table or model that estimates junction temperature, 7}, based on the input values. The process 600 returns to block 602 and initiates turn on or turn off of the device. [0073] FIG. 23 shows the graphs 100, 102 of the gate-emitter voltage, VGE device current, ICE , and device voltage, VCE during an on-off cycle of FIG. 13, and the time 400 at which current begins to flow through the semiconductor switch. At point 554, the device enters the turn-on phase 130. During the turn on phase 130, the gate-emitter voltage, VGE climbs from an off gate-emitter voltage, VGE’.OFF (e.g., -15 volts) toward an on gate-emitter voltage, VGEON (e.g., +15 volts). When the gate-emitter voltage, VGE reaches a threshold voltage, Vth, (indicated by circle 402) current begins to flow through the device. Accordingly, the time to threshold 650 may be logged, and input to the model or look up table to estimate junction temperature, 7}. As described above, the presence of current flowing through the device may be determined by monitoring the voltage across the parasitic inductance between the emitter terminal and the reference emitter terminal, VEE which is indicative of the derivative of the current flowing through the device. In one embodiment, a time to threshold 650 is the time elapsed from the moment 554 the device enters the turn-on phase 130 to the moment 400 when the voltage across the emitter terminals, VEE exceeds a configurable reference level. In another embodiment, the voltage across the emitter terminals, VEE may be integrated by an integrator circuit and the time to threshold 650 is the time elapsed from the moment 554 the device enters the turn-on phase 130 to the moment 400 when the output of the integrator circuit exceeds a configurable reference level. As with the embodiments described above, other values (e.g., device current, ICE , during an on state, and device voltage, VCE during an off state) may also be sampled or estimated and logged when the time to threshold 650 is logged. The time to threshold 650 and other values may then be input to a model or lookup table to estimate junction temperature, Tj.

[0074] FIG. 24 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 14 in which junction temperature, Tj, is estimated based on time for current to flow through the semiconductor switch 12. As illustrated, the voltage across the emitter terminals, VEE is sampled and sent through a signal conditioner 24, which may apply one or more filters, and then fed to a scaling stage 450. The scaling stage 450 then provides the signal to the ECU 16. In the present embodiment, the timer 28 tracks the time elapsed from when the device 12 enters the turn on phase to the moment when the voltage across the emitter terminals, VEE·, exceeds a threshold value. The time to threshold is logged and used as an input to the look-up table or model to estimate the junction temperature, 7).

[0075] FIG. 25 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 24 in which junction temperature, 7}, is estimated based on time for current to flow through the semiconductor switch 12. Current is determined to be flowing through the device when the voltage across the emitter terminals, VEE·, exceeds the threshold value. As shown, the voltage divider 150 is electrically coupled to the sensing collector terminal 58 and the reference emitter terminal 56. The voltage divider 150 samples the device voltage, VCE’, reduces the amplitude of the signal, and passes the signal to the signal conditioner 24, which may apply one or more filters. The device voltage, VCE·, also passes through an analog to digital converter 26 before being provided to the ECU 16. The time to threshold and the device voltage, VCE·, then act as inputs to the look-up table or model to estimate the junction temperature, 7}.

[0076] FIG. 26 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 16 in which junction temperature, 7}, is estimated based on time for current to flow through the semiconductor switch 12. In the illustrated embodiment, an integrator circuit 452 is disposed between the signal conditioner 24 and the scaling stage 450. Because the voltage across the emitter terminals, VEE·, is representative of the derivative of the device current, ICE , the integrator circuit integrates the sampled emitter terminals, VEE·, to determine the device current, ICE. Once the device current, ICE , exceeds a threshold value, the ECU 16 logs the time to threshold and uses the time to threshold as an input to a lookup table or model 32 to estimate the junction temperature, 7}.

[0077] FIG. 27 is a schematic of an embodiment of the semiconductor based system 10 of FIG. 24 in which junction temperature, 7}, is estimated based on time for current to flow through the semiconductor switch 12, and device voltage, VCE·, during an off phase. In the illustrated embodiment, an integrator circuit 452 is disposed between the signal conditioner 24 and the scaling stage 450. Because the voltage across the emitter terminals, VEE·, is representative of the derivative of the device current, ICE , the integrator circuit integrates the sampled emitter terminals, VEE·, to determine the device current, ICE. AS shown, the voltage divider 150 is electrically coupled to the sensing collector terminal 58 and the reference emitter terminal 56. The voltage divider 150 samples the device voltage, VCE·, reduces the amplitude of the signal, and passes the signal to the signal conditioner 24, which may apply one or more filters. The device voltage, VCE·, also passes through an analog to digital converter 26 before being provided to the ECU 16. Once the device current, ICE , exceeds a threshold value, the ECU 16 logs the time to threshold and uses the time to threshold and the device voltage, VCE·, as inputs to a lookup table or model 32 to estimate the junction temperature, 7).

[0078] FIG. 28 is a flow chart of a process 700 for estimating junction temperature, T _j , of a semiconductor switch based upon time for current to start flowing through the device. At block 702, a turn on of the semiconductor switch is initiated. As discussed above, the semiconductor switch may run for a period of time (e.g., 20-30 seconds or more) to warm up before junction temperature, 7}, may be estimated based on time for current to flow through the device. At block 704, the timer is initiated. At block 705, the parasitic inductance voltage (e.g., the voltage across the emitter terminals, VEE) is monitored. In some embodiments, the parasitic inductance voltage, VEE·, may be monitored directly. In other embodiments, the parasitic inductance voltage, VEE·, may be integrated to determine the device current, ICE. In general, the voltage across the emitter terminals, VEE·, may be indicative of the device current, ICE. In decision 706, if current is not flowing through the device, the process 700 returns to block 705 and continues monitoring the voltage across the emitter terminals, VEE·. If current is flowing through the device, the timer is stopped (block 708) and the time to threshold is logged (block 710). In some embodiments, other values, such as device current, ICE , during an on state, and/or device voltage, VCE·, during an off state, may be logged in addition to time to threshold. At block 712, the junction temperature, Tj, is estimated based on time to threshold, and in some embodiments, the other sampled values. Specifically, the time to threshold and the other values (e.g., device current, ICE , and/or device voltage, VCE·) may be inputs for a look-up table or model that estimates junction temperature, 7), based on the input values. The process 700 returns to block 702 and initiates turn on of the device.

[0079] The disclosed techniques include estimating junction temperature of a semiconductor switch based on sampled electrical parameters. By using junction temperature estimation instead of direct measurement (e.g., optical measurement, direct contact measurement, etc.), the integrity of device packaging may be maintained, and the footprint of the device packaging may be kept small. In one embodiment, the sampled electrical parameter may include gate-emitter voltage, VGE sampled upon the expiration of a timer configured to expire during a specific time during the semiconductor switch’s on-off cycle. In another embodiment, the device voltage, VCE may be monitored as the device runs. A sample of the gate-emitter voltage, VGE may be triggered when the device enters or exits saturation. In another embodiment, the voltage across the parasitic inductance between the emitter terminal and the reference emitter terminal, VEE may be monitored to determine when current begins to flow through the semiconductor switch. When current begins to flow, a sample of the gate-emitter voltage, VGE may be triggered. In yet another embodiment, the time elapsed from entering the turn on phase to saturation and/or the time elapsed from entering the turn-off phase to desaturation may be tracked and logged. In a further embodiment, the time elapsed from entering the turn on phase until current starts to flow through the device (as indicated by the voltage across the parasitic inductance between the emitter terminal and the reference emitter terminal, VEE) may be tracked and logged. In each embodiment, the sampled and/or tracked values, along with other sampled values in some embodiments, may be input to a lookup table or model to estimate the junction temperature of the semiconductor switch. The estimated junction temperature, 7}, of the semiconductor switch may provide useful information about the state of the semiconductor switch, as well as to provide a reference to make sure the device is operating below the specified maximum junction temperature, Tj,max.

[0080] This written description uses examples to disclose the claimed subject matter, including the best mode, and also to enable any person skilled in the art to practice the disclosed subject matter, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the claimed subject matter is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.