SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING OPC MODELING VIA MACHINE LEARNING ON SIMULATED 2D OPTICAL IMAGES

FOR SED AND POST SED PROCESSES

5 CLAIM OF PRIORITY [0001] None.

COPYRIGHT NOTICE

[0002] A portion of the disclosure of this patent document contains material which is 10 subject to copyright protection. The copyright owner has no objection to the facsimile

reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

15 TECHNICAL FIELD

[0003] The subject matter described herein relates generally to the field of semiconductor and electronics manufacturing, and more particularly, to systems, methods, and apparatuses for implementing Optical Proximity Correction (OPC) modeling via machine learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED 20 processes.

BACKGROUND

[0004] The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem 25 mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.

[0005] Conventional techniques utilizing Optical Proximity Correction (OPC) models 30 are not sufficiently accurate as semiconductor manufacturing techniques necessitate increasingly

- 1 - Attorney Docket No.: P107351PCT

strict tolerances and smaller physical dimensions.

|0006] For advanced process nodes in semiconductor manufacturing, one of the major challenges are to control defects and yield to a level that is viable for high volume manufacturing (HVM). To maintain the density scaling and reduce cell footprint, process margins are tightening 5 which in turn causes systematic and random process variations resulting in the processes being more prone to defects.

[0007] One such source of process variation is the result of insufficiently accurate model prediction of lithographic processes, which impacts the optical proximity correction (OPC) of mask design.

10 |0008] The accuracy of these measurements and the accuracy of the model is of utmost importance because any variation of the OPC model translates to a variation of dimensions on the final semiconductor chips produced.

[0009] When the physical dimensions of the manufactured semiconductors were greater, such inaccuracies and uncertainty were manageable due to the greater margins. However, as the 15 physical size of these manufactured semiconductors is reduced further into the nanometer realm of manufacturing, it becomes necessary to operate using increasingly accurate models if manufacturing yields are to remain economically viable.

[0010] The present state of the art may therefore benefit from the systems, methods, and apparatuses for implementing Optical Proximity Correction (OPC) modeling via machine 20 learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED

processes as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments are illustrated by way of example, and not by way of limitation, 25 and will be more fully understood with reference to the following detailed description when considered in connection with the figures in which:

[0012] Figure 1A depicts an exemplary Artificial Neural Network (ANN) machine learning algorithm in which the input variables predict the deterministic model error or process driven changes in critical dimension in accordance with described embodiments;

30 [0013] Figure IB depicts a bar chart depicting benchmarking model performance

improvements over previous solutions in accordance with described embodiments;

|0014] Figure 2A depicts an exemplary modeling flow utilizing the Artificial Neural Network (ANN) machine learning algorithm in accordance with described embodiments;

-2- [0015] Figure 2B depicts an exemplary schematic of an Artificial Neural Network utilized for predicting the EPE shift amounts from the 2D optical image of every EPE in accordance with described embodiments;

[0016] Figure 3 depicts several exemplary comparisons between trained models and actual SEM images in accordance with described embodiments;

[0017] Figure 4A depicts exemplary post-SED model performance for specific geometries in accordance with described embodiments;

[0018] Figure 4B depicts another exemplary post-SED model performance for specific geometries in accordance with described embodiments;

[0019] Figure 5 depicts a comparison between Cartesian and polar model inputs in accordance with described embodiments;

[0020] Figure 6 depicts an exemplary simulated 2D optical image map in accordance with described embodiments;

[0021] Figure 7 is a schematic of a computer system in accordance with described embodiments;

[0022] Figure 8 illustrates a semiconductor device (or an interposer) that includes one or more described embodiments;

[0023] Figure 9 illustrates a computing device in accordance with one implementation of the invention; and

[0024] Figure 10 is a flow diagram illustrating a method for reducing Optical Proximity

Correction (OPC) model error via machine learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED processes in accordance with described embodiments.

DETAILED DESCRIPTION [0025] Described herein are systems, methods, and apparatuses for implementing

Optical Proximity Correction (OPC) modeling via machine learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED processes. For instance, in accordance with one embodiment, there are means described for creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of me lithography process used to create the mask, the semi-physical model specifying optical intensity values representing the plurality of features of the mask;

capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the features of the mask as represented by the optical intensity values within the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting contours of the plurality of features of the mask as represented by the optical intensity values within the semi-physical model based on the quantified differences.

[0026] Optical Proximity Correction (OPC) models require accurate mask layout dimensions as input parameters. The greater the accuracy, the more useful and accurate the resulting model will be for the semiconductor manufacturing processes.

[0027] The methodologies described herein provide improvements to OPC model accuracy which may then be applied to a variety of lithography processes.

10028 ) As circuit feature sizes shrink to enable continued Moore's Law scaling, the accuracy requirements for the placement and size of individual wafer features continue to tighten. A critical determiner of this wafer feature scaling is lithography fidelity, which is a direct result of proper feature sizing on the product photomasks. The size of mask features is directly determined by the OPC (Optical Proximity Correction) as determined by the OPC lithography model. As the Edge Placement Error (EPE) requirements tighten for next generation node manufacturing, such as 10-nanometer (nm) node and beyond, significant improvements are required in OPC modeling capability to enable both efficient process development cycles, and ultimately to enable correct feature sizes on product wafers to so as to attain proper circuit function.

[0029] Resist patterns generated by lithographic processes are the results of complicated optical, chemical and physical phenomenon, which can be modeled based on optical image parameters and geometric parameters. Model predictions, which are represented in the form of contours, are generated based on the distorted image maps, which are numerically stable and efficient enough to be used for high volume manufacturing. To generate an accurate and yet numerically efficient model, machine learning algorithms such as Artificial Neural Network (ANN) algorithms are employed in accordance with certain embodiments.

[0030] The methodologies illustrated here as well as the systems and apparatuses which implement or embody such methodologies are utilized to further enhance OPC Model prediction beyond currently known techniques. According to described embodiments, such OPC models begin with a semi-physical lithography model as well as commonly contained empirical postSED (Spin Exposure Develop) process biases so that a reticle corrected with the described techniques satisfy both lithographic and post-Etch device requirements.

[0031] Conventional OPC models employed for reticle correction model optical and resist lithography phenomenon utilized various approximations to speed up calculations to enable full-chip correction which resulted in model errors that can no longer be sustained for advanced technology nodes due to the stricter tolerances and reduced dimensions of modern semiconductor manufacturing. Alternate techniques such as rigorous finite difference time domain (FDTD) calculations help to improve accuracy but are computationally unfeasible for large scale and high volume manufacturing processes.

[0032] The techniques described herein are demonstrated to produce more accurate lithographic models than conventional OPC models with an acceptable increase in computational cost and are therefore economically viable for manufacturing.

|0033| Rule based model error compensation has also been conventionally utilized for known problematic configurations. However, such a technique is only feasible for a very limited set of geometries, and it is therefore infeasible to generate the requisite rules for all possible configurations in the circuit pattern. Moreover, use of rule based model error compensation introduces unnecessary and undesirable complexity into the tapeout flow, which in turn translates to increased costs in terms of the engineering resources necessary to characterize, specify, code, and validate such rules as well as computational resources required to then calculate the models.

[0034] Existing modeling software for OPC modeling provides a predictive model for lithographic processes. Such models are then relied upon for applying corrections to the masks so as to ensure correct pattern fidelity and correct dimensions of features on the manufactured silicon wafers.

[0035] The existing modeling software for OPC is deficient in terms of the accuracy when new lithographic systems having tighter margins and dimensions are utilized, resulting in unworkable errors inhibiting the newer technologies from being successfully scaled to high volume manufacturing. Conventional OPC models simply cannot predict with sufficient accuracy and precision to the smaller feature size and feature geometries associated new technologies.

[0036] Improvements to the existing OPC models are needed such that the OPC models which drive manufacturing may be successfully utilized to attain sufficiently accurate pattern fidelity on the mask and on the manufactured silicon wafers.

[0037] Use of the conventional models have been demonstrated to result in unacceptable yields from the fabrication process due to the degree of uncertainty of such models, resulting in the features actually printed failing within the layers due to the size of the features as printed which is a direct result of the inaccurate models. The position and size of the features of the mask are critical to the functioning of the circuit produced and on the scale of nanometers the margin for error becomes incredibly small, thus necessitating model outputs with a greater degree of precision. Printing deviances of tens of nanometers in the process which are not accounted for in the design will render an entire silicon wafer inoperable. Such a circuit simply will not work and will not function like a processor because such deviations cause joins and shorts which are not part of the circuit design.

[0038] The conventional OPC models need further adjustment and correction and improved contour correction or shifting means so as to move these printed features into the correct position with a greater degree of precision. Such improvements ensure functionally operable silicon and thus improve manufacturing yields and profitability for any given product.

10039 ) In the following description, numerous specific details are set forth such as examples of specific systems, languages, components, etc., in order to provide a thorough understanding of the various embodiments. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the embodiments disclosed herein. In other instances, well known materials or methods have not been described in detail in order to avoid unnecessarily obscuring the disclosed embodiments.

[0040] In addition to various hardware components depicted in the figures and described herein, embodiments further include various operations which are described below. The operations described in accordance with such embodiments may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the operations. Alternatively, the operations may be performed by a combination of hardware and software.

[0041] Any of the disclosed embodiments may be used alone or together with one another in any combination. Although various embodiments may have been partially motivated by deficiencies with conventional techniques and approaches, some of which are described or alluded to within the specification, the embodiments need not necessarily address or solve any of these deficiencies, but rather, may address only some of the deficiencies, address none of the deficiencies, or be directed toward different deficiencies and problems which are not directly discussed.

[0042] Implementations of embodiments of the invention may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.

[0043] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the invention may also be carried out using nonplanar transistors.

[0044] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0045] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

[0046] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0047] In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0048] In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0049] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0050] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors.

The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or

polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0051] Figure 1A depicts an exemplary Artificial Neural Network (ANN) 105 machine learning algorithm in which the input variables predict the deterministic model error or process driven changes in critical dimension in accordance with described embodiments.

[0052] More particularly, there is depicted on the left an initial OPC contour 120 represented by the bold line and outermost ellipse and then a second contour is further depicted via the inner ellipse showing the Scanning Electron Microscope (SEM) contour 125 representing fabrication data as taken from an SEM image.

[0053] On the right is a neural network 105 having as input several input image parameters 1 10 which are calculated using an OPC model and the resulting output from the neural network is a contour shift prediction 115. In accordance with one embodiment the image input parameters 1 10 used to train the neural network 105 are simulated optical parameters representing the entirety of the feature set for use as the input image parameters 1 10.

[0054] Any specific layout will have a deterministic OPC model error. Neural networks, such as Artificial Neural Network (ANN) 105, are able to approximate any arbitrary formula. Therefore, in accordance with described embodiments, the neural network 105 is trained to describe the relationship between the layout and the respective OPC model error, using the image input parameters 1 10 to enable the neural network 105 to learn about the layout. A sufficient quantity of image input parameters 1 10 are provided so as to enable such learning.

[0055] A simulated optical image from conventional OPC models is obtained from the convolution of the layout and an optical transfer function. According to described embodiments, image parameters are defined via optical images that capture information about the layout which is men used to train the neural network 105 to describe the deterministic relationship between the layout and conventional OPC model error.

|0056] Through the application of machine learning techniques using, for instance, the depicted Artificial Neural Network (ANN) 105 as well as Convolutional Neural Networks (CNN), it is possible to train OPC models capable of compensating for discrepancies between simulated semi-physical models and actual physical measurements taken from SEM images. Using such compensation, the OPC models are made to yield improved predictive results with reduced EPE at various process steps, resulting in better corrected reticles that help in meeting the technology requirement of that node, such as placement within design tolerances.

[0057] Within the context of machine learning, an Artificial Neural Network (ANN) 105 is a computational approach which is based on a large collection of neural units loosely modeling the way a biological brain solves problems with large clusters of biological neurons connected by axons. Each neural unit is connected with many others, and links can be enforcing or inhibitory in their effect on the activation state of connected neural units. Such systems are self-learning and trained rather than explicitly programmed and they excel in areas where the solution or feature detection is difficult to express in a traditional computer program.

[0058] A so called convolutional neural network (CNN, or ConvNet) is a type of feedforward artificial neural network in which the connectivity pattern between its neurons is inspired by the organization of the animal visual cortex. Individual cortical neurons respond to stimuli in a restricted region of space known as the receptive field. The receptive fields of different neurons partially overlap such that they tile the visual field. The response of an individual neuron to stimuli within its receptive field can be approximated mathematically by a convolution operation.

|0059] According to certain embodiments, geometric information from the layout is additionally utilized to directly train the neural network to predict the amount of model error associated with the geometry. Once trained, the neural network 105 provides a more accurate model which can then be implemented by shifting the initial OPC contour 120 by an amount predicted by neural network 105.

[0060] The OPC model provides a forward function which connects what is on the mask to what is on the wafer. Software algorithms provide a basic physics solution to this problem, but the solution requires many approximations which thus operates as a source of inaccuracies.

Described embodiments therefore reformulate the problem in such a way that a list of features is provided to the neural network for the purposes of training. Through training based on such input features, such as those derived from the depicted input image parameters, the neural network learns what adaptations are necessary to conform the base OPC models to known physical models. These adaptations are output as the contour shift predictions 115 and result in a semi- physical model which permits formulas and corrections by which the trained neural network 105 describes the differences between the incoming base OPC model and the observed physical realities.

[0061] Because the model, the structures, the features, and the mask is so complex it simply is not practical to manually determine what function or adaptations to the incoming base OPC model are necessary to conform that model to the reality as observed in the SEM imagery taken from fabricated silicon wafers utilizing the base OPC model. Use of the neural network 105 to apply machine learning therefore provides a significant advantage as the neural network is leveraged to determine the complexity and learn the necessary adaptations.

10062 ) In accordance with certain embodiments, the neural network 105 predicts the deterministic model error or process driven changes in critical dimensions for the size and position of features. According to a particular embodiment, the neural network provides contour fitting to the SEM contour 125 image representing the actually observed physical outputs from a fabrication process utilizing the base OPC model which provides the initial OPC contour 120.

[0063] In accordance with certain embodiments, the initial OPC contour 120 is a result of the software algorithms which provides a prediction of the physical space via a semi-physical model. According to such an embodiment, SEM image data is then collected for the patterns to generate or determine the SEM contour 125 representing the fab data for actual physical samples of fabricated physical silicon wafers generated using the initial OPC base model.

[0064] According to such an embodiment, the delta between the initial OPC contour 120 and the SEM contour 125 is the determined model error of the base OPC model. The neural network 105 is trained to be able to predict the determined model error of the base OPC model so as to output an improved model using the contour shift prediction 1 15 provided by the trained neural network 105.

[0065] Figure IB depicts a bar chart depicting benchmarking model performance 101 improvements over previous solutions in accordance with described embodiments.

[0066] More particularly, the bar chart depicts the Edge Placement Error (EPE) 160 on the vertical axis and the base semi-physical model 155 on the left. As may be observed by the bar 140, the improved MERLN2d model which is described herein provides a 35% EPE improvement 135 over the simple MERLN model (see element 135) and as may be further observed at bar 145, the improved MERLN2d model described herein provides a 50% EPE improvement over the base semi-physical model (see element 130).

[0067] The simple MERLN model provides worthwhile improvements over the base semi-physical model, however, as tolerances reduce to ever smaller dimensions, further improvements are necessary. The improved methodologies described herein yield such improvements through advanced machine learning modeling techniques described in more detail below.

[0068] Figure 2 A depicts an exemplary modeling flow 201 utilizing the Artificial

Neural Network (ANN) machine learning algorithm in accordance with described embodiments.

[0069] More particularly, there is described at block 206 means for sampling data collection for model building when then proceeds to block 211 where a base OPC model (e.g., an initial contour such as the initial OPC contour depicted by element 120 at Figure 1A) is provided. According to certain embodiments, the processing advances to block 215 where a correction engine for mask design applies the contour as rendered by the base OPC model.

[0070] However, described embodiments provide further correction and improvement over the base OPC model via the contour shift as predicted by the trained neural network. In particular, returning to block 210 where the base OPC model or the initial contour is provided, the processing instead advances into the newly introduced elements of the modeling flow 201 depicted by the dashed line in which processing from block 21 1 advances next to block 221 where a model error and lithographic process characterization is applied. Next, contour shifting 226 is applied utilizing the contour shift as predicted by the trained neural network. After contour shifting 226, processing then advances to block 231 where the final model or the final contour is provided as a result of the contour shifting 226 applied using the contour shift as predicted by the neural network.

[0071] After the final model is provided, processing then returns to block 216 where a correction engine for the mask design applies the appropriate correction as benefitted from the contour shifting 226 operation.

[0072] In accordance with one embodiment, the trained neural network output providing the contour shift prediction results in a third contour, one between the initial OPC contour 120 and the SEM contour 125 (see Figure 1A), which is a predicted contour as output by applying the contour shift prediction 115 of the trained neural network as a correction for the base OPC model, thus yielding an improved contour fit between the improved prediction and reality.

[0073] As depicted, the contour shifting 226 operation produces the final model's final contour at block 231 from the input base OPC model's initial contour at block 211, and it is this final contour which is then utilized by the correction engine for the mask design at block 216.

[0074] Ideally, the combination of the semi-physical model and the output of the trained neural network would exactly equal the physical data which equates the observed measurements from the SEM imagery data. In practice, significant improvement is attained as described below, but the predicted final contour 230 is not exactly identical, but it is sufficiently accurate for the smaller feature size dimensions and positions utilized by the newer technologies, and thus, appropriate for scaling up silicon wafer production in high volume manufacturing.

[0075] Although not exact, the predicted final contour rendered by the final model at block 231 is much closer to the actually observed SEM data and the contour shifting 226 as provided by the contour shift prediction 1 15 from Figure 1 A is thus usable to better predict a wide array of structures and how they will behave, which may then compared to new SEM imagery for such features. Moreover, iterative training of the neural network further improves the predictive capability and thus improves the eventual final model and final contour 230 for any mask structures and features.

[0076] As depicted, the final model 231 is then re-applied via OPC correction to modify the mask such that features and structures are positioned in the correct location such that when a next silicon wafer is fabricated through the manufacturing process, all the structures and features will be in the correct location and the resulting silicon die will be functional and operate correctly according to design specifications.

[0077] Figure 2B depicts an exemplary schematic of an Artificial Neural Network 201 utilized for predicting the EPE shift 210 amounts from the 2D optical image of every EPE in accordance with described embodiments. Element 245 provides the formula for Edge Placement Error shift, where where km represents the

coefficients of the trained kernel 235 and where lm represents optical intensity 240.

[0078] According to described embodiments, the EPE shift prediction 210 rendered as an output by the model seeks to fit a delta between the semi-physical model and the measured wafer data as obtained from SEM imagery. According to such embodiments, the fitting the delta or predicting the EPE shift is rendered as an output by the neural network which accepts as inputs the pixelated optical image intensity 240 values from the 2D optical images 220, 225, and 230.

[0079] As depicted here, there are multiple image maps 220, 225, and 230 which are utilized to provide the Artificial Neural Network 201 with an image map for every EPE 215 within an input sample collection of the provided image maps 220, 225, and 230, thus resulting in the Artificial Neural Network 201 yielding as an output the EPE shift prediction 210.

[0080] Any weights learned in the model may be interpreted as 2D kernels from each neuron in the architecture according to described embodiments. [0081] As depicted here, EPE contour shift prediction 210 is calibrated using the pixelated 2D optical images 220, 225, and 230 simulated around the model contour edge. In order to apply the machine learning techniques on the overwhelming amount of information and generate useful models for OPC, techniques such as spatial/MEEF (Mask Error Enhancement Factor) regularization, kernel smoothing, PCA (Principal Component Analysis) reduction have been developed and applied. Using such techniques, the convolutional neural networks (CNN) and improved models are trained on SEM images obtained either after conventional SED processing, or after post-SED process processing.

[0082] As depicted via the pixelated 2D optical images 220, 225, and 230, the trained kernels act upon each of the 2D optical images 220, 225, and 230 at a location to predict the EPE shift amount. The kernels constructed during the machine learning training then reveal characteristic signatures of the layout design data as may be observed within the pixelated 2D optical images 220, 225, and 230 revealing typical features and structures despite being rendered entirely within a simulated image.

[0083] The models described herein provide output which predicts the critical dimensions of the features, geometries, and other structures which will be printed upon a wafer after lithography and etching and other patterning processes. Consequently, it is very important that the models are as precise as possible so as to best represent what the fabricated wafer will ultimately become. Errors in the model translate to potentially systematic errors within the fabricated wafer and impede high volume manufacturing, impede efficient production, and slow the time from development to release of a new product as the errors in the model must be resolved so as to attain a correctly fabricated product.

[0084] According to described embodiments, a semi-physical model is utilized which describes the optics of, for instance, a lithographic mask, upon which various machine learning techniques are them applied to describe the inaccuracies of the previous semi-physical model versus what is actually observed within fabricated wafers, based on, for instance, SEM images of such wafers.

[0085] According to certain embodiments, parameters calculated based on a baseline semi-physical model are utilized as input into the neural networks for the purposes of training the model. However, in other embodiments, simulated optical images are pixelated so as to produce pixelated 2D optical images 220, 225, and 230.

[0086] The baseline semi-physical optical models are able to predict an optical image of the radical and therefore, that output of the baseline semi-physical optical may be received as an input into a process which then pixelates the image which may then be utilized as input into the neural networks for training the models or for learning algorithms.

|0087] For instance, through such a process the machine learning neural networks will "learn" or otherwise identify how to describe the inaccuracies between the pixelated 2D optical images 220, 225, and 230 provided as input into the neural network and actual physical measurements from SEM images, thus producing an EPE shift prediction 210 which may then be utilized to adjust the contours predicted by the models.

[0088] Contour adjustments to the semi-physical model are necessary because the predictions by a model do not exactly match the end result of a fabricated silicon wafer having physically undergone a lithography process. Such contour adjustments, using for example the EPE shift prediction 210 therefore help to better align the predictions of the models with the end result of the corresponding physical processes which result in the fabricated wafer.

[0089] For example, by taking SEM images of the fabricated wafer at the FCCD stage (Final Check of Critical Dimensions) or the DCCD stage (Develop Check of Critical

Dimensions) and capturing the differences between the actual measurements obtained from SEM images and the predictions of the semi-physical model, it is then possible to measure the inaccuracies between the features and geometries represented within the model versus those same corresponding features and geometries actually fabricated into the wafer.

(0090] With the known inaccuracy obtained, the neural networks can then be utilized in pursuit of the objective to reduce the inaccuracy between the predictions of the semi-physical model and the actual measurement data captured from the SEM images.

[0091] According to described embodiments, the photolithographic mask pattern is utilized as an input into the semi-physical model to predict what will be lithographically printed onto a wafer. According to such embodiments, a physical lithographic mask is also utilized to generate 2D optical images which may then be pixelated to generate the pixelated 2D optical images 220, 225, and 230 which are used as inputs into the neural network for the purposes of training.

[0092] Therefore, according to such embodiments, the model is utilized to predict the result of lithographic patterning for any given physical lithographic mask.

[0093] According to such embodiments, EPE represents the discrepancy, delta, or measured inaccuracy between the predictions for any given feature or geometry as provided by the semi-physical model versus the reality of those same corresponding features and geometries within a wafer, as captured by an SEM image.

[0094] According to described embodiments, simulated optical images are therefore created using a semi-physical model, converted into the pixelated 2D optical images 220, 225, and 230 shown here, which are then provided as input to this neural network. Measurements of actual EPE data is then additionally provided as input into the neural network from which the code of the neural network then develops the necessary transformations starting from the simulated images (based on the photolithographic physical mask) to the actual physical measurements taken from the SEM images.

[0095] In such a way, there may be considered two systems. A first system which utilizes the semi-physical model by taking a photolithographic mask as its input and providing as an output a prediction of what the physical reality should be and a second system which accepts as its input the predictions from the semi-physical model along with the physical measurements from the actual electron microscope imagery and provides as its output an offset or contour adjustment necessary to bring the actual physically fabricated wafer into alignment with the predictions by the model.

[0096] For instance, such an offset may be considered an etch placement error shift which accounts for the various features and geometries of the model and renders the necessary contour adjustments so as to permit the models to more accurately predict what will result from the physical photolithographic Spin, Exposure, Develop, (SED) and post SED processes.

[0097] While use of the pixelated 2D optical images 220, 225, and 230 is possible, they result in a very large number of parameters for every spatial point. For instance, according to certain embodiments, there are several hundred parameters which describe every single point This quantity of data represents a challenging computational problem.

[0098] By flattening the pixelated 2D optical images 220, 225, and 230 into a one- dimensional (ID) array which is then input into the neural network the computational workload is significantly reduced, but it nevertheless remains necessary to impose a 2D nature or a 2D architecture upon the data, notwithstanding the flattening of the pixelated 2D optical images.

[0099] Therefore, it is in accordance with certain embodiments that the neurons are topically averaged out over their neighboring pixels. In such a way it is thus possible to smooth out the neurons averaging over the topically neighboring pixels during the training of the models within the neural network using the pixelated 2D optical images flattened into 1 D arrays.

[00100] Because the architecture of the neural network lacks any inherent knowledge of two-dimensionality of the data and simply views a 10x10 pixel-set as 100 numbers, it is possible to flatten the 2D images into the ID array, however, it is then necessary to represent certain relationships between the numbers, such as their special association due to, for instance, borders between pixels, etc.

[00101] Therefore, according to another embodiment, a constraint is applied to the neural network architecture during the training of the models by performing spatial regularization such that the 2D optical images are shifted in either the X or Y direction by a small amount, thus constraining any predicted EPE shift given as an output by the trained models to correspondingly small amount. Stated differently, the spatial regularization and spatial averaging of the data making up the one-dimensional array prevents any abnormally large jumps or sharp deviations by the predicted adjusted contour, thus permitting greater adhesion or compliance between the adjusted contour of a model with the actual underlying geometries and features of a fabricated wafer when measured via SEM image data.

[00102] According to another embodiment, given three nodes in the neural network with each of the three nodes using simulated optical images, each of the three nodes will learn about 2D kernels by fitting parameters inside the neural network. Because the inputs are 2D in nature, fitting of parameters may be applied as 2D weightings resulting in a two-dimensional

interpretation.

[00103] As depicted here, the learned 2D rays depict the training of the neural network from the image maps for every EPE 215 through the pixelated 2D optical images 220, 225, and 230 thus providing as a predicted output from the trained models the EPE shift prediction 210.

[00104] Here there are three nodes corresponding to the pixelated 2D optical images 220, 225, and 230 and thus, for every spatial location, the neural network will have a simulated optical image which is then multiplied by each of the three kernels through a non-linear hyperbolic function to linearly combine each of the three neurons together to yield a scale of quantity representing the EPE shift prediction 210 needed as the output.

[00105] Figure 3 depicts several exemplary comparisons between trained models and actual SEM images in accordance with described embodiments. In particular, the pixelated images on the left may be compared with the actual SEM images on the right revealing similarities between the kernels of the trained models and the layout design.

[00106] As depicted here, the trained kernels are highly resonant with regard to specific layouts and geometries as the kernels of the trained models recognize specific building blocks of the layout which may be considered as analogous to a fuzzy pattern matching approach.

[00107] For instance, in the first row of images there is depicted a donut geometry 310 at element 325 within the Scanning Electron Microscope (SEM) image on the right which has a similar and corresponding donut geometry 310 revealed within the trained model on the left. On the second row of images there is depicted a stair step geometry 315 at element 330 within the SEM image on the right which has a similar and corresponding donut stair step geometry 315 revealed within the trained model on the left. Lastly, at the third row of images there is depicted multiple offset plugs 320 at elements 335 and 340 within the SEM image on the right which has a similar and corresponding set of offset plugs 320 revealed within the trained model on the left.

[00108] Once trained, the models are utilized to correct the reticle to precisely align with the desired design target. While prior solutions utilized a limited subset of features extracted from the semi-physical model here the full 2D simulated optical image around each spatial location may be utilized for greater precision due to the richer feature set having greater information density capable of generating improved Edge Placement Error (EPE) predictions.

[00109] Here the model predictions are depicted on the left and the actual underlying SEM images resulting from the photolithographic SED and post SED processes are depicted on the right with the model's predicted contours overlaid atop the SEM images so as to show the closeness of the model predictions. The model learns the necessary weights from inputs provided and those weights are then utilized to act upon the input optical images from the semi-physical model to produce a result which is, in many ways, similar to the actual geometries and features produced on a wafer.

[00110] In accordance with described embodiments, the simulated 2D optical image maps shown on the left incorporate information about the local geometrical context for every feature. For instance, contextual information regarding nested isolated structures/features and nearest neighbor influence is embedded within the corrected mask and the optical source. Such factors have been demonstrably shown to influence the OPC model error and post-SED process biases. Inclusion of such contextual information regarding the features improves the trained model's EPE prediction improvement by more than 40% EPE over currently known baseline semi-physical OPC modeling methodologies and EPE prediction improvement exceeding 50% for post-SED process data is obtained when compared with an assumed constant post-SED bias.

[00111] According to certain embodiments, a 2D optical image of every edge is utilized to train an Artificial Neural Network (ANN) via which the training leads to the formulation of a transfer function which outputs a predicted EPE shift value which reduces the OPC model error and post-SED process bias at that specific edge location.

[00112] According to described embodiments, once the models are trained, either a model error or a post-SED bias compensation is calculated for every spatial location starting from its corresponding optical image map to reduce the OPC model error and post-SED process bias.

[00113] One way to provide the 2D optical information to the artificial neural network for the purpose of training is to flatten out the input image into a one-dimensional (ID) array, however, doing so causes the neural network to lose some information about spatial relationships between neighboring pixels subsequent to flattening the 2D images into the ID array.

[00114] Therefore, two techniques were developed in order to impose the 2D nature of the inputs into the artificial neural network. Firstly, the neuron kernels are smoothed out by averaging over the topologically of neighboring pixels during training, thus feeding a 2D structure into to the neural network. Secondly, "spatial-regularization" is imposed upon the models by configuring constraints requiring that the neural networks must predict similar results if the 2D images are shifted in the x or the y direction by a small amount, such as shifting in the x or y direction by less than a configurable threshold amount, thus establishing the 2D topology relationship.

100115] Such constraints additionally cause the model to generate smoothly varying predictions and reduce numerical noise and instability during OPC which further improves the utility and precision of the predictions output by the trained models.

[00116] Application of the described methodologies for the postSED data has been demonstrated to correctly explain even extreme variation of etch bias from pattern to pattern.

[00117] Figure 4A depicts exemplary post-SED model performance 401 for specific geometries in accordance with described embodiments. For instance, as can be seen here, SEM image 430 includes a feature with a large variation in holeEtch bias resulting in the 20nm/edge etch bias 420 depicted. Within the SEM image 430 there is overlaid the various contour positions including the thick outer line showing the contour of the semi-physical model 405, with the dashed middle line depicting the counter predicted by the simple MERLN model 410 and lastly, the inner most line depicting the adjusted contour 415 in accordance with the methodologies as described herein. Notably, the adjusted contour 415 adheres most closely with the actual SEM image 430 feature, thus providing a very precise match.

[00118] Similarly, the bottom SEM image 435 depicts a feature having a 7.5 nm/edge etch bias 425 in which, as before, the thick outermost line depicts the contour of the semi- physical model 405, with the dashed middle line depicting the counter predicted by the simple MERLN model 410 and the inner most line depicting the adjusted contour 415 which adheres very closely to the actual SEM image 430 feature.

[00119] Thus, as applied, the described methodology is able to accurately describe patterns that the conventionally known OPC models simply cannot capture.

[00120] SEM images 430 and 435 represent different amount of edge bias from the DCCD location in which SEM image 430 exhibits a relatively large etch bias and the SEM image 435 on the bottom exhibiting a much smaller etch bias. Regardless, the differing etch biases may nevertheless be captured and understood by the trained model such that different structures which will exhibit different etch biases will nevertheless be accurately represented by the models' output predictions.

[00121] Figure 4B depicts another exemplary post-SED model performance 402 for specific geometries in accordance with described embodiments.

[00122] Here, the SEM image 445 depicts a feature having an 8.7 nm/edge improvement

440 as shown by the adjusted contour's 415 adhesion or compliance with the SEM image features. Despite the simple MERLN model 410 results being significantly better than the baseline contour provided by the semi-physical model 405, the results of the simple MERLN 410 simply are insufficiently precise in certain areas and with certain geometries when dealing with next generation feature sizes which require stricter and tighter design tolerances than necessitated by previous product lines.

[00123] Whereas the patterns and geometries depicted at Figure 4A represented expected features for the model, the features and geometries at Figure 4B conversely represent patterns having a large variation in holeEtch bias which the conventional semi-physical models simply are not able to fit via their prediction outputs when compared with actual SEM image 445 data. However, as can be seen, the adjusted contour 415 of the improved MERLN2d model does adheres extremely well to the shape of the unexpected features and geometries, thus providing for reduced error and greater compliance with design tolerances.

[00124] Figure 5 depicts a comparison 501 between Cartesian and polar model inputs in accordance with described embodiments.

[00125] As shown here, the Cartesian model inputs produce the contour jaggedness of the semi-physical model contour 505 close to the corner 520 whereas the polar model inputs used to produce the adjusted contour 515 results in a non-jagged and much smoother contour at the corner 520.

[00126] In accordance with certain embodiments, the orientation of the 2D image maps used for model training is aligned along the simulated optical intensity gradient direction which enforces the physical property of rotational symmetry of the model. However, the rotating image box scheme introduces certain numerical instability issues, especially around sharp corners 520 of the model contours, as may be observed by the sharp correction by the semi-physical model contour 505 as it rounds the corner 520.

[00127] Therefore, so as to resolve the problem of numerical instability, the polar basis is utilized rather than Cartesian basis as input features, such that the input parameters by construct vary smoothly along sharp corners 520 as may be observed by the adjusted contour 515 rounding the corner 520 in a much smoother flow without any sharp correction. [00128] The comparison SOI shown here using Cartesian inputs versus polar inputs reveals greatly improved numerical stability with the adjusted contour 515 in terms of undesirable contour jaggedness over the non-adjusted semi-physical model contour 505.

Physically, the adjusted model should also satisfy mirror symmetry such that when the layout is mirrored, the adjusted model should predict exactly the mirrored contours. Therefore, so as to enforce such symmetry, it is in accordance with certain embodiments that an unconventional neuron symTanh algorithm is applied in which the even and odd features are separated out so as to generate a symmetrized result as an output. According to such an embodiment, the symTanh neuron enforces the symmetry property of the model.

|00129] Laboratory results show that without the application of the symTanh neuron to the model, the model's predictions for critical dimensions (CD) of features and geometries may vary by as much 5nm when mirroring the layout. Conversely, when the symTanh neuron is applied to the model, variation of critical dimensions for those same features and geometries drops to a drastically improved 0.2nm; a near-zero result which reflects the remains of other numerical noise in the tool.

[00130] Figure 6 depicts an exemplary simulated 2D optical image map 601 in accordance with described embodiments. As shown here, the solid black dots represent inputs 620, to a Convolutional Neural Network (CNN) which rasters a common set of weights (e.g. kernels) across the image to generate a reduced map 635. According to such embodiments, the process is applied over successive levels using different weights, such as until a final estimate is produced resulting in the final output 630.

[00131] For instance, here the many input 620 dots are utilized with a first layer of common weights 605 which converge into the reduced map 635 which is made up of the hidden layer 6225 white dots (beneath the second layer weights 610.) The process is then repeated for the reduced map 635 using the second layer of weights 610 causing the reduced map 635 to converge or reduce into the final output 630 as shown. According to certain embodiments, multiple channels may additionally be utilized at each level of processing, and there may be more than simply the two levels of processing which are illustrated here.

[00132] According to described embodiments, use of the 2D optical information within the model permits the utilization of more sophisticated forms of machine learning than available with previously known techniques, such as the use of Convolutional Neural Networks (CNNs).

[00133] Convolutional type neural networks enforce a spatial interpretation in network construction so as to achieve similar fit improvements attainable with other artificial neural networks but with fewer fitting parameters, thus effectively pruning degenerate input with a minimal loss of signal.

100134] According to certain embodiments, detailed information from the 2D pixelated image maps is input to the neural networks to train the models. Because the size of the data table used for training may be extremely large there is a corresponding computational and computing infrastructure burden which stresses available resources such as available disk space and memory space which in turn negatively affects training time.

[00135] For instance, it has been observed that training with 21x21 pixelated images results in an input data table upwards of 16GB in size which in turn requires approximately —80GB memory and approximately one full week for training.

|00136] So as to improve computational efficiencies and reduce total training times, it is therefore in accordance with certain embodiments that a Principle-Component- Analysis (PCA) methodology is applied so as to reduce the number of input parameters from, for example, 441 input parameters to merely 12 input parameters. Such an approach thus reduces the data table size to a much more manageable -500MB and reduces training time from approximately one week to 2—3 hours with the memory consumption of—3GB.

[00137] In accordance with described embodiments, the methodologies may additionally be applied to the creation of existing reticles.

[00138] Using such methodologies, the OPC Model accuracy will directly translate to accuracy of feature sizes on wafer. Stated differently, utilizing such methodologies, the predicted contours and feature sizes, positions, and geometries are accurately represented within the OPC model and that accuracy corresponds well to the physically produced silicon wafer.

[00139] Where systematic OPC Model errors exist, the systemic errors will be replicated on the photomask, will be replicated in lithographic patterning, and will ultimately be replicated in the final circuit elements.

[00140] Should any device features deviate significantly from design specifications then such features will likely manifest as severe yield loss, or as complete circuit failure. It is for this reason that OPC Model errors be reduced as much as possible and that any such errors satisfy a minimum accuracy threshold so as to enable process development and learning. Without reaching the minimum accuracy threshold, technology development is impaired or halted while new plates are created in an attempt to address errors discovered on fabricated wafers.

[00141] Practice of the disclosed methodologies result in a powerful new technique to improve OPC model fidelity to a sufficient degree to enable process development on next generation lOnm nodes and beyond. Such fidelity simply is not feasible via previously known models yet is necessary in furtherance of Moore's law through decreased feature sizes and reduced design tolerances.

100142] In such a way a reduction technique is applied to the data permitting, for example, a reduction from 16 GB down to 3 GB and a reduction in processing time from an exemplary three days down to approximately three hours.

[00143] Such a reduction permits an acceptable trade off between potentially improved predictability using die higher fidelity data and the longer processing times with acceptable levels of predictability and significantly reduced processing times due to the vast reduction of data and parameters required to be processed.

[00144] Notwithstanding any reduction of data, certain constraints or requirements must remain for the model. For instance, according to one embodiment, a symmetry requirement is imposed upon the model such that physical rotation of a holder in which the physical

photolithographic mask is held will yield a corresponding rotation of the features and geometries of the model both from the prediction process but additionally from a simple rotation of the model's output. Similarly, inputting a photolithographic mask upside down (e.g., rotated by 180 degrees) should result in model predictions that are similarly rotated by 180 degrees from a model prediction based on a photolithographic mask which is input right-side up. However, while such a result seems naturally intuitive, the reality is that without such a constraint, the neural network does not necessarily produce outputs and predictions which are symmetrical in such a way.

[00145] Therefore, a symmetry requirement is applied to the architecture of the neural network such that any imagery map may be rotated according to the EPE in any direction and the trained models will yield the same consistent prediction outputs for all features and geometries.

100146] Similarly, the model is constrained such that if the photolithographic mask is flipped over, not just rotated by 180 degrees, then again, the output predictions should be the same and should be rotatable in any direction and also rotatable on any plane.

[00147] According to one embodiment, alignment of the direction of the image map is aligned with direction of the EPE by rotating the physical photolithographic mask such that the trained models may internally develop algorithms which yield consistent predictive results no matter the direction or orientation of the photolithographic mask.

[00148] According to another embodiment, symmetry is attained through a multistep process in which the model is permitted to output asymmetric results such that many parts of the predicted output align whereas other parts are asymmetric and therefore do not align. For instance, one set of model results from a photolithographic mask which is flipped and another set of results from the same photolithographic mask that is not flipped. [00149] The asymmetric results are then processed through a symmetry function by the neural network which takes the asymmetric parts and identifies the necessary adjustments or algorithmic corrections to make them align when the flipped prediction is flipped again to be the same as the non-flipped results or conversely, by aligning the non-flipped predictive results with the predictive results for the flipped photolithographic mask when those results are flipped yet again. Thus, according to one embodiment, the neural network accepts as input for the purposes of training the same photolithographic mask both flipped and non-flipped, and the neural network is required to output predictions for which symmetry exists between both the flipped and non-flipped inputs.

100150] Stated differently, after passing through the equation or algorithm developed by the neural network, both the flipped and non-flipped predictive results will be identical or within a threshold margin of error (e.g., a very small deviation attributable to noise in the data) when converted back and forth between flipped and non-flipped.

(00151] According to such an embodiment, symmetry is imposed upon the trained models and the output predictions of the trained models via a symTanh algorithm applied to even and odd features yield a symmetric result.

[00152] According to another embodiment, each block of input is rotated and the symTanh algorithm is then executed against the rotated block. For instance, the symTanh algorithm may be executed against each of the input 620 block after rotation and again executed against the hidden layer 62S block after rotation, resulting in the symmetry compliant and reduced final output 630.

[00153] Figure 7 is a schematic of a computer system 700 in accordance with described embodiments. The computer system 700 (also referred to as the electronic system 700) as depicted can embody means for implementing Optical Proximity Correction (OPC) modeling via machine learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED processes, according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system 700 may be a mobile device such as a net-book computer. The computer system 700 may be a mobile device such as a wireless smartphone or tablet. The computer system 700 may be a desktop computer. The computer system 700 may be a hand-held reader. The computer system 700 may be a server system. The computer system 700 may be a supercomputer or high-performance computing system.

[00154] In accordance with one embodiment, the electronic system 700 is a computer system that includes a system bus 720 to electrically couple the various components of the electronic system 700. The system bus 720 is a single bus or any combination of busses according to various embodiments. The electronic system 700 includes a voltage source 730 that provides power to the integrated circuit 710. In some embodiments, the voltage source 730 supplies current to the integrated circuit 710 through the system bus 720.

[00155] Such an integrated circuit 710 is electrically coupled to the system bus 720 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 710 includes a processor 712 that can be of any type. As used herein, the processor 712 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 712 includes, or is coupled with, electrical devices having gradient encapsulant protection, as disclosed herein.

100156| In accordance with one embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 710 are a custom circuit or an application-specific integrated circuit (ASIC), such as a

communications circuit 714 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 710 includes on-die memory 716 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 710 includes embedded on-die memory 716 such as embedded dynamic random-access memory (eDRAM).

[00157] In accordance with one embodiment, the integrated circuit 710 is complemented with a subsequent integrated circuit 71 1. Useful embodiments include a dual processor 713 and a dual communications circuit 715 and dual on-die memory 717 such as SRAM. In accordance with one embodiment, the dual integrated circuit 710 includes embedded on-die memory 717 such as eDRAM.

[00158] In one embodiment, the electronic system 700 also includes an external memory

740 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 742 in the form of RAM, one or more hard drives 744, and/or one or more drives that handle removable media 746, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 740 may also be embedded memory 748 such as the first die in a die stack, according to an embodiment.

[00159] In accordance with one embodiment, the electronic system 700 also includes a display device 750 and an audio output 760. In one embodiment, the electronic system 700 includes an input device 770 such as a controller that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 700. In an embodiment, an input device 770 is a camera. In an embodiment, an input device 770 is a digital sound recorder. In an embodiment, an input device 770 is a camera and a digital sound recorder.

[00160] As shown herein, the integrated circuit 710 can be implemented in a number of different embodiments, including means for implementing Optical Proximity Correction (OPC) modeling via machine learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED processes for a semiconductor substrate package, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate or a semiconductor package having therein means for implementing Optical Proximity Correction (OPC) modeling via machine teaming on simulated 2D optical images for Spin Exposure Develop (SED) and post SED processes, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates and semiconductor packages having means for implementing Optical Proximity Correction (OPC) modeling via machine learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED processes for semiconductor substrate package embodiments and their equivalents. A foundation substrate 798 may be included, as represented by the dashed line of Figure 7. Passive devices 799 may also be included, as is also depicted in Figure 7.

[00161] Figure 8 illustrates a semiconductor device 800 (or an interposer) that includes one or more described embodiments. The interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.

[00162] The interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[00163] The interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812. The interposer 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. In accordance with described embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.

[00164] Figure 9 illustrates a computing device 900 in accordance with one

implementation of the invention. The computing device 900 houses a board 902. The board 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

[00165] Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[00166] The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[00167] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[00168] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS- FET transistors built in accordance with implementations of the invention.

|00169] In further implementations, another component housed within the computing device 900 may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

[00170] In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

[00171] Figure 10 is a flow diagram illustrating a method 1000 for reducing Optical Proximity Correction (OPC) model error via machine learning on simulated 2D optical images for Spin Exposure Develop (SED) and post SED processes in accordance with described embodiments. Some of the blocks and/or operations listed below are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Additionally, operations from method 1000 may be utilized in a variety of combinations.

[00172] At block 1005, the method 1000 for reducing Optical Proximity Correction

(OPC) model error by the operates via the following processes.

[00173] At block 1010, the method includes creating a mask via a lithography process.

[00174] At block 1015, the method includes fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask.

|00175| At block 1020, the method includes creating a semi-physical model of the mask using physical parameters of die lithography process used to create the mask, the semi-physical model specifying optical intensity values representing the plurality of features of the mask.

[00176] At block 1025, the method includes capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer.

[00177] At block 1030, the method includes quantifying differences between (a) the features of the mask as represented by the optical intensity values within the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images.

[00178] At block 1035, the method includes shifting contours of the plurality of features of the mask as represented by the optical intensity values within the semi-physical model based on the quantified differences.

100179] While the subject matter disclosed herein has been described by way of example and in terms of the specific embodiments, it is to be understood that the claimed embodiments are not limited to the explicitly enumerated embodiments disclosed. To the contrary, the disclosure is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosed subject matter is therefore to be determined in reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[00180] It is therefore in accordance with the described embodiments, that: [00181] According to one embodiment there is a method for reducing Optical Proximity Correction (OPC) model error, in which the method includes: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi- physical model specifying optical intensity values representing the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the features of the mask as represented by the optical intensity values within the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting contours of the plurality of features of the mask as represented by the optical intensity values within the semi-physical model based on the quantified differences.

[00182] According to another embodiment of the method, creating the semi-physical model of the mask using physical parameters of the lithography process used to create the mask includes capturing optical intensity values from a light source shone through a photolithographic mask, in which the semi-physical model specifies the optical intensity values representing the plurality of features of the mask as captured from the light source when shone through the photolithographic mask.

[00183] According to another embodiment, the method further includes: generating two- dimensional (2D) simulated images from the semi-physical model of the mask including the optical intensity values representing the plurality of features of the mask.

[00184] According to another embodiment of the method, creating the semi-physical model of the mask using physical parameters of the lithography process used to create the mask, includes pixelating the optical intensity values representing the plurality of features of the mask from a light source shone through the mask.

[00185] According to another embodiment, the method further includes: generating two- dimensional (2D) simulated images from the semi-physical model of the mask including optical intensity values representing the plurality of features of the mask; and pixelating the 2D simulated images to create pixelated 2D simulated images including pixelated optical intensity values representing the plurality of features of the mask.

[00186] According to another embodiment, the method further includes: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the plurality of features of the mask as specified by the semi-physical model. [00187] According to another embodiment of the method, the neural network includes one of: an Artificial Neural Network (ANN) to algorithmically fit the contours of the plurality of features of the mask to corresponding contours of the plurality of features embodied within the physical silicon wafer as captured by the SEM images; or a Convolutional Neural Network (CNN) to raster a common set of weights across an image map formed from the optical intensity values representing the plurality of features of the mask to generate a reduced map; and in which the method further includes training the neural network to output offset predictions to be applied to any one of a plurality of new semi-physical models via Optical Proximity Correction (OPC).

[00188] According to another embodiment of the method, training the neural network includes at least: inputting the optical intensity values representing the plurality of features of the mask into the neural network; and inputting physical measurements of the plurality of features embodied within the physical silicon wafer as captured from the SEM images.

[00189] According to another embodiment of the method, training the neural network includes: identifying deltas between contours of the plurality of features embodied within the physical silicon wafer as captured by the SEM images and corresponding contours of the plurality of features of the mask as specified by the semi-physical model; and fitting the deltas between the semi-physical model and measurements taken from the physical silicon wafer as captured by the SEM images.

[00190] According to another embodiment, the method further includes: pixelating the optical intensity values representing the plurality of features of the mask to form simulated pixelated 2D optical images; and combining the deltas with the simulated pixelated 2D optical images to estimate Edge Placement Error (EPE) between the contours of the plurality of features of the mask as specified by the semi-physical model and the corresponding contours of the plurality of features embodied within the physical silicon wafer as captured by the SEM images.

[00191] According to another embodiment of the method, fitting the deltas includes adjusting the contours of the plurality of features of the mask as specified by the semi-physical model to match the corresponding contours of the plurality of features embodied within the physical silicon wafer as captured by the SEM images.

[00192] According to another embodiment, the method further includes: outputting contour adjustment predictions from the trained neural network defining offsets to the contours of the plurality of features of the mask as specified by the semi-physical model; and applying the offsets to the semi-physical model via Optical Proximity Correction (OPC) to reduce OPC model error of the semi-physical model.

[00193] According to another embodiment, the method further includes: creating a new semi-physical model of a new mask using physical parameters of the lithography process used to create the new mask, the new semi-physical model specifying optical intensity values

representing a new plurality of features of the new mask; outputting contour adjustment predictions from the trained neural network defining offsets to contours of the new plurality of features of the new mask as specified by the new semi-physical model; and applying the offsets to the new semi-physical model via Optical Proximity Correction (OPC) to reduce OPC model error of the new semi-physical model.

[00194] According to another embodiment, the method further includes: pixelating the optical intensity values representing the plurality of features of the mask from a light source shone through the mask to generate simulated pixelated 2D optical images representing the features of the mask as specified by the semi-physical model; flattening the simulated pixelated 2D optical images into a one-dimensional (ID) array.

[00195] According to another embodiment of the method, flattening the simulated pixelated 2D optical images into the one-dimensional (ID) array includes applying spatial- regularization to the simulated pixelated 2D optical images.

[00196] According to another embodiment, the method further includes: pixelating the optical intensity values representing the plurality of features of the mask from a light source shone through the mask to form pixelated 2D simulated image maps representing the plurality of features of the mask; and iteratively rasterizing one or more sets of weights across the pixelated 2D simulated image maps to generate a reduced image map.

[00197] According to another embodiment, the method further includes: rotating the mask by 180 degrees; capturing new optical intensity values representing the plurality of features of the mask rotated 180 degrees; and in which training the neural network further includes requiring the neural network to enforce symmetry between the optical intensity values representing the plurality of features of the mask before rotation and the new optical intensity values representing the plurality of features of the mask rotated 180 degrees.

[00198] According to another embodiment of the method, training the neural network includes: inputting a simulated 2D optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model and an optical transfer function; and in which the trained neural network generates a deterministic relationship between the layout of the contours of the plurality of features of the mask as specified by the semi-physical model and the quantified differences.

[00199] According to another embodiment of the method, the neural network generates an equation Function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and in which the neural network generates a new model of the mask specifying the contours of the plurality of features of the mask shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.

[00200] According to another embodiment, the method further includes: using the new model generated by the trained neural network to predict new mask features based on a predicted contour shift generated by the trained neural network to contours of the new mask features as determined by the semi-physical model.

[00201] According to another embodiment of the method, quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images includes: collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the mask as specified by the semi-physical model to determine the differences.

[00202] According to another embodiment of the method, quantifying differences includes: measuring critical dimensions of the features embodied by the physical silicon wafer from thousands of the SEM images captured, in which the measuring of the critical dimensions includes measuring at each of a plurality of target points along the contours of the plurality of features of the mask as specified by the semi-physical model and comparing to the plurality of features embodied by the physical silicon wafer to generate millions of data points quantifying the differences between the SEM images and the semi-physical model.

[00203] According to yet another embodiment, there is a system which is configured to reduce Optical Proximity Correction (OPC) model error, in which the system includes: a mask created via a lithography process; a physical silicon wafer having been fabricated using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; a semi-physical model of the mask created using physical parameters of the lithography process used to create the mask, the semi-physical model specifying optical intensity values representing the plurality of features of the mask; storage to capture Scanning Electron

Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; an analysis unit to quantify differences between (a) the features of the mask as represented by the optical intensity values within the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and the analysis unit to shift contours of the plurality of features of the mask as represented by the optical intensity values within the semi-physical model based on the quantified differences.

[00204] According to another embodiment of the system, the analysis unit is to further generate two-dimensional (2D) simulated images from the semi-physical model of the mask including optical intensity values representing the plurality of features of the mask; and in which the analysis unit is to further pixelate the 2D simulated images to create pixelated 2D simulated images including pixelated optical intensity values representing the plurality of features of the mask.

[00205] According to another embodiment of the system, the analysis unit is to further train a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the plurality of features of the mask as specified by the semi-physical model.

[00206] According to yet another embodiment, there is a non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, in which operations include: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi- physical model specifying optical intensity values representing the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the features of the mask as represented by the optical intensity values within the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting contours of the plurality of features of the mask as represented by the optical intensity values within the semi-physical model based on the quantified differences.

[00207] According to another embodiment of the non-transitory computer readable media, the instructions cause the processor to perform operations further including generating two-dimensional (2D) simulated images from the semi-physical model of the mask including optical intensity values representing the plurality of features of the mask; and pixelating the 2D simulated images to create pixelated 2D simulated images including pixelated optical intensity values representing the plurality of features of the mask.

100208] According to another embodiment of the non-transitory computer readable media, the instructions cause the processor to perform operations further including: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the plurality of features of the mask as specified by the semi-physical model.