Technical Field

[0001] The present disclosure relates to formation of integrated chips and more specifically to an etching process.

Background

[0002] Semiconductor integrated chips can be fabricated in a process that includes imaging, deposition and etching. Additional steps can include doping and cleaning. Wafers (such as mono-crystal silicon wafers, silicon on sapphire wafers or gallium arsenide wafers) can be used as a substrate. Photolithography can be used to mark areas of the wafer for

enhancement through doping or deposition. An integrated circuit is composed of a plurality of layers which can include diffusion layers (which can include dopants), implant layers (which can include additional ions), metal layers (defining conduction) and/or via or contact layers (which can define conduction between layers).

Brief Description of the Drawings

[0003] FIG. 1 is a diagram illustrating a set of layers during an etch process consistent with embodiments disclosed herein.

[0004] FIG. 2 is a graph illustrating a mass signal over time that corresponds with the etch process shown in FIG. 1 consistent with embodiments disclosed herein.

[0005] FIG. 3 is a graph showing a mass spectral signal from a SiHF ₃ ion as an Si0 ₂ layer is etched away on a wafer consistent with embodiments disclosed herein.

[0006] FIG. 4 is a graph illustrating a reading from a mass spectrometer consistent with embodiments disclosed herein.

[0007] FIG. 5 illustrates an interposer consistent with embodiments disclosed herein.

[0008] FIG. 6 illustrates a computing device consistent with embodiments disclosed herein.

[0009] FIG. 7 is a flow chart illustrating a method for etching control consistent with embodiments disclosed herein.

[0010] FIG. 8 is a block diagram illustrating a system for etching control consistent with embodiments disclosed herein. Detailed Description

[0011] Described herein are systems and methods of using isotopically enriched film precursors or etch reagents in conjunction with mass spectroscopic detection of the etch reaction products to enable precise etch endpoint control. The etch apparatus can etch to a precise predetermined depth set by a depth of an isotopically enriched layer(s) regardless of incoming process variation. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0012] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention; however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0013] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0014] Implementations of the invention may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.

[0015] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the invention may also be carried out using nonplanar transistors.

[0016] Each MOS transistor includes a gate stack formed of at least two layers: a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0 ₂ ) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0017] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0018] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an MOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0019] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0020] In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, or silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0021] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternative semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0022] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 ₂ ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as

silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0023] Layers of materials enriched with chemical isotopes can delineate boundaries between materials in a semiconductor process. During an etch process, these boundary layers are removed by chemical reactions, giving rise to volatile reaction products. By using a mass spectrometer attached to the etch chamber to monitor the concentration of isotopically labeled compounds in the reaction products, the system can determine that the desired etch depth has been achieved and terminate the etch process.

[0024] Current methods of etch endpointing may not be as chemically specific or sensitive as mass spectrometry. This lack of specificity and/or sensitivity can lead to an inability to stop the etch process on a precise composition or material depth. For example, optical emission endpointing lacks a chemical specificity to perform this function. In contrast, a combination of mass spectrometry and isotopically enriched thin film layers can enable precise chemically determined etch depth.

[0025] FIG. 1 shows one implementation of the isotopically enriched layer that resides below the layer to be etched. The mass signal(s) from the isotopically enriched layer is monitored over time. When the mass signal from the enriched layer begins to abate and vanishes the etch is stopped.

[0026] In the embodiment shown in FIG. 1, a time period T ₀ represents the initial state of the material stack to be etched. Time T ₁ corresponds to the introduction of the etch reactants or plasma ignition. Times T ₂ and T ₃ show the initial removal of the layer to be etched by the etchant reagents. By time T ₄ , the etched layer is sufficiently removed by the etch reagents such that the first few molecules of the isotopically enriched layer are volatilized from the layer, which leads to a rise in the mass spectral signal for the enriched isotope layer. At time T ₅ , the enriched layer is fully involved and the mass signal has plateaued. As the enriched layer is removed the enriched isotope signal decays away, indicating that the etch has reached completion at time T ₆ .

[0027] The principle of detecting an indicator within an indicator layer (such as an isotropically enhanced layer) can be used with multiple different etching processes. Etching processes can include plasma etching, atomic layer etching, vapor etching or wet etching. A detector coupled to an etching chamber can include a mass spectrometer, mass spectrometric detection of the output of a chromatography column or a gas or liquid chromatography or other separation column preceding a mass spectrometer. The mass spectrometer can be configured to sample a gas medium comprising residual indicator material from the etching process. The liquid chromatograph can be configured to sample a liquid medium comprising residual indicator material from the etching process, which can be run through a mass spectrometer. A liquid etchant medium can also be sampled and atomized directly into a mass spectrometer without preceding chromatographic separation.

[0028] Using an isotropically enhanced layer can provide a benefit of having a similar chemical and physical reaction as the substrate or etch layer, while being detectable. For example, when the indicator layer is similar to the etch layer, a similar chemical reactivity can allow the etch process to smoothly transition from the etch layer to the indicator layer. When the indicator layer is similar to the substrate layer, a similar chemical reactivity or physical characteristics can allow the indicator layer to behave similarly to the substrate layer (e.g., similar doping characteristics, etc.).

[0029] FIG. 2 is a graph 200 illustrating a mass signal over time that corresponds with the etch process shown in FIG. 1. The x-axis is time and the y-axis is mass signal. The mass signal from the enriched layer is plotted versus time to show how it could be used for an endpointing signal for an etch. The etch can be stopped at different points in time. For example, the etch process can be stopped at a rising edge, such as shown at T ₄ . This can, for example, be used to avoid fully removing the indicator layer. In another example, the etch process can be stopped after a transition point or plateau as shown at time T ₅ . In one example the etch process can be stopped on a falling edge, such as shown between times T ₅ and T ₆ . In another embodiment, the etch process can stopped after a threshold is reached or exceeded. For example, the threshold can be the background mass signal measurement shown in time T ₀ , T ₁ or others. The threshold can also be the time or mass signal between T ₄ and T ₅ or between T ₅ and T ₆ . [0030] FIGs. 3 and 4 show example data of an etching process using mass spectroscopy to determine an etching endpoint using an indicator. Measured mass spectra of a current etch process on natural abundance (non-enriched or natural concentration) materials demonstrate that mass spectrometry can resolve an etching of one material atop a substrate. FIG. 3 is a graph 300 showing a mass spectral signal from a SiHF ₃ ion as an Si0 ₂ layer is etched away on a wafer.

[0031] FIG. 4 shows a reading from a mass spectrometer. For example, if a bottom few nm of an indicator layer were isotopically enriched in 29Si instead of a predominant natural isotope of 28Si then an 89 amu peak (not shown) would grow in time as the endpoint was reached as the 88 amu peak (shown) was decreasing. A noise threshold 402 is shown, above which measurements are noted.

[0032] The indicator and process can be further modified to include multiple indicators and/or structures. In one embodiment, double labeling and/or multiple labeling can be used for spatially resolving which indicator layers are being etched different rates. For example, a top of a 3-dimensional structure such as a trench can be labeled with a first isotope, the bottom material with a second isotope and the walls with a third isotope. Relative rates of evolution of isotopically labeled products (e.g., levels of indicators or indicator derived products) can indicate relative etch rates for the various components of the structure.

Another example includes labeling a backbone pattern with a first indicator, a spacer surrounding this "mandrel" backbone layer with a second indicator and the intervening regions with a third indicator. Relative etch rates can be used to optimize a spacer etch, for example.

[0033] This additional indicator concept can be further generalized. For example, a pattern of carbon hard mask fins (CxHyOz) can be used on a silicon nitride substrate (Si ₃ N ₄ ) with an oxide spacer. The oxide is labeled with 29-Si, the nitride labeled with 15-N, and the spacer made of an organic material enriched with 13-C. The mass signals from all 3 structures yields information about relative etch rates of each structure. Fourier-transform ion-trap mass spectrometry can allow for simultaneous observation of all 3 isotopes.

[0034] FIG. 5 illustrates an interposer 500 that includes one or more embodiments of the invention. The interposer 500 is an intervening substrate used to bridge a first substrate 502 to a second substrate 504. The first substrate 502 may be, for instance, an integrated circuit die. The second substrate 504 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 500 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, the interposer 500 may couple an integrated circuit die to a ball grid array (BGA) 506 that can subsequently be coupled to the second substrate 504. In some embodiments, the first and second substrates 502/504 are attached to opposing sides of the interposer 500. In other embodiments, the first and second substrates 502/504 are attached to the same side of the interposer 500. And in further embodiments, three or more substrates are interconnected by way of the interposer 500.

[0035] The interposer 500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer 500 may be formed of alternative rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[0036] The interposer 500 may include metal interconnects 508 and vias 510, including, but not limited to, through-silicon vias (TSVs) 512. The interposer 500 may further include embedded devices 514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 500.

[0037] In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of the interposer 500.

[0038] FIG. 6 illustrates a computing device 600 in accordance with one embodiment of the invention. The computing device 600 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternative embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 600 include, but are not limited to, an integrated circuit die 602 and at least one

communications logic unit 608. In some implementations the communications logic unit 608 is fabricated within the integrated circuit die 602 while in other implementations the communications logic unit 608 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 602. The integrated circuit die 602 may include a CPU 604 as well as on-die memory 606, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM). [0039] Computing device 600 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die.

These other components include, but are not limited to, volatile memory 610 (e.g., DRAM), non-volatile memory 612 (e.g., ROM or flash memory), a graphics processing unit 614 (GPU), a digital signal processor 616, a crypto processor 642 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 620, at least one antenna 622 (in some implementations two or more antenna may be used), a display or a touchscreen display 624, a touchscreen controller 626, a battery 629 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 628, a compass, a motion coprocessor or sensors 632 (that may include an

accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 634, a camera 636, user input devices 638 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 640 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 600 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some

implementations, the computing device 600 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 600 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

[0040] The communications logic unit 608 enables wireless communications for the transfer of data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The

communications logic unit 608 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 600 may include a plurality of communications logic units 608. For instance, a first communications logic unit 608 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 608 may be dedicated to longer range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0041] The processor 604 of the computing device 600 includes one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments of the invention using the method for etching control. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0042] The communications logic unit 608 may also include one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments of the etching process described herein.

[0043] In further embodiments, another component housed within the computing device 600 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the etching process described herein.

[0044] In various embodiments, the computing device 600 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a

dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other electronic device that processes data.

[0045] FIG. 7 is a flow chart illustrating a method 700 for etching control. The method 700 can be performed by systems on structures as described above including FIGs. 1 and 5-6. In block 702, an etching system starts an etching process of a material stack, the material stack comprising an etch layer, an indicator layer and a substrate layer, wherein the indicator layer comprises an indicator. In block 704, the etching system monitors a concentration of the indicator. In block 706, the etching system determines that the concentration of the indicator indicates the etching process has etched through the etch layer and has at least reached the indicator layer. In block 708, the etching system stops the etching process based at least in part on the determined concentration.

[0046] FIG. 8 is a block diagram illustrating a system for etching control. A material stack 806 including an indicator material can be placed in an etch chamber 804. The etch chamber 804 can include a chamber interface 812 that is coupled to a mass spectrometer 802. A processor 801 can be coupled to the etch chamber 804 and the mass spectrometer 802 through a detector interface 808. A processor 810 can control an etching process of the etch chamber 804 until the mass spectrometer 802 indicates over detector interface 808 that the mass spectrometer 802 detects an indicator level or indicator level over time that indicates the etching process is complete. When the processor 810 determines the etching process is complete, the processor 810 can stop the etching process in the etch chamber 804.

Examples

[0047] The following examples pertain to further embodiments.

[0048] Example 1 is set of layers for use in an etch chamber. The etch layer includes a first isotope of a first material to be removed during an etching process. The etch layer includes a substrate layer including a second isotope of a second material, and a the substrate layer designed to remain after the etching process. The etch layer includes an isotopically enriched layer including a third isotope and constructed between the etch layer and the substrate layer. The isotopically enriched layer includes an addition of the third isotope, where a

concentration of the third isotope within the isotopically enriched layer is higher than an expected background concentration due to the addition. The concentration of the third isotope provides an indicator during the etching process that indicates a stop point in the etching process designed to remove at least a portion of the etch layer.

[0049] Example 2 is the set of layers of Example 1, where the third isotope in the isotopically enriched layer is an isotope of the first material, providing a similar chemical response as the first material.

[0050] Example 3 is the set of layers of Example 1, where the third isotope in the isotopically enriched layer is an isotope of the second material, providing a similar chemical response as the second material.

[0051] Example 4 is the set of layers of Example 1, where the third isotope in the isotopically enriched layer is an isotope of a third material.

[0052] Example 5 is the set of layers of Example 1, where the second isotope of the first material is an isotope of nitrogen, silicon or carbon.

[0053] Example 6 is the set of layers of Example 1, where the second isotope of the first material exceeds a two times natural concentration within the isotopically enriched layer.

[0054] Example 7 is the set of layers of any of Examples 1-6, where the set of layers include a memory unit.

[0055] Example 8 is the set of layers of any of Examples 1-6, where the set of layers includes a processor. [0056] Example 9 is an apparatus of an etching system. The apparatus includes a detector interface attached to a detector monitoring an etching chamber. The detector interface is designed to process a message indicating a presence of an indicator material. The apparatus includes a processor attached to the detector interface. The processor is designed to start an etching process of a material stack, the material stack including an etch layer, an indicator layer and a substrate layer, where the indicator layer includes the indicator material. The processor processes the message indicating a concentration of the indicator material exceeds a threshold, the concentration above the threshold indicating the etching process has etched through the etch layer and has at least reached the indicator layer. The processor stops the etching process based at least in part on the message.

[0057] Example 10 is the apparatus of Example 9, where the concentration of the indicator material over time correlates with an etch depth over time.

[0058] Example 11 is the apparatus of Example 9, where to process the message further includes detecting a rise in a mass spectral signal for the indicator material due to volatizing of the indicator layer including the indicator material, the rise indicating the etching process having arrived at the indicator layer.

[0059] Example 12 is the apparatus of Example 9, where to process the message further includes detecting a plateau in a mass spectral signal for the indicator material due to volatizing of the indicator layer including the indicator material.

[0060] Example 13 is the apparatus of Example 9, where to process the message further further includes detecting a fall in a mass spectral signal for the indicator material due to volatizing of the indicator layer including the indicator material over time, the fall indicating the etching process having substantially etched through the indicator layer.

[0061] Example 14 is the apparatus of Example 9, where to process the message further includes detecting exceeding a threshold value in a mass spectral signal for the indicator material due to volatizing of the indicator layer including the indicator material.

[0062] Example 15 is the apparatus of Example 9, where the indicator layer includes an isotope of the etch layer or the substrate layer.

[0063] In Example 16, the apparatus of Example 9, further includes an etch delivery system.

[0064] Example 17 is the apparatus of Example 16, where the etch delivery system is designed for plasma etching, atomic layer etching, vapor etching or wet etching.

[0065] In Example 18, the apparatus of Example 9, further includes the detector.

[0066] Example 19 is the apparatus of Example 18, where the detector includes a liquid chromatograph. [0067] Example 20 is the apparatus of Example 19, where the liquid chromatograph is designed to sample a liquid medium for the indicator material.

[0068] Example 21 is the apparatus of Example 19, where the detector is a mass spectrometer is designed for mass spectrometric detection of the output of a chromatography column from the liquid chromatograph.

[0069] Example 22 is the apparatus of Example 18, where the detector is a mass

spectrometer.

[0070] Example 23 is the apparatus of Example 22, where the mass spectrometer is designed to sample a gas medium for the indicator material.

[0071] Example 24 is the apparatus of Example 22, where the mass spectrometer is designed for mass spectrometric detection of the output of a chromatography column

[0072] Example 25 is the apparatus of any of Examples 9-23, where to stop the etching process further includes a delay before stopping the etching process.

[0073] Example 26 is the apparatus of any of Examples 9-23, where the indicator material within the indicator layer is present in the concentration above a natural concentration.

[0074] Example 27 is a method of determining a stop point in an etch process. The method includes starting an etching process of a material stack, the material stack including an etch layer, an indicator layer and a substrate layer, where the indicator layer includes an indicator. The method includes monitoring a concentration of the indicator. The method includes determining that the concentration of the indicator indicates the etching process has etched through the etch layer and has at least reached the indicator layer. The method includes stopping the etching process based at least in part on the determined concentration.

[0075] Example 28 is the method of Example 27, where the concentration of the indicator correlates with etch depth.

[0076] Example 29 is the method of Example 27, where the indicator is an isotope of a material within the etch layer, the isotope having a similar chemistry of the material.

[0077] Example 30 is the method of Example 27, where the indicator is an isotope of a material within the substrate layer, the isotope having a similar chemistry of the material.

[0078] In Example 31, the method of Example 27, further includes depositing the indicator layer on the substrate layer, and depositing the etch layer on the indicator layer.

[0079] Example 32 is the method of Example 27, where to monitor the concentration of the indicator further includes to use mass spectrometric detection of an output of a

chromatography column to monitor a concentration of the indicator within a liquid medium within an etch chamber. [0080] Example 33 is the method of Example 27, where to monitor the concentration of the indicator further includes to use a mass spectrometer to monitor the concentration of the indicator within a gas medium within an etch chamber.

[0081] In Example 34, an apparatus includes a procedure to perform a method as exemplified in any of Examples 27-33.

[0082] In Example 35, a machine-readable storage includes machine-readable instructions, that when executed, implements a method or realizes an apparatus as exemplified in any of Examples 27-33.

[0083] Example 36 is a computing device. The computing device includes a processor mounted on a substrate, and a memory unit capable of storing data. The computing device includes a graphics processing unit, an antenna within the computing device, and a display on the computing device. The computing device includes a battery within the computing device, and a power amplifier within the processor. The computing device includes a voltage regulator within the processor where the processor includes an etch layer including a first isotope of a first material, the etch layer designed to be removed during an etching process. The processor further includes a substrate layer including a third isotope of a second material, the substrate layer designed to remain after the etching process. The processor also includes an isotopically enriched layer constructed between the etch layer and the substrate layer, including a second isotope of the first material or a second isotope of the second material, where a concentration of the second isotope within the isotopically enriched layer is higher than an expected natural concentration of the second isotope, the concentration of the second isotope providing an indicator during the etching process that indicates a stop point in the etching process.

[0084] Example 37 is the computing device of Example 36, where the concentration of the indicator correlates with etch depth.

[0085] Reference throughout this specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment of the present invention. Thus, appearances of the phrase "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0086] As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on its presentation in a common group without indications to the contrary. In addition, various embodiments and examples of the present invention may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations of the present invention.

[0087] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of materials, frequencies, sizes, lengths, widths, shapes, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[0088] It should be recognized that the systems described herein include descriptions of specific embodiments. These embodiments can be combined into single systems, partially combined into other systems, split into multiple systems or divided or combined in other ways. In addition, it is contemplated that parameters/attributes/aspects/etc. of one embodiment can be used in another embodiment. The parameters/attributes/aspects/etc. are merely described in one or more embodiments for clarity, and it is recognized that the parameters/attributes/aspects/etc. can be combined with or substituted for

parameters/attributes/etc. of another embodiment unless specifically disclaimed herein.

[0089] Although the foregoing has been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications may be made without departing from the principles thereof. It should be noted that there are many alternative ways of

implementing both the processes and apparatuses described herein. Accordingly, the present embodiments are to be considered illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

[0090] The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The scope of the present invention should, therefore, be determined only by the following claims.