Title:
SYSTEMS AND METHODS FOR DYNAMIC LOW LATENCY OPTIMIZATION
Document Type and Number:
WIPO Patent Application WO/2018/176507
Kind Code:
A1
Abstract:
Systems and methods which provide low latency optimization configured to perform from the hardware layer across the operating system to an application. Low latency operation implemented is optimized for a specific application, which interfaces with specific hardware, executing on a host processor-based system configured for low latency optimization according to the concepts herein. For example, a low latency optimization implementation may comprise various modules implemented in both the user space and Kernel space, wherein the modules cooperate to obtain information regarding the services and hardware utilized by an application and to provide such information for facilitating low latency operation with respect to the application. Low latency operation is dynamically enabled or disabled by a low latency optimization implementation, such as to facilitate low latency operation on an application by application basis as appropriate or as desired.
Inventors:
LO CHUN CHUNG (CN)
Application Number:
PCT/CN2017/080100
Publication Date:
October 04, 2018
Filing Date:
April 11, 2017
Export Citation:
Assignee:
HONG KONG APPLIED SCIENCE & TECH RESEARCH INST CO LTD (CN)
International Classes:
G06F11/32
Foreign References:
| US20140201357A1 | 2014-07-17 | |||
| CN101616194A | 2009-12-30 | |||
| CN104461730A | 2015-03-25 | |||
| CN104424034A | 2015-03-18 |
Attorney, Agent or Firm:
CHINA TRUER IP (CN)
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