1 . A multi-bank, dual-pipe SRAM device comprising:

(i) a memory array comprising a plurality of SRAM banks, each SRAM bank including a block of single port SRAM memory cells organized as a matrix of rows and columns, a decoder, a sense amplifier, and memory cell access circuitry, wherein each SRAM bank is capable of operating at a maximum frequency, f(m), and is configured for, and capable of, performing a read operation and a write operation together within a single f(m) clock cycle;

(ii) a read/write control input circuit that receives a read operation and a write operation within a single external clock cycle of frequency, f(e), and provides those read and write operations to each SRAM bank;

(iii) an address input circuit that receives a read address and a write address within a single external clock cycle of frequency, f(e)e and provides those read and write addresses to each SRAM bank;

(iv) a data input circuit that receives first and second beats of write data within a single external clock cycle of frequency, f(e), and provides those two beats of write data to each SRAM bank; and

(v) bank access circuitry at the plurality of SRAM banks, coupled to the read/write control input circuit, the address input circuit, and the data input circuit, that controls combinations of read and write operations to the SRAM banks at no greater than their maximum operating frequency, f(m);

wherein the external clock frequency, f(e), is at least twice the maximum frequency, f(m), that each SRAM bank is capable of operating at, and the read/write control circuity operates at the external clock frequency, f(e), and/or the address circuitry operates at the external clock frequency, f(e), and/or the data circuitry operates at the external clock frequency, f(e).

2. The device of claim 1 or any claim herein, wherein the address circuitry receives a read address and a write address, and is arranged and electrically coupled to split the read address into a first read address stream and a second read address stream, and split the write address into a first write address stream and a second write address stream; and

wherein the address input pipeline circuit further comprises a first address input pipeline and a second address input pipeline coupled between the address circuitry and the plurality of SRAM banks, the first address pipeline and the second address pipeline configure to bus read address information that has been split and write address information that has been split to the plurality of SRAM banks, wherein each of the address input pipelines operate at half-frequency of input clock frequency;

wherein the data circuitry is arranged and connected to:

split the beat one write data into a first half-frequency beat one write data stream and a second half-frequency beat one write data stream;

split the beat two write data into a first half-frequency beat two write data stream and a second half-frequency beat two write data stream; and

a first data input pipeline and a second data input pipeline coupled between the data circuitry and the plurality of SRAM banks, the first data pipeline and the second data pipeline configured to bus the first beat one write data stream, the second beat one write data stream, the first beat two write data stream, and the second beat two write data stream to the plurality of SRAM banks; and

wherein the bank access circuitry arranged and electrically coupled to: merge/recombine the split read address information and the split write address information into a single read/write address stream to read and write to each particular bank of the plurality of SRAM banks;

form a single beat one write data stream by combining/merging the first beat one write data stream and the second beat one write data stream to write the beat one data to at least one of the plurality of SRAM banks; and

form a single beat two write data stream by combining the first beat two write data stream and the second beat two write data stream to write beat two data to one or more of the plurality of SRAM banks.

3. The device of claim 1 or any claim herein,

wherein the address circuitry receives a read address and a write address, and is arranged and electrically coupled to:

split the read address into a first read address stream and a second read address stream, and split the write address into a first write address stream and a second write address stream; and

provide read address information that has been split and write address information that has been split to the plurality of SRAM banks;

wherein the data circuitry is arranged and connected to:

split the beat one write data into a first half-frequency beat one write data stream and a second half-frequency beat one write data stream;

split the beat two write data into a first half-frequency beat two write data stream and a second half-frequency beat two write data stream; and

provide the first beat one write data stream, the second beat one write data stream, the first beat two write data stream, and the second beat two write data stream to the plurality of SRAM banks; and

wherein the bank access circuitry is arranged and electrically coupled to: merge/recombine the split read address information and the split write address information into a single read/write address stream to read and write to each particular bank of the plurality of SRAM banks;

form a single beat one write data stream by combining/merging the first beat one write data stream and the second beat one write data stream to write the beat one data to at least one of the plurality of SRAM banks; and

form a single beat two write data stream by combining the first beat two write data stream and the second beat two write data stream to write beat two data to one or more of the plurality of SRAM banks.

4. A multi-bank, dual-pipe SRAM device comprising:

(i) a memory array comprising a plurality of SRAM banks, wherein the each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry; (ii) an address input pipeline circuit comprising:

address circuitry that receives a read address and a write address, the address circuitry arranged and electrically coupled to split the read address into a first read address stream and a second read address stream, and split the write address into a first write address stream and a second write address stream; and

a first address input pipeline and a second address input pipeline coupled between the address circuitry and the plurality of SRAM banks, the first address pipeline and the second address pipeline configure to bus read address information that has been split and write address information that has been split to the plurality of SRAM banks, wherein each of the address input pipelines operate at half-frequency of input clock frequency;

(iii) a data input pipeline circuit comprising:

data circuitry that receives first and second beats of write data comprising beat one write data and beat two write data, wherein the data circuitry is arranged and connected to:

split the beat one write data into a first half-frequency beat one write data stream and a second half-frequency beat one write data stream;

split the beat two write data into a first half-frequency beat two write data stream and a second half-frequency beat two write data stream; and

a first data input pipeline and a second data input pipeline coupled between the data circuitry and the plurality of SRAM banks, the first data pipeline and the second data pipeline configured to bus the first beat one write data stream, the second beat one write data stream, the first beat two write data stream, and the second beat two write data stream to the plurality of SRAM banks; and

(iv) bank access circuitry, at the plurality of SRAM banks, the bank access circuitry arranged and electrically coupled to: merge/recombine the split read address information and the split write address information into a single read/write address stream to read and write to each particular bank of the plurality of SRAM banks;

form a single beat one write data stream by combining/merging the first beat one write data stream and the second beat one write data stream to write the beat one data to at least one of the plurality of SRAM banks; and

form a single beat two write data stream by combining the first beat two write data stream and the second beat two write data stream to write beat two data to one or more of the plurality of SRAM banks.

5. The device of claim 1 , claim 2, claim 4 or any claim herein wherein the address pipeline circuit and/or the bank access circuitry are configured to:

form a first read/write address stream (Au) from the first read address stream and the first write address stream, and form a second read/write address stream (Av) from the second read address stream and the second write address stream;

merge/recombine the first read/write address stream and the second read/write address stream into the single read/write address stream to read and write to each particular bank of the plurality of SRAM banks.

6. The device of claim 1 , claim 4, claim 5 or any claim herein, wherein the access circuitry comprises circuit components arranged and coupled to:

designate alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle, respectively;

generate a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock; and

generate a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock.

7. The device of claim 1 , claim 4, claim 5 or any claim herein, further comprising: a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle;

a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock.

8. The device of claim 1 , claim 4, claim 5, claim 6, claim 7 or any claim herein wherein the address circuitry uses the first input clock to latch a read address input per clock cycle, and uses the second input clock to latch a write address input per clock cycle.

9. The device of claim 1 , claim 4, claim 5 or any claim herein,:

wherein a read operation initiated in the first pipeline clock cycle is paired with a write operation initiated in a same or a different first pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to a same SRAM bank or to a different SRAM bank;

wherein the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the first pipeline clock cycle does not exceed two cycles;

wherein a read operation initiated in a second pipeline clock cycle is paired with a write operation initiated in a same or a different second pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to the same SRAM bank or to the different SRAM bank;

wherein the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the second pipeline clock cycle does not exceed two cycles.

10. The device of claim 9 or any claim herein wherein the read addresses are restricted to a non-busy SRAM bank due to one or more busy SRAM banks based on previously-initiated read and write operations at the time the read address is input and a new read operation is subsequently generated; and

wherein the write addresses are not restricted insofar as any SRAM bank may be written to at any time regardless of the previously-initiated read and write operations.

1 1 . The device of claim 10 or any claim herein further comprising:

a first data input clock and a second data input clock, mesochronous with or physically same as the first input clock and the second input clock,

respectively, wherein the second data input clock is the inverse of the first data input clock;

data circuitry using the first data input clock to latch a first beat of write data transferred per clock cycle per write operation; and

the data circuitry using the second data input clock to latch a second beat of write data transferred per clock cycle per write operation.

12. The device of claim 1 1 or any claim herein, wherein the data circuitry captures and buses the two beats of write data transferred per write operation to the plurality of SRAM banks through a first data input pipeline and a second data input pipeline, wherein each of the data pipelines operates at half of the first/second input clock frequency.

13. The device of claim 10, claim 1 1 , or any claim herein further comprising: a first address input pipeline generating first pipeline read addresses and first pipeline write addresses after capturing, and propagating the first pipeline read/write addresses to each of the plurality of SRAM banks.

14. The device of claim 10 or any claim herein further comprising: a second address input pipeline generating second pipeline read addresses and second pipeline write addresses after capturing, and propagating the second pipeline read/write addresses to each of the plurality of SRAM banks.

15. The device of claim 1 , claim 4, claim 5 or any claim herein, wherein the data circuitry captures and propagates the two beats of write data transferred per write operation to the plurality of SRAM banks through a first data input pipeline and a second data input pipeline, wherein each of the data pipelines operates at half of the first/second input clock frequency.

16. The device of claim 16, claim 17, or any claim herein further comprising: a first address input pipeline generating first pipeline read addresses and first pipeline write addresses after capturing, and propagating the first pipeline read/write addresses to each of the plurality of SRAM banks.

17. A multi-bank, dual-pipe SRAM device comprising:

a memory array comprising a plurality of SRAM banks, wherein the each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry;

an address input pipeline circuit comprising address circuitry that receives a read address and a write address, as well as a first address input pipeline and a second address input pipeline coupled between the address circuitry and the plurality of SRAM banks, the address circuitry arranged and connected to:

split the read address into a first read address stream and a second read address stream, and split the write address into a first write address stream and a second write address stream;

form a first read/write address stream (Au) from the first read address stream and the first write address stream, and form a second read/write address stream (Av) from the second read address stream and the second write address stream;

bus the first read/write address stream and the second read/write address stream to the plurality of SRAM banks through the first address input pipeline and the second address input pipeline, respectively, wherein each of the address input pipelines operate at half-frequency of input clock frequency;

a data input pipeline circuit comprising:

data circuitry that receives first and second beats of write data comprising beat one write data and beat two write data; and

a first data input pipeline and a second data input pipeline coupled between the data circuitry and the plurality of SRAM banks;

wherein the data circuitry is arranged and connected to:

split the beat one write data into a first half-frequency beat one write data stream and a second half-frequency beat one write data stream;

split the beat two write data into a first half-frequency beat two write data stream and a second half-frequency beat two write data stream;

bus, via the first data input pipeline and the second data input pipeline, the first beat one write data stream, the second beat one write data stream, the first beat two write data stream, and the second beat two write data stream to the memory;

bank access circuitry, at the plurality of SRAM banks, the bank access circuitry arranged and coupled to:

recombine the first read/write address stream and the second read/write address stream into a single read/write address stream to read and write to each particular bank of the plurality of SRAM banks;

form a single beat one write data stream by combining/merging the first beat one write data stream and the second beat one write data stream to write the beat one data to at least one of the plurality of SRAM banks; and

form a single beat two write data stream by combining the first beat two write data stream and the second beat two write data stream to write beat two data to one or more of the plurality of SRAM banks.

18. The device of claim 17 or any claim herein, wherein the access circuitry comprises circuit components arranged and coupled to:

designate alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle, respectively;

generate a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock; and

generate a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock.

19. The device of claim 17 or any claim herein, further comprising:

a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle;

a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock.

20. The device of claim 19 or any claim herein wherein the address circuitry uses the first input clock to latch a read address input per clock cycle, and uses the second input clock to latch a write address input per clock cycle.

21 . The device of claim 17 or any claim herein,:

wherein a read operation initiated in the first pipeline clock cycle is paired with a write operation initiated in a same or a different first pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to a same SRAM bank or to a different SRAM bank;

wherein the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the first pipeline clock cycle does not exceed two cycles;

wherein a read operation initiated in a second pipeline clock cycle is paired with a write operation initiated in a same or a different second pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to the same SRAM bank or to the different SRAM bank;

wherein the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the second pipeline clock cycle does not exceed two cycles.

22. The device of claim 21 or any claim herein wherein the read addresses are restricted to a non-busy SRAM bank due to one or more busy SRAM banks based on previously-initiated read and write operations at the time the read address is input and a new read operation is subsequently generated; and

wherein the write addresses are not restricted insofar as any SRAM bank may be written to at any time regardless of the previously-initiated read and write operations.

23. The device of claim 22 or any claim herein further comprising:

a first data input clock and a second data input clock, mesochronous with or physically same as the first input clock and the second input clock,

respectively, wherein the second data input clock is the inverse of the first data input clock;

data circuitry using the first data input clock to latch a first beat of write data transferred per clock cycle per write operation; and

the data circuitry using the second data input clock to latch a second beat of write data transferred per clock cycle per write operation.

24. The device of claim 23 or any claim herein, wherein the data circuitry captures and buses the two beats of write data transferred per write operation to the plurality of SRAM banks through a first data input pipeline and a second data input pipeline, wherein each of the data pipelines operates at half of the first/second input clock frequency.

25. The device of claim 22, claim 23, or any claim herein further comprising: a first address input pipeline generating first pipeline read addresses and first pipeline write addresses after capturing, and propagating the first pipeline read/write addresses to each of the plurality of SRAM banks;

26. The device of claim 22 or any claim herein further comprising:

a second address input pipeline generating second pipeline read addresses and second pipeline write addresses after capturing, and propagating the second pipeline read/write addresses to each of the plurality of SRAM banks.

27. The device of claim 17 or any claim herein, wherein the data circuitry captures and buses the two beats of write data transferred per write operation to the plurality of SRAM banks through a first data input pipeline and a second data input pipeline, wherein each of the data pipelines operates at half of the first/second input clock frequency.

28. The device of claim 16, claim 17, or any claim herein further comprising: a first address input pipeline generating first pipeline read addresses and first pipeline write addresses after capturing, and propagating the first pipeline read/write addresses to each of the plurality of SRAM banks.

29. A multi-bank, dual-pipe SRAM device comprising:

a memory array comprising a plurality of SRAM banks, wherein the each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry; an address input pipeline circuit comprising address circuitry that receives a read address and a write address, as well as a first address input pipeline and a second address input pipeline coupled between the address circuitry and the plurality of SRAM banks, the address circuitry arranged and connected to:

split the read address into a first read address stream and a second read address stream, and split the write address into a first write address stream and a second write address stream;

form a first read/write address stream from the first read address stream and the first write address stream, and form a second read/write address stream from the second read address stream and the second write address stream;

wherein each of the address input pipelines operate at half- frequency of input clock frequency;

a data input pipeline circuit comprising:

data circuitry that receives first and second beats of write data comprising beat one write data and beat two write data; and

a first data input pipeline and a second data input pipeline coupled between the data circuitry and the plurality of SRAM banks;

wherein the data circuitry is arranged and connected to:

split the beat one write data into a first half-frequency beat one write data stream and a second half-frequency beat one write data stream;

split the beat two write data into a first half-frequency beat two write data stream and a second half-frequency beat two write data stream;

bank access circuitry, at the plurality of SRAM banks, the bank access circuitry arranged and coupled to:

recombine the first read/write address stream and the second read/write address stream into a single read/write address stream to read and write to each particular bank of the plurality of SRAM banks.

30. The device of claim 29 or any claim herein wherein the address circuitry is arranged to: bus the first read/write address stream and the second read/write address stream to the plurality of SRAM banks through the first address input pipeline and the second address input pipeline, respectively.

31 . The device of claim 29 wherein the data circuitry is arranged to:

bus, via the first data input pipeline and the second data input pipeline, the first beat one write data stream, the second beat one write data stream, the first beat two write data stream, and the second beat two write data stream to the memory.

32. The device of claim 29 wherein the bank access circuitry is arranged to: form a single beat one write data stream by combining/merging the first beat one write data stream and the second beat one write data stream to write the beat one data to at least one of the plurality of SRAM banks; and

form a single beat two write data stream by combining the first beat two write data stream and the second beat two write data stream to write beat two data to one or more of the plurality of SRAM banks.

33. The device of claim 1 , claim 4, or any claim herein further comprising one or more of:

a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle;

a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock; and/or

wherein the access circuitry is configured to do one or more of:

designate alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle respectively;

generate a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock; and/or

generate a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock.

34. A Quad-B2 SRAM memory device comprising:

a memory array comprising a plurality of SRAM banks, wherein the each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry, the memory cell access circuitry comprising:

a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle;

a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock;

wherein the access circuitry is configured to:

designate alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle respectively;

generate a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock; and generate a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock.

35. The device of claim 34 or any claim herein: wherein a read operation initiated in the first pipeline clock cycle is paired with a write operation initiated in a same or a different first pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to a same SRAM bank or to a different SRAM bank; wherein the read operation is executed for less than two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the first pipeline clock cycle does not exceed two cycles;

wherein a read operation initiated in a second pipeline clock cycle is paired with a write operation initiated in a same or a different second pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to the same SRAM bank or to the different SRAM bank; and/or

wherein the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the second pipeline clock cycle does not exceed two cycles.

36. The device of claim 35 or any claim herein further comprising:

address circuitry using the first input clock to latch a read address input per clock cycle;

the address circuitry using the second input clock to latch a write address input per clock cycle;

the address circuitry capturing and propagating read and write

addresses to the plurality of SRAM banks through a first address input pipeline and a second address input pipeline, wherein each of the address input pipelines operate at half of the first/second input clock frequency.

37. The device of claim 36 or any claim herein wherein the read

addresses are restricted to a non-busy SRAM bank due to one or more busy SRAM banks based on previously-initiated read and write operations at the time the read address is input and a new read operation is subsequently generated;

wherein the write addresses are not restricted insofar as any SRAM bank may be written to at any time regardless of the previously-initiated read and write operations.

38. The device of claim 37 or any claim herein further comprising:

a first data input clock and a second data input clock,

mesochronous with or physically same as the first input clock and the second input clock, respectively, wherein the second data input clock is the inverse of the first data input clock;

data circuitry using the first data input clock to latch a first beat of write data transferred per clock cycle per write operation;

the data circuitry using the second data input clock to latch a second beat of write data transferred per clock cycle per write operation; the data circuitry capturing and propagating the two beats of write data transferred per write operation to the plurality of SRAM banks through a first data input pipeline and a second data input pipeline, wherein each of the data pipelines operates at half of the first/second input clock frequency.

39. The device of claim 37, claim 38, or any claim herein further comprising:

a first address input pipeline generating first pipeline read addresses and first pipeline write addresses after capturing, and

propagating the first pipeline read/write addresses to each of the plurality of SRAM banks;

a second address input pipeline generating second pipeline read addresses and second pipeline write addresses after capturing, and propagating the second pipeline read/write addresses to each of the plurality of SRAM banks.

40. The device of claim 39 or any claim herein, wherein a first portion of the first address input pipeline and the second address input pipeline comprise:

a first address register/latch that captures read addresses on a rising edge of the first input clock every cycle, regardless of the state of a first read control captured on the same rising edge of the first input clock; a second address register/latch that captures write addresses on the rising edge of the second input clock in clock cycles in which a first write control is captured low/active on a preceding rising edge of the first input clock.

41 . The device of claim 40 or any claim herein, wherein a second portion of the first address input pipeline and the second address input pipeline comprises:

a third address register/latch that re-latches the read address from the first address register/latch on the rising edge of the first pipeline clock to generate a first pipeline read address valid for two cycles;

a fourth address register/latch that re-latches the read address from the first address register/latch on the rising edge of the third pipeline clock to generate a second pipeline read address valid for two cycles;

a fifth address register/latch that re-latches the write address from the second address register/latch on the rising edge of the second pipeline clock to generate a first pipeline write address valid for two cycles; and a sixth address register/latch that re-latches the write address from the second address register/latch on the rising edge of the fourth pipeline clock to generate a second pipeline write address valid for two cycles.

42. The device of claim 40 or any claim herein, wherein a second portion of the first address input pipeline and second address input pipeline comprises: a third address register/latch that re-latches the read address from the first address register/latch on the rising edge of the first pipeline clock to generate a first pipeline read address valid for two cycles;

a fourth address register/latch that re-latches the read address from the first address register/latch on the rising edge of the third pipeline clock to generate a second pipeline read address valid for two cycles;

a fifth address register/latch, serving as a first write buffer in the first address input pipeline, that re-latches the write address from the second address register/latch on the rising edge of the third clock pipeline to generate a write address valid for two cycles;

a sixth address register/latch, serving as a second write buffer in the first address input pipeline, that re-latches the write address from the fifth address register/latch on the rising edge of the third pipeline clock to generate a write address valid for two cycles;

a seventh address register/latch that re-latches the write address from sixth address register/latch on the rising edge of the first pipeline clock to generate a first pipeline write address valid for two cycles;

an eighth address register/latch, serving as a first write buffer in the second address input pipeline, that re-latches the write address from the second address register/latch on the rising edge of the first pipeline clock to generate a write address valid for two cycles;

a ninth address register/latch, serving as a second write buffer in the second address input pipeline, that re-latches the write address from the eighth address register/latch on the rising edge of the first pipeline clock to generate a write address valid for two cycles;

a tenth address register/latch that re-latches the write address from the ninth address register/latch on the rising edge of the third pipeline clock to generate a second pipeline write address valid for two cycles.

43. The device of claim 40 or any claim herein, wherein a second portion of the first address input pipeline and the second address input pipeline comprises:

a third address register/latch that re-latches the read address from the first address register/latch on the rising edge of the first pipeline clock to generate a first pipeline read address valid for two cycles;

a fourth address register/latch that re-latches the read address from the first address register/latch on the rising edge of the third pipeline clock to generate a second pipeline read address valid for two cycles;

a first series of a plurality of address registers/latches that are a plurality of write buffers in the first address input pipeline that sequentially re-latch the write address from the second address register/latch on the rising edge of the third pipeline clock to generate a first series of write addresses valid for two cycles at each stage;

a fifth address register/latch that re-latches the write address from the first series of address registers/latches on the rising edge of the first pipeline clock to generate a first pipeline write address valid for two cycles; a second series of a plurality of address registers/latches that are a plurality of write buffers in the second address input pipeline that

sequentially re-latch the write address from the second address

register/latch on the rising edge of the first pipeline clock to generate a second series of write addresses valid for two cycles at each stage;

a sixth address register/latch that re-latches the write address from the second series of address registers/latches on the rising edge of the third pipeline clock to generate a second pipeline write address valid for two cycles.

44. The device of claim 41 , claim 42, claim 43 or any claim herein, wherein a third portion of the first address input pipeline and second address input pipeline comprises:

a first 2:1 address mux that time-multiplexes the first pipeline read and write addresses together into a single first pipeline address stream that is subsequently bussed to the each SRAM bank, wherein the combined duration of the first pipeline read and write address is two cycles;

a second 2:1 address mux that time-multiplexes the second pipeline read and write addresses together into a single second pipeline address stream that is subsequently bussed to the each SRAM bank, wherein the combined duration of the second pipeline read and write address is two cycles.

45. The device of claim 44 or any claim herein, wherein the circuitry is configured to generate:

a first pulse, derived from the first pipeline clock and shorter than one cycle at a slow operating frequency or longer than one cycle at a maximum operating frequency, that selects the first pipeline read address to be multiplexed into the first pipeline address stream;

a second pulse, derived from the third pipeline clock at the slow operating frequency or that is started after the first pulse completes at the maximum operating frequency and selects the first pipeline write address to be multiplexed into the first pipeline address stream;

a third pulse derived from third pipeline clock and shorter than one cycle at the slow operating frequency or longer than one cycle at the maximum operating frequency, that selects the second pipeline read address to be multiplexed into the second pipeline address stream; and a fourth pulse, derived from the first pipeline clock at the slow operating frequency or that is started after the third pulse completes and selects the second pipeline write address to be multiplexed into the second pipeline address stream.

46. The device of claim 45 or any claim herein wherein

the first pulse is a one-shot, self-timed pulse whose width emulates the read cycle delay; the second pulse is a one-shot, self-timed pulse whose width emulates the write cycle delay;

the third pulse is a one-shot, self-timed pulse whose width emulates the read cycle delay;

the fourth pulse is a one-shot, self-timed pulse whose width emulates the write cycle delay.

47. The device of claim 44, claim 46 or any claim herein further comprising:

a first address pre-decoder along the address path before capturing in a first read register/latch and a first write register/latch.

48. The device of claim 44, claim 46 or any claim herein further comprising:

a first address pre-decoder provided in the read address path after capturing in a first read register/latch and before splitting the read address path into a first pipeline read address path and a second pipeline read address path;

a second address pre-decoder provided in the write address path after capturing in a first write register/latch and before splitting the write address path into a first pipeline write address path and a second pipeline write address path.

49. The device of claim 44, claim 46 or any claim herein, further comprising:

a first address pre-decoder provided in the first pipeline read address path and before the first 2:1 address mux;

a second address pre-decoder provided in the second pipeline read address path and before the second 2:1 address mux;

a third address pre-decoder provided in the first pipeline write address path and before the first 2:1 address mux; a fourth address pre-decoder provided in the second pipeline write address path and before the second 2:1 address mux.

50. The device of one of claim 44, claim 47, claim 48, claim 49 or any claim herein further comprising:

a 2:1 address SRAM bank mux provided at the each SRAM bank that time-multiplexes first pipeline address stream non-bank addresses from the first address input pipeline and second pipeline address stream non-bank addresses from the second address input pipeline together into a single SRAM bank address stream to read and write to the

corresponding SRAM bank,

wherein SRAM bank circuitry decodes the first pipeline address stream bank addresses from the first address input pipeline and generates a first SRAM bank one-shot pulse that selects the first pipeline address stream non-bank addresses (read and/or write) to be multiplexed into the SRAM bank address stream;

wherein the SRAM bank circuitry decodes the second pipeline address stream bank addresses from the second address input pipeline and generates a second SRAM bank one-shot pulse that selects the second pipeline address stream non-bank addresses (read and/or write) to be multiplex into the SRAM bank address stream.

51 . The device of claim 50 or any claim herein wherein the first 2:1 address mux, the second 2:1 address mux, and the 2:1 address SRAM bank mux each comprise:

two mux inputs, two mux input selects with one dedicated per mux input, and a mux output;

a first driver, a second driver, and a third driver, each of the drivers comprising: an input, an enable, and an output such that the output is equal to the input when the enable is active, and is t -stated when the enable is inactive;

wherein the first driver input is the first mux input, the second driver input is the second mux input, and the third driver input is ground;

wherein the first driver enable is the first mux input select, the second driver enable is the second mux input select, and the third driver enable is a logical NOR of the two mux input selects;

wherein the first driver output, the second driver output and the third driver output are dotted together to create the mux output; and

wherein the third driver causes the mux output to be "low" when neither of the two mux input selects are active.

52. The device of claim 38 or any claim herein further comprising:

a first data input pipeline generating two beats of first pipeline write data after capturing and transferring to the first input clock domain, and propagating the two beats of first pipeline write data to each SRAM bank; and

a second data input pipeline generating two beats of second pipeline write data after capturing and transferring to the first input clock domain, and propagating the two beats of the second pipeline write data to each SRAM bank.

53. The device of claim 52 or any claim herein, wherein a first portion of the first data input pipeline and the second data input pipeline comprises: a first data register/latch capturing the first beat of write data on the rising edge of the first data input clock every cycle, regardless of the state of the first write control captured on the rising edge of the first input clock in the same cycle; and

a second data register/latch capturing the second beat of write data on the rising edge of the second data input clock every cycle, regardless of the state of the first write control captured on the rising edge of the first input clock in the same cycle.

54. The device of claim 53 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline

comprises:

a third data register/latch that re-latches the first beat of write data from the first data register/latch on the rising edge of the second input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a fourth data register/latch that re-latches the first beat of write data from the third data register/latch on the rising edge of the third pipeline clock, thereby generating a first pipeline first beat of write data valid for two cycles;

a fifth data register/latch that re-latches the first beat of write data from the third data register/latch on the rising edge of the first pipeline clock, thereby generating a second pipeline first beat of write data valid for two cycles;

a sixth data register/latch that re-latches the second beat of write data from the second data register/latch on the rising edge of the first input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a seventh data register/latch that re-latches the second beat of write data from the sixth data register/latch on the rising edge of the third pipeline clock, thereby generating a first pipeline second beat of write data valid for two cycles; and

an eighth data register/latch that re-latches the second beat of write data from the sixth data register/latch on the rising edge of the first pipeline clock, thereby generating a second pipeline second beat of write data valid for two cycles.

55. The device of claim 53 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline

comprises:

a third data register/latch that re-latches the first beat of write data from the first data register/latch with the second data input clock;

a fourth data register/latch that re-latches first beat of write data from the third data register/latch with the second input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a fifth data register/latch that re-latches first beat of write data from the fourth data register/latch with the first input clock;

a sixth data register/latch that re-latches first beat of write data from the fifth data register/latch with the second input clock;

a seventh data register/latch that re-latches the second beat of write data from the second data register/latch with the first data input clock;

an eighth data register/latch that re-latches the second beat of write data from the seventh data register/latch with the first input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle; and

a ninth data register/latch that re-latches the second beat of write data from eighth data register/latch with the second input clock,

wherein each of the third data register/latch to ninth data

register/latch is transparent when their respective input clock is "low" and latches when their respective input clock goes "high".

56. The device of claim 54 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline further comprises:

a ninth data register/latch serving as a first write buffer for the first beat of write data in the first data input pipeline that re-latches the first beat of write data on the rising edge of fourth pipeline clock, thereby generating a first beat of write data valid for two cycles;

a tenth data register/latch serving as a second write buffer for the first beat of write data in the first data input pipeline that re-latches the first beat of write data from the ninth register/latch on the rising edge of third pipeline clock, thereby generating a first beat of write data valid for two cycles;

an eleventh data register/latch that re-latches the first beat of write data from the tenth data register/latch on the rising edge of the first pipeline clock, thereby generating a first pipeline first beat of write data valid for two cycles;

a twelfth data register/latch serving as a first write buffer for the first beat of write data in the second data input pipeline that re-latches the first beat of write data on the rising edge of second pipeline clock, thereby generating a first beat of write data valid for two cycles;

a thirteenth data register/latch serving as a second write buffer for the first beat of write data in the second data input pipeline that re-latches the first beat of write data from twelfth data register/latch on the rising edge of the first pipeline clock, thereby generating a first beat of write data valid for two cycles;

a fourteenth data register/latch that re-latches the first beat of write data from thirteenth data register/latch on the rising edge of third pipeline clock, thereby generating a second pipeline first beat of write data valid for two cycles;

a fifteenth data register/latch serving as a first write buffer for the second beat of write data in the first data pipeline that re-latches the second beat of write data from the ninth data register/latch on the rising edge of fourth pipeline clock, thereby generating a second beat of write data valid for two cycles;

a sixteenth data register/latch serving as a write data buffer for the second beat of write data in the first data pipeline that re-latches the second beat of write data from fifteenth data register/latch on the rising edge of the third pipeline clock, thereby generating a second beat of write data valid for two cycles;

a seventeenth data register/latch that re-latches the second beat of write data from the sixteenth data register/latch on the rising edge of the first pipeline clock, thereby generating a first pipeline second beat of write data valid for two cycles;

a eighteenth data register/latch serving as a first write buffer for the second beat of write data in the second data input pipeline that re-latches the second beat of write data from ninth data register/latch on the rising edge of second pipeline clock, thereby generating a second beat of write data valid for two cycles;

a nineteenth data register/latch serving as a second write buffer for the second beat of write data in the second data input pipeline that re- latches the second beat of write data from eighteenth data register/latch on the rising edge of first pipeline clock, thereby generating a second beat of write data valid for two cycles; and

a twentieth data register/latch that re-latches the second beat of write data from the nineteenth data register/latch on the rising edge of third pipeline clock, thereby generating a second pipeline second beat of write data valid for two cycles.

57. The device of claim 53 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline comprising: a third data register/latch that re-latches the first beat of write data from the first data register/latch on the rising edge of the second input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a first series of a plurality of registers/latches that are a plurality of write buffers for the first beat of write data in the first data input pipeline that sequentially re-latch the first beat of write data from the third data register/latch on the rising edge of the third pipeline clock, thereby generating a series of first beats of write data valid for two cycles at each stage;

a fourth register/latch that re-latches the first beat of write data from the first series of a plurality of registers/latches on the rising edge of the first pipeline clock, thereby generating a first pipeline first beat of write data valid for two cycles;

a second series of a plurality of registers/latches that are a plurality of write buffers for the first beat of write data in the second data input pipeline that sequentially re-latch the first beat of write data from the third data register/latch on the rising edge of the first pipeline clock, thereby generating a series of first beats of write data valid for two cycles at each stage;

a fifth data register/latch that re-latches the first beat of write data from the second series of a plurality of registers/latches on the rising edge of the third pipeline clock, thereby generating a second pipeline first beat of write data valid for two cycles;

a sixth data register/latch that re-latches the second beat of write data from the second data register/latch on the rising edge of the first input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle; a third series of a plurality of registers/latches that are a plurality of write buffers for the second beat of write data in the first data input pipeline that sequentially re-latch the second beat of write data from the sixth data register/latch on the rising edge of the third pipeline clock, thereby generating a series of second beats of write data valid for two cycles at each stage;

a seventh data register/latch that re-latches the second beat of write data from the third series of a plurality of registers/latches on the rising edge of the first pipeline clock, thereby generating a first pipeline second beat of write data valid for two cycles;

a fourth series of a plurality of registers/latches that are a plurality of write buffers for the second beat of write data in the second data input pipeline that sequentially re-latch the second beat of write data from the sixth data register/latch on the rising edge of the first pipeline clock, thereby generating a series of second beats of write data valid for two cycles at each stage; and

an eighth data register/latch that re-latches the second beat of write data from the fourth series of a plurality of registers/latches on the rising edge of the third pipeline, thereby generating a second pipeline second beat of write data valid for two cycles.

58. The device of claim 54, claim 56, claim 57 or any claim herein further comprising:

a first 2:1 write data mux at each SRAM bank that time-multiplexes the first pipeline first beat of write data from the first data input pipeline and the second pipeline first beat of write data from the second data input pipeline together into a single first data stream of first beat of write data sent to the corresponding SRAM bank;

a second 2:1 write data mux at each SRAM bank that time- multiplexes the first pipeline second beat of write data from the first data input pipeline and the second pipeline second beat of write data from the second data input pipeline together into a single second data stream of second beat of write data sent to the corresponding SRAM bank;

SRAM bank circuitry that decodes the first pipeline address stream bank write addresses from the first address input pipeline and generates a first SRAM bank one-shot pulse that selects the first pipeline first beat of write data to be multiplexed into the first write data stream, and first

pipeline second beat of write data to be multiplexed into the second write data stream;

SRAM bank circuitry that decodes the second pipeline address stream bank write addresses from the second address input pipeline and generates a second SRAM bank one-shot pulse that selects the second pipeline first beat of write data to be multiplexed into the first write data stream, and second pipeline second beat of write data to be multiplexed into the second write data stream.

59. The device of claim 58 or any claim herein wherein the first and the second 2:1 write data muxes each comprise:

two mux inputs, two mux input selects with one dedicated per mux input, and a mux output;

a first driver and a second driver each comprising:

an input, an enable, and an output wherein the output is equal to the input when the enable is active, and is tri-stated when the enable is inactive;

the first driver input is the first mux input and the second driver input is the second mux input;

the first driver enable is the first input select and the second driver enable is the second input select;

the first driver output and the second driver output are dotted together to create the mux output; and

a driver latch keeping the mux output at its current state when neither of the mux input selects is active.

60. A Quad-B2 SRAM memory device comprising:

a memory array comprising a plurality of SRAM banks, wherein

each SRAM bank includes a block of single port SRAM memory cells

organized as a matrix of rows and columns and memory cell access

circuitry, the memory cell access circuitry comprising:

a first read control input and a first write control input for

initiating read and write operations in the same clock cycle for each and every clock cycle;

a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock;

wherein the plurality of SRAM banks are simultaneously active.

61 . The device of claim 60 or any claim herein,

wherein a read operation initiated in any clock cycle is paired with a write operation initiated in the same clock cycle, wherein the read operation and the write operation are executed sequentially over two clock cycles, either to a same SRAM bank or to a different SRAM bank;

wherein the read operation is executed for less than two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation does not exceed two cycles.

62. A method of operating a Quad-B2 SRAM memory device, the method comprising:

configuring a memory array with a plurality of SRAM banks,

wherein the each SRAM bank includes a block of single port SRAM

memory cells organized as a matrix of rows and columns and memory cell access circuitry,

configuring the memory cell access circuitry with: a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle;

a first input clock and a second input clock, wherein the

second input clock is the inverse of the first input clock;

via the access circuitry:

designating alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle respectively;

generating a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock; and

generating a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock.

63. The method of claim 62 or any claim herein:

wherein a read operation initiated in the first pipeline clock cycle is paired with a write operation initiated in a same or a different first pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to a same SRAM bank or to a different SRAM bank; wherein the read operation is executed for less than two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the first pipeline clock cycle does not exceed two cycles;

wherein a read operation initiated in a second pipeline clock cycle is paired with a write operation initiated in a same or a different second pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to the same SRAM bank or to the different SRAM bank; and/or wherein the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the second pipeline clock cycle does not exceed two cycles.

64. The method of claim 63 or any claim herein further comprising

utilizing:

address circuitry using the first input clock to latch a read address input per clock cycle;

the address circuitry using the second input clock to latch a write address input per clock cycle;

the address circuitry capturing and propagating read and write

addresses to the plurality of SRAM banks through a first address input pipeline and a second address input pipeline, wherein each of the address input pipelines operate at half of the first/second input clock frequency.

65. The method of claim 64 or any claim herein wherein the read

addresses are restricted to a non-busy SRAM bank due to one or more busy SRAM banks based on previously-initiated read and write operations at the time the read address is input and a new read operation is

subsequently generated;

wherein the write addresses are not restricted insofar as any SRAM bank may be written to at any time regardless of the previously-initiated read and write operations.

66. The method of claim 65 or any claim herein further comprising

utilizing:

a first data input clock and a second data input clock,

mesochronous with or physically same as the first input clock and the second input clock, respectively, wherein the second data input clock is the inverse of the first data input clock; data circuitry using the first data input clock to latch a first beat of write data transferred per clock cycle per write operation;

the data circuitry using the second data input clock to latch a second beat of write data transferred per clock cycle per write operation; the data circuitry capturing and propagating the two beats of write data transferred per write operation to the plurality of SRAM banks through a first data input pipeline and a second data input pipeline, wherein each of the data pipelines operates at half of the first/second input clock frequency.

67. The method of claim 65, claim 66, or any claim herein further comprising utilizing:

a first address input pipeline generating first pipeline read addresses and first pipeline write addresses after capturing, and propagating the first pipeline read/write addresses to each of the plurality of SRAM banks;

a second address input pipeline generating second pipeline read addresses and second pipeline write addresses after capturing, and propagating the second pipeline read/write addresses to each of the plurality of SRAM banks.

68. The method of claim 67 or any claim herein, wherein a first portion of the first address input pipeline and the second address input pipeline comprise:

a first address register/latch that captures read addresses on a rising edge of the first input clock every cycle, regardless of the state of a first read control captured on the same rising edge of the first input clock; a second address register/latch that captures write addresses on the rising edge of the second input clock in clock cycles in which a first write control is captured low/active on a preceding rising edge of the first input clock.

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RECTMED SHEET (RULE 91)

69. The method of claim 68 or any claim herein, wherein a second portion of the first address input pipeline and the second address input pipeline comprises:

a third address register/latch that re-latches the read address from the first address register/latch on the rising edge of the first pipeline clock to generate a first pipeline read address valid for two cycles;

a fourth address register/latch that re-latches the read address from the first address register/latch on the rising edge of the third pipeline clock to generate a second pipeline read address valid for two cycles;

a fifth address register/latch that re-latches the write address from the second address register/latch on the rising edge of the second pipeline clock to generate a first pipeline write address valid for two cycles; and a sixth address register/latch that re-latches the write address from the second address register/latch on the rising edge of the fourth pipeline clock to generate a second pipeline write address valid for two cycles.

70. The method of claim 68 or any claim herein, wherein a second portion of the first address input pipeline and second address input pipeline comprises:

a third address register/latch that re-latches the read address from the first address register/latch on the rising edge of the first pipeline clock to generate a first pipeline read address valid for two cycles;

a fourth address register/latch that re-latches the read address from the first address register/latch on the rising edge of the third pipeline clock to generate a second pipeline read address valid for two cycles;

a fifth address register/latch, serving as a first write buffer in the first address input pipeline, that re-latches the write address from the second address register/latch on the rising edge of the third clock pipeline to generate a write address valid for two cycles;

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RECTMED SHEET (RULE 91) a sixth address register/latch, serving as a second write buffer in the first address input pipeline, that re-latches the write address from the fifth address register/latch on the rising edge of the third pipeline clock to generate a write address valid for two cycles;

a seventh address register/latch that re-latches the write address from sixth address register/latch on the rising edge of the first pipeline clock to generate a first pipeline write address valid for two cycles;

an eighth address register/latch, serving as a first write buffer in the second address input pipeline, that re-latches the write address from the second address register/latch on the rising edge of the first pipeline clock to generate a write address valid for two cycles;

a ninth address register/latch, serving as a second write buffer in the second address input pipeline, that re-latches the write address from the eighth address register/latch on the rising edge of the first pipeline clock to generate a write address valid for two cycles;

a tenth address register/latch that re-latches the write address from the ninth address register/latch on the rising edge of the third pipeline clock to generate a second pipeline write address valid for two cycles.

71. The method of claim 68 or any claim herein, wherein a second portion of the first address input pipeline and the second address input pipeline comprises:

a third address register/latch that re-latches the read address from the first address register/latch on the rising edge of the first pipeline clock to generate a first pipeline read address valid for two cycles;

a fourth address register/latch that re-latches the read address from the first address register/latch on the rising edge of the third pipeline clock to generate a second pipeline read address valid for two cycles;

a first series of a plurality of address registers/latches that are a plurality of write buffers in the first address input pipeline that sequentially re-latch the write address from the second address register/latch on the

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RECTMED SHEET (RULE 91) rising edge of the third pipeline clock to generate a first series of write addresses valid for two cycles at each stage;

a fifth address register/latch that re-latches the write address from the first series of address registers/latches on the rising edge of the first pipeline clock to generate a first pipeline write address valid for two cycles; a second series of a plurality of address registers/latches that are a plurality of write buffers in the second address input pipeline that

sequentially re-latch the write address from the second address

register/latch on the rising edge of the first pipeline clock to generate a second series of write addresses valid for two cycles at each stage;

a sixth address register/latch that re-latches the write address from the second series of address registers/latches on the rising edge of the third pipeline clock to generate a second pipeline write address valid for two cycles.

72. The method of claim 69, claim 70, claim 71 or any claim herein, wherein a third portion of the first address input pipeline and second address input pipeline comprises:

a first 2:1 address mux that time-multiplexes the first pipeline read and write addresses together into a single first pipeline address stream that is subsequently bussed to the each SRAM bank, wherein the

combined duration of the first pipeline read and write address is two

cycles;

a second 2:1 address mux that time-multiplexes the second

pipeline read and write addresses together into a single second pipeline address stream that is subsequently bussed to the each SRAM bank, wherein the combined duration of the second pipeline read and write

address is two cycles.

73. The method of claim 72 or any claim herein, further comprising

utilizing the circuitry to generate:

- 79 -

RECTMED SHEET (RULE 91) a first pulse, derived from the first pipeline clock and shorter than one cycle at a slow operating frequency or longer than one cycle at a maximum operating frequency, that selects the first pipeline read address to be multiplexed into the first pipeline address stream;

a second pulse, derived from the third pipeline clock at the slow operating frequency or that is started after the first pulse completes at the maximum operating frequency and selects the first pipeline write address to be multiplexed into the first pipeline address stream;

a third pulse derived from third pipeline clock and shorter than one cycle at the slow operating frequency or longer than one cycle at the maximum operating frequency, that selects the second pipeline read address to be multiplexed into the second pipeline address stream; and a fourth pulse, derived from the first pipeline clock at the slow operating frequency or that is started after the third pulse completes and selects the second pipeline write address to be multiplexed into the second pipeline address stream.

74. The method of claim 73 or any claim herein wherein

the first pulse is a one-shot, self-timed pulse whose width emulates the read cycle delay;

the second pulse is a one-shot, self-timed pulse whose width emulates the write cycle delay;

the third pulse is a one-shot, self-timed pulse whose width emulates the read cycle delay;

the fourth pulse is a one-shot, self-timed pulse whose width emulates the write cycle delay.

75. The method of claim 72, claim 74 or any claim herein further comprising utilizing:

a first address pre-decoder along the address path before capturing in a first read register/latch and a first write register/latch.

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RECTMED SHEET (RULE 91)

76. The method of claim 72, claim 74 or any claim herein further comprising utilizing:

a first address pre-decoder provided in the read address path after capturing in a first read register/latch and before splitting the read address path into a first pipeline read address path and a second pipeline read address path;

a second address pre-decoder provided in the write address path after capturing in a first write register/latch and before splitting the write address path into a first pipeline write address path and a second pipeline write address path.

77. The method of claim 72, claim 74 or any claim herein, further comprising utilizing:

a first address pre-decoder provided in the first pipeline read address path and before the first 2:1 address mux;

a second address pre-decoder provided in the second pipeline read address path and before the second 2:1 address mux;

a third address pre-decoder provided in the first pipeline write address path and before the first 2:1 address mux;

a fourth address pre-decoder provided in the second pipeline write address path and before the second 2:1 address mux.

78. The method of one of claim 72, claim 75, claim 76, claim 77 or any claim herein further comprising utilizing:

a 2:1 address SRAM bank mux provided at the each SRAM bank that time-multiplexes first pipeline address stream non-bank addresses from the first address input pipeline and second pipeline address stream non-bank addresses from the second address input pipeline together into a single SRAM bank address stream to read and write to the

corresponding SRAM bank, wherein SRAM bank circuitry decodes the first pipeline address stream bank addresses from the first address input pipeline and generates a first SRAM bank one-shot pulse that selects the first pipeline address stream non-bank addresses (read and/or write) to be multiplexed into the SRAM bank address stream;

wherein the SRAM bank circuitry decodes the second pipeline address stream bank addresses from the second address input pipeline and generates a second SRAM bank one-shot pulse that selects the second pipeline address stream non-bank addresses (read and/or write) to be multiplex into the SRAM bank address stream.

79. The method of claim 78 or any claim herein wherein the first 2:1 address mux, the second 2:1 address mux, and the 2:1 address SRAM bank mux each comprise:

two mux inputs, two mux input selects with one dedicated per mux input, and a mux output;

a first driver, a second driver, and a third driver, each of the drivers comprising:

an input, an enable, and an output such that the output is equal to the input when the enable is active, and is tri-stated when the enable is inactive;

wherein the first driver input is the first mux input, the second driver input is the second mux input, and the third driver input is ground;

wherein the first driver enable is the first mux input select, the second driver enable is the second mux input select, and the third driver enable is a logical NOR of the two mux input selects;

wherein the first driver output, the second driver output and the third driver output are dotted together to create the mux output;

wherein the third driver causes the mux output to be "low" when neither of the two mux input selects are active.

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RECTMED SHEET (RULE 91)

80. The method of claim 66 or any claim herein further comprising utilizing:

a first data input pipeline generating two beats of first pipeline write data after capturing and transferring to the first input clock domain, and propagating the two beats of first pipeline write data to each SRAM bank; a second data input pipeline generating two beats of second pipeline write data after capturing and transferring to the first input clock domain, and propagating the two beats of the second pipeline write data to each SRAM bank.

81. The method of claim 80 or any claim herein, wherein a first portion of the first data input pipeline and the second data input pipeline comprises: a first data register/latch capturing the first beat of write data on the rising edge of the first data input clock every cycle, regardless of the state of the first write control captured on the rising edge of the first input clock in the same cycle;

a second data register/latch capturing the second beat of write data on the rising edge of the second data input clock every cycle, regardless of the state of the first write control captured on the rising edge of the first input clock in the same cycle.

82. The method of claim 81 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline comprises:

a third data register/latch that re-latches the first beat of write data from the first data register/latch on the rising edge of the second input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a fourth data register/latch that re-latches the first beat of write data from the third data register/latch on the rising edge of the third pipeline

- 83 -

RECTMED SHEET (RULE 91) clock, thereby generating a first pipeline first beat of write data valid for two cycles;

a fifth data register/latch that re-latches the first beat of write data from the third data register/latch on the rising edge of the first pipeline clock, thereby generating a second pipeline first beat of write data valid for two cycles;

a sixth data register/latch that re-latches the second beat of write data from the second data register/latch on the rising edge of the first input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a seventh data register/latch that re-latches the second beat of write data from the sixth data register/latch on the rising edge of the third pipeline clock, thereby generating a first pipeline second beat of write data valid for two cycles;

an eighth data register/latch that re-latches the second beat of write data from the sixth data register/latch on the rising edge of the first pipeline clock, thereby generating a second pipeline second beat of write data valid for two cycles.

83. The method of claim 81 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline

comprises:

a third data register/latch that re-latches the first beat of write data from the first data register/latch with the second data input clock;

a fourth data register/latch that re-latches first beat of write data from the third data register/latch with the second input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

- 84 -

RECTMED SHEET (RULE 91) a fifth data register/latch that re-latches first beat of write data from the fourth data register/latch with the first input clock;

a sixth data register/latch that re-latches first beat of write data from the fifth data register/latch with the second input clock;

a seventh data register/latch that re-latches the second beat of write data from the second data register/latch with the first data input clock;

an eighth data register/latch that re-latches the second beat of write data from the seventh data register/latch with the first input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a ninth data register/latch that re-latches the second beat of write data from eighth data register/latch with the second input clock,

wherein each of the third data register/latch to ninth data

register/latch is transparent when their respective input clock is "low" and latches when their respective input clock goes "high".

84. The method of claim 82 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline further comprises:

a ninth data register/latch serving as a first write buffer for the first beat of write data in the first data input pipeline that re-latches the first beat of write data on the rising edge of fourth pipeline clock, thereby generating a first beat of write data valid for two cycles;

a tenth data register/latch serving as a second write buffer for the first beat of write data in the first data input pipeline that re-latches the first beat of write data from the ninth register/latch on the rising edge of third pipeline clock, thereby generating a first beat of write data valid for two cycles;

- 85 -

RECTMED SHEET (RULE 91) an eleventh data register/latch that re-latches the first beat of write data from the tenth data register/latch on the rising edge of the first pipeline clock, thereby generating a first pipeline first beat of write data valid for two cycles;

a twelfth data register/latch serving as a first write buffer for the first beat of write data in the second data input pipeline that re-latches the first beat of write data on the rising edge of second pipeline clock, thereby generating a first beat of write data valid for two cycles;

a thirteenth data register/latch serving as a second write buffer for the first beat of write data in the second data input pipeline that re-latches the first beat of write data from twelfth data register/latch on the rising edge of the first pipeline clock, thereby generating a first beat of write data valid for two cycles;

a fourteenth data register/latch that re-latches the first beat of write data from thirteenth data register/latch on the rising edge of third pipeline clock, thereby generating a second pipeline first beat of write data valid for two cycles;

a fifteenth data register/latch serving as a first write buffer for the second beat of write data in the first data pipeline that re-latches the second beat of write data from the ninth data register/latch on the rising edge of fourth pipeline clock, thereby generating a second beat of write data valid for two cycles;

a sixteenth data register/latch serving as a write data buffer for the second beat of write data in the first data pipeline that re-latches the second beat of write data from fifteenth data register/latch on the rising edge of the third pipeline clock, thereby generating a second beat of write data valid for two cycles;

a seventeenth data register/latch that re-latches the second beat of write data from the sixteenth data register/latch on the rising edge of the first pipeline clock, thereby generating a first pipeline second beat of write data valid for two cycles;

- 86 -

RECTMED SHEET (RULE 91) an eighteenth data register/latch serving as a first write buffer for the second beat of write data in the second data input pipeline that re- latches the second beat of write data from ninth data register/latch on the rising edge of second pipeline clock, thereby generating a second beat of write data valid for two cycles;

a nineteenth data register/latch serving as a second write buffer for the second beat of write data in the second data input pipeline that re- latches the second beat of write data from eighteenth data register/latch on the rising edge of first pipeline clock, thereby generating a second beat of write data valid for two cycles;

a twentieth data register/latch that re-latches the second beat of write data from the nineteenth data register/latch on the rising edge of third pipeline clock, thereby generating a second pipeline second beat of write data valid for two cycles.

85. The method of claim 81 or any claim herein, wherein a second portion of the first data input pipeline and the second data input pipeline comprise: a third data register/latch that re-latches the first beat of write data from the first data register/latch on the rising edge of the second input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a first series of a plurality of registers/latches that are a plurality of write buffers for the first beat of write data in the first data input pipeline that sequentially re-latch the first beat of write data from the third data register/latch on the rising edge of the third pipeline clock, thereby generating a series of first beats of write data valid for two cycles at each stage;

a fourth register/latch that re-latches the first beat of write data from the first series of a plurality of registers/latches on the rising edge of the

- 87 -

RECTMED SHEET (RULE 91) first pipeline clock, thereby generating a first pipeline first beat of write data valid for two cycles;

a second series of a plurality of registers/latches that are a plurality of write buffers for the first beat of write data in the second data input pipeline that sequentially re-latch the first beat of write data from the third data register/latch on the rising edge of the first pipeline clock, thereby generating a series of first beats of write data valid for two cycles at each stage;

a fifth data register/latch that re-latches the first beat of write data from the second series of a plurality of registers/latches on the rising edge of the third pipeline clock, thereby generating a second pipeline first beat of write data valid for two cycles;

a sixth data register/latch that re-latches the second beat of write data from the second data register/latch on the rising edge of the first input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle;

a third series of a plurality of registers/latches that are a plurality of write buffers for the second beat of write data in the first data input pipeline that sequentially re-latch the second beat of write data from the sixth data register/latch on the rising edge of the third pipeline clock, thereby generating a series of second beats of write data valid for two cycles at each stage;

a seventh data register/latch that re-latches the second beat of write data from the third series of a plurality of registers/latches on the rising edge of the first pipeline clock, thereby generating a first pipeline second beat of write data valid for two cycles;

a fourth series of a plurality of registers/latches that are a plurality of write buffers for the second beat of write data in the second data input pipeline that sequentially re-latch the second beat of write data from the sixth data register/latch on the rising edge of the first pipeline clock,

- 88 -

RECTMED SHEET (RULE 91) thereby generating a series of second beats of write data valid for two cycles at each stage;

an eighth data register/latch that re-latches the second beat of write data from the fourth series of a plurality of registers/latches on the rising edge of the third pipeline, thereby generating a second pipeline second beat of write data valid for two cycles.

86. The method of claim 82, claim 84, claim 85 or any claim herein further comprising utilizing:

a first 2:1 write data mux at each SRAM bank that time-multiplexes the first pipeline first beat of write data from the first data input pipeline and the second pipeline first beat of write data from the second data input pipeline together into a single first data stream of first beat of write data sent to the corresponding SRAM bank;

a second 2:1 write data mux at each SRAM bank that time- multiplexes the first pipeline second beat of write data from the first data input pipeline and the second pipeline second beat of write data from the second data input pipeline together into a single second data stream of second beat of write data sent to the corresponding SRAM bank;

SRAM bank circuitry that decodes the first pipeline address stream bank write addresses from the first address input pipeline and generates a first SRAM bank one-shot pulse that selects the first pipeline first beat of write data to be multiplexed into the first write data stream, and first pipeline second beat of write data to be multiplexed into the second write data stream;

SRAM bank circuitry that decodes the second pipeline address stream bank write addresses from the second address input pipeline and generates a second SRAM bank one-shot pulse that selects the second pipeline first beat of write data to be multiplexed into the first write data stream, and second pipeline second beat of write data to be multiplexed into the second write data stream.

- 89 -

RECTMED SHEET (RULE 91)

87. The method of claim 86 or any claim herein wherein the first and the second 2:1 write data muxes each comprise:

two mux inputs, two mux input selects with one dedicated per mux input, and a mux output;

a first driver and a second driver each comprising:

an input, an enable, and an output wherein the output is equal to the input when the enable is active, and is tri-stated when the enable is inactive; wherein the first driver input is the first mux input and the second driver input is the second mux input;

wherein the first driver enable is the first input select and the second driver enable is the second input select;

wherein the first driver output and the second driver output are dotted together to create the mux output; and

a driver latch keeping the mux output at its current state when neither of the mux input selects is active.

88. A Quad-B2 SRAM memory method comprising utilizing:

a memory array comprising a plurality of SRAM banks, wherein

each SRAM bank includes a block of single port SRAM memory cells

organized as a matrix of rows and columns and memory cell access

circuitry, the memory cell access circuitry comprising a first read control input, a first write control input, a first input clock, and a second input

clock;

wherein the first read control input and the first write control input initiate read and write operations in the same clock cycle for each and

every clock cycle;

wherein the second input clock is the inverse of the first input clock; and

wherein the plurality of SRAM banks are simultaneously active.

89. The method of claim 88 or any claim herein,

- 90 -

RECTMED SHEET (RULE 91) wherein a read operation initiated in any clock cycle is paired with a write operation initiated in the same clock cycle, wherein the read operation and the write operation are executed sequentially over two clock cycles, either to a same SRAM bank or to a different SRAM bank;

wherein the read operation is executed for less than two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation does not exceed two cycles.

90. Systems and methods, such as in Multi-Bank, Dual-Pipe SRAMs, involving circuitry configured for:

(1) capturing read and write addresses, splitting them into two half- frequency read address streams and two half-frequency write address streams, combining the first read and write address streams together and combining the second read and write address streams together, and bussing them to each SRAM bank, where the two read/write address streams are recombined into a single read/write address stream to read and write a particular bank; and/or

(2) capturing two beats of write data, splitting them into two half-frequency beat one write data streams and two half-frequency beat two write data streams, and bussing them to each SRAM bank, where the two beat one write data streams are recombined into a single beat one write data stream to write beat one data to a particular bank, and the two beat two write data streams are recombined into a single beat two write data stream to write beat two data to a particular bank.

91. The invention of any claim herein involving circuitry configured for:

(1) capturing read and write addresses, splitting them into two half- frequency read address streams and two half-frequency write address streams, combining the first read and write address streams together and combining the second read and write address streams together, and bussing them to each SRAM bank, where the two read/write address streams are recombined into a single read/write address stream to read and write a particular bank; and/or

(2) capturing two beats of write data, splitting them into two half-frequency beat one write data streams and two half-frequency beat two write data streams, and bussing them to each SRAM bank, where the two beat one write data streams are recombined into a single beat one write data stream to write beat one data to a particular bank, and the two beat two write data streams are recombined into a single beat two write data stream to write beat two data to a particular bank.

92. A method of SRAM operation, the method comprising:

performing one or more steps of SRAM operation involving features or functioning of one or more method claims herein, and/or of other claims herein, and/or consistent with one or more aspects of this disclosure.

93. A method of fabricating the SRAM device of claim 1 , and/or of other claims herein, and/or consistent with one or more aspects this disclosure.

94. A method of fabricating an SRAM device, the method comprising:

forming transistors onto one or more substrates;

forming interconnects, including multiple metallization layers and/or interconnects between the transistors; and

connecting the transistors and/or other components wherein an SRAM device of claim 1 , and/or of other claims herein, and/or consistent with one or more aspects of this disclosure is provided.

95. The method of claim 94 or any claim herein, wherein the fabricating includes one or more CMOS fabrication process(es) and/or CMOS process technologies.

96. A method of multi-bank, dual-pipe SRAM device operation comprising:

- 92 -

RECTMED SHEET (RULE 91) (i) configuring a memory array comprising a plurality of SRAM banks, each SRAM bank including a block of single port SRAM memory cells organized as a matrix of rows and columns, a decoder, a sense amplifier, and memory cell access circuitry, wherein each SRAM bank is capable of operating at a maximum frequency, f(m), and is configured for, and capable of, performing a read operation and a write operation together within a single f(m) clock cycle;

(ii) receiving via a read/write control input circuit a read operation and a write operation within a single external clock cycle of frequency, f(e), and providing those read and write operations to each SRAM bank;

(iii) receiving via an address input circuit a read address and a write address within a single external clock cycle of frequency, f(e), and providing those read and write addresses to each SRAM bank;

(iv) receiving via a data input circuit first and second beats of write data within a single external clock cycle of frequency, f(e), and providing those two beats of write data to each SRAM bank; and

(v) coupling bank access circuitry at the plurality of SRAM banks to the read/write control input circuit, the address input circuit, and the data input circuit, that controls combinations of read and write operations to the SRAM banks at no greater than their maximum operating frequency, f(m);

wherein the external clock frequency, f(e), is at least twice the maximum frequency, f(m), that each SRAM bank is capable of operating at, and operating the read/write control circuity at such an external clock frequency, and/or the address circuitry operates at such an external clock frequency, and/or the data circuitry operates at such an external clock frequency.

97. The method of claim 96 or any claim herein, further comprising:

receiving/processing via the address circuitry a read address and a write address;

splitting the read address into a first read address stream and a second read address stream;

- 93 -

RECTMED SHEET (RULE 91) splitting the write address into a first write address stream and a second write address stream; and

bussing via a first address input pipeline and a second address input pipeline coupled between the address circuitry and the plurality of SRAM banks, read address information that has been split and write address information that has been split to the plurality of SRAM banks, wherein each of the address input pipelines operate at half-frequency of input clock frequency, wherein the address input pipeline circuit comprises the first address pipeline and the second address pipeline;

splitting via the data circuitry the beat one write data into a first half- frequency beat one write data stream and a second half-frequency beat one write data stream;

splitting via the data circuitry the beat two write data into a first half- frequency beat two write data stream and a second half-frequency beat two write data stream; and

bussing via a first data input pipeline and a second data input pipeline the first beat one write data stream, the second beat one write data stream, the first beat two write data stream, and the second beat two write data stream to the plurality of SRAM banks, wherein the first data pipeline and the second data pipeline are coupled between the data circuitry and the plurality of SRAM banks; and

merging/recombining via the bank access circuitry split read address information and the split write address information into a single read/write address stream to read and write to each particular bank of the plurality of SRAM banks;

forming via the bank access circuitry a single beat one write data stream by combining/merging the first beat one write data stream and the second beat one write data stream to write the beat one data to at least one of the plurality of SRAM banks; and

- 94 -

RECTMED SHEET (RULE 91) forming via the bank access circuitry a single beat two write data stream by combining the first beat two write data stream and the second beat two write data stream to write beat two data to one or more of the plurality of SRAM banks.

98. The method of claim 96 or any claim herein, further comprising:

receiving/processing via the address circuitry a read address and a write address;

splitting the read address into a first read address stream and a second read address stream;

splitting the write address into a first write address stream and a second write address stream;

providing read address information that has been split and write address information that has been split to the plurality of SRAM banks;

splitting via the data circuitry the beat one write data into a first half- frequency beat one write data stream and a second half-frequency beat one write data stream;

splitting via the data circuitry the beat two write data into a first half- frequency beat two write data stream and a second half-frequency beat two write data stream; and

providing via the data circuitry the first beat one write data stream, the second beat one write data stream, the first beat two write data stream, and the second beat two write data stream to the plurality of SRAM banks; and

merging/recombining via the bank access circuitry the split read address information and the split write address information into a single read/write address stream to read and write to each particular bank of the plurality of SRAM banks;

forming via the bank access circuitry a single beat one write data stream by combining/merging the first beat one write data stream and the second beat one write data stream to write the beat one data to at least one of the plurality of SRAM banks; and

- 95 -

RECTMED SHEET (RULE 91) forming via the bank access circuitry a single beat two write data stream by combining the first beat two write data stream and the second beat two write data stream to write beat two data to one or more of the plurality of SRAM banks.

99. A Quad-B2 SRAM memory device comprising:

a memory array comprising a plurality of SRAM banks, wherein each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry, the memory cell access circuitry comprising:

a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle;

a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock;

wherein the access circuitry is configured to:

designate alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle respectively;

generate a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock; and

generate a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock.

100. A method of operating a Quad-B2 SRAM memory device comprising a memory array comprising a plurality of SRAM banks, wherein each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry, the memory cell access circuitry comprising a first read control input, a first write control input, a first input clock,

- 96 -

RECTMED SHEET (RULE 91) and a second input clock, wherein the second input clock is the inverse of the first input clock, the method comprising:

initiating read and write operations in the same clock cycle for each and every clock cycle via the first read control input and the first write control input for;

designate alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle respectively via the access circuitry;

generate a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock, via the access circuitry; and

generate a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock, via the access circuitry.

101. The device of claim 99, or the method of claim 100, or the invention of any claim herein, further comprising, in the device or method:

a read operation initiated in the first pipeline clock cycle is paired with a write operation initiated in a same first pipeline clock cycle;

the read operation and the write operation are executed sequentially over two cycles, either to a same SRAM bank or to a different SRAM bank;

the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the first pipeline clock cycle does not exceed two cycles;

a read operation initiated in a second pipeline clock cycle is paired with a write operation initiated in a same second pipeline clock cycle, wherein the read operation and the write operation are executed sequentially over two cycles, either to a same SRAM bank or to a different SRAM bank;

- 97 -

RECTMED SHEET (RULE 91) the read operation is executed for less than a duration of two cycles, the write operation is executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation of the second pipeline clock cycle does not exceed two cycles.

102. The device or method of claim 101 or any claim herein, wherein the memory device further comprises address circuitry and control circuitry, further comprising, in the device or method:

the address circuitry uses the first input clock to latch a read address input per clock cycle;

the address circuitry using the second input clock to latch a write address input per clock cycle;

the control circuitry uses the first input clock to latch a read control signal per clock cycle;

the control circuitry uses the first input clock to latch a write control signal per clock cycle; and

the address circuitry captures and propagates read and write addresses to the plurality of SRAM banks through a first address input pipeline and a second address input pipeline, wherein each of the address input pipelines operate at half of the first/second input clock frequency.

103. The device or method of claim 102 or any claim herein, further comprising, in the device or method:

the read addresses are restricted to a non-busy SRAM bank due to one or more busy SRAM banks based on previously-initiated read and write operations at the time the read address is input and a new read operation is subsequently generated;

the write addresses are not restricted insofar as any SRAM bank may be written to at any time regardless of the previously-initiated read and write operations.

- 98 -

RECTMED SHEET (RULE 91)

104. The device or method of claim 103 or any claim herein, wherein the memory device further comprises a first data input clock, a second data input clock, and data circuitry, further comprising, in the device or method:

the first data input clock and the second data input clock are

mesochronous with or physically same as the first input clock and the second input clock, respectively;

the second data input clock is the inverse of the first data input clock; the data circuitry uses the first data input clock to latch a first beat of write data transferred per clock cycle per write operation;

the data circuitry uses the second data input clock to latch a second beat of write data transferred per clock cycle per write operation;

the data circuitry captures and propagates the two beats of write data transferred per write operation to the plurality of SRAM banks through a first data input pipeline and a second data input pipeline;

each of the data pipelines operates at half of the first/second input clock frequency.

105. The device or method of claim 104 or any claim herein, wherein the memory device further comprises an address input latch/mux, further comprising, in the device or method:

the address input latch/mux captures the read and write addresses, and the address input latch/mux time-multiplexes the read and write addresses into a single address stream that is bussed to each SRAM bank.

106. The device or method of claim 105 or any claim herein, wherein a first portion of the address input latch/mux comprises a first address register/latch and a second address register/latch, further comprising, in the device or method: the first address register/latch captures read addresses on the rising edge of the first input clock every cycle, regardless of the state of a first read control captured on the same rising edge of the first input clock;

- 99 -

RECTMED SHEET (RULE 91) the second address register/latch captures write addresses on the rising edge of the second input clock in cycles in which a first write control is captured low/active on the preceding rising edge of the first input clock.

107. The device or method of claim 106 or any claim herein, wherein a second portion of the address input latch/mux comprises a first 2:1 address mux, further comprising, in the device or method:

the first 2:1 address mux time-multiplexes the read and write addresses from the first address register/latch and the second address register/latch together into a single first address stream that is subsequently bussed to the each SRAM bank,

the first input clock high selects the read address from the first address register/latch to be multiplexed into the first address stream, and

the second input clock high selects the write address from the second address register/latch to be multiplexed into the first address stream.

108. The device or method of claim 107 or any claim herein, wherein the first 2:1 address mux comprises a first mux input and a second mux input, a first mux input select dedicated to the first mux input and a second mux input select dedicated to the second mux input, and a mux output, and the memory device further comprises a driver latch and a first driver and a second driver each comprising an input, an enable, and an output, further comprising, in the device or method:

the output is equal to the input when the enable is active, and is tri-stated when the enable is inactive;

the first driver input is the first mux input, the second driver input is the second mux input,

the first driver enable is a first mux input select, the second driver enable is a second mux input select;

the first and second driver outputs are dotted together to create the mux output; and

- 100 -

RECTMED SHEET (RULE 91) the driver latch keeps the mux output at its current state when neither of the first mux input select and the second mux input select is active.

109. The device or method of claim 108 or any claim herein, wherein the memory device further comprises control input latch (CIL) circuitry, further comprising, in the device or method:

the control input latch (CIL) circuitry captures the read control signal and the write control signal subsequently bussed to each SRAM bank.

110. The device or method of claim 109 or any claim herein, wherein the control input latch (CIL) circuitry comprises a first CIL register/latch, a second CIL register/latch, and a third CIL register/latch, further comprising, in the device or method:

the first CIL register/latch captures the read control signal on the rising edge of the first input clock every clock cycle;

a second CIL register/latch captures the write control signal on the rising edge of the first input clock every clock cycle; and

a third CIL register/latch re-latches the output of the second CIL register/latch on the rising edge of second input clock every clock cycle.

11 1. The device or method of claim 1 10 or any claim herein, wherein the CIL circuitry further comprises a first inverter and a second inverter, further comprising, in the device or method:

the first inverter inverts the output of the first CIL register/latch, thereby generating an active-high read control signal bussed to each SRAM bank; and the second inverter inverts the output of the third CIL register/latch, thereby generating an active-high write control signal bussed to each SRAM bank.

112. The device or method of claim 1 1 1 or any claim herein, wherein the memory device further comprises SRAM bank circuitry at each SRAM bank, further comprising, in the device or method:

the SRAM bank circuitry at each SRAM bank decodes and de-multiplexes the bank addresses in the first address stream read and write address stream four ways into a first pipeline read bank signal, a first pipeline write bank signal, a second pipeline read bank signal, a second pipeline write bank signal, and from them generate a first pipeline read bank signal clock, a first pipeline write bank signal clock, a second pipeline read bank signal clock, a second pipeline write bank signal clock, respectively,

the bank addresses in the first address stream are decoded in an address pre-decoder to generate a single bit output bank signal which is active if the corresponding read or write operation is targeted for the corresponding SRAM bank;

the bank signal is logically ANDed with the active-high read control signal to generate a read bank signal to ensure it is generated from a valid read address when it is subsequently latched by a first bank register/latch or a second bank register/latch;

the bank signal is logically ANDed with the active-high write control signal to generate a write bank signal, to ensure it is generated from a valid write address when it is subsequently latched by a third bank register/latch or a fourth bank register/latch;

a first bank register/latch and a second bank register/latch are used to demultiplex the read bank signal two ways, which in turn are used to generate the first pipeline read bank signal clock and the second pipeline read bank signal clock,

the first bank register/latch latches the read bank signal with the first pipeline clock, thereby generating the first pipeline read bank signal which is then logically ANDed with the first pipeline clock to generate the first pipeline read bank signal clock; the second bank register/latch latches the read bank signal with the third pipeline clock, thereby generating the second pipeline read bank signal, which is then logically ANDed with the third pipeline clock to generate the second pipeline read bank signal clock;

a third bank register/latch and a fourth bank register/latch are used to demultiplex the write bank signal two ways, which in turn are used to generate the first pipeline write bank signal clock and the second pipeline write bank signal clock,

the third bank register/latch latches the write bank signal with the second pipeline clock, thereby generating the first pipeline write bank signal, which is then logically ANDed with the second pipeline clock to generate the first pipeline write bank signal clock; and

the fourth bank register/latch latches the write bank signal with the fourth pipeline clock, thereby generating the second pipeline write bank signal, which is then logically ANDed with the fourth pipeline clock to generate the second pipeline write bank signal clock.

113. The device or method of claim 1 12 or any claim herein, wherein the memory device further comprises a fifth bank register/latch and a sixth bank register/latch, further comprising, in the device or method:

the fifth bank register/latch latches the first pipeline write bank signal clock with the third pipeline clock, thereby generating a third pipeline write bank signal clock; and

the sixth bank register/latch latches the second pipeline write bank signal clock with the first pipeline clock, thereby generating a fourth pipeline write bank signal clock.

114. The device or method of claim 1 13 or any claim herein, further comprising, in the device or method:

the SRAM bank circuitry at each SRAM bank generates a self-timed first pipeline read bank pulse, a self-timed second pipeline read bank pulse, a self- timed first pipeline write bank pulse and a self-timed second pipeline write bank pulse;

the first pipeline read bank signal clock is used to generate the self-timed first pipeline read bank pulse that is active for less than a duration of two cycles, which causes a read operation to the bank;

the second pipeline read bank signal clock is used to generate a self- timed second pipeline read bank pulse that is active for less than a duration of two cycles, which causes a read operation to the bank;

the third pipeline write bank signal clock, the self-timed first pipeline read bank pulse, and the self-timed second pipeline write bank pulse, are used to generate the self-timed first pipeline write bank pulse active for less than or equal to a duration of one cycle, which causes a write operation to the bank; and

the fourth pipeline write bank signal clock, the self-timed second pipeline read bank pulse, and the self-timed first pipeline write bank pulse, are used to generate the self-timed second pipeline write bank pulse active for less than or equal to a duration of one cycle, which causes a write operation to the bank.

115. The device or method of claim 1 14 or any claim herein, further comprising, in the device or method:

the combined duration of the self-timed first pipeline read bank pulse active and the self-timed first pipeline write bank pulse active is less than or equal to two cycles; and

the combined duration of the self-timed second pipeline read bank pulse active and the self-timed second pipeline write bank pulse active is less than or equal to two cycles.

116. The device or method of claim 1 15 or any claim herein, wherein the memory device further comprises SRAM bank circuitry at each SRAM bank comprising a first non-bank register/latch, a second non-bank register/latch, a third non-bank register/latch, and a fourth non-bank register/latch, further comprising, in the device or method:

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RECTMED SHEET (RULE 91) the SRAM bank circuitry at each SRAM bank decodes and de-multiplexes the non-bank addresses in the first address stream read and write address stream four ways into a non-bank first pipeline read address, a non-bank first pipeline write address, a non-bank second pipeline read address, a non-bank second pipeline write address, wherein the non-bank addresses in the first address stream are decoded in an address pre-decoder;

the first non-bank register/latch latches the decoded non-bank addresses with the first pipeline read bank signal clock, thereby generating the non-bank first pipeline read address valid for two cycles;

the second non-bank register/latch latches the decoded non-bank addresses with the first pipeline write bank signal clock, thereby generating the non-bank first pipeline write address valid for two cycles;

the third non-bank register/latch latches the decoded non-bank addresses with the second pipeline read bank signal clock, thereby generating the non-bank second pipeline read address valid for two cycles; and

the fourth non-bank register/latch latches the decoded non-bank addresses with the second pipeline write bank signal clock, thereby generating the non-bank second pipeline write address valid for two cycles.

117. The device or method of claim 1 16 or any claim herein, wherein the memory device further comprises a 4:1 address multiplexer at each SRAM bank, further comprising, in the device or method:

the 4:1 address multiplexer at each SRAM bank time-multiplexes the non- bank first pipeline read address, the non-bank first pipeline write address, the non-bank second pipeline read address, and the non-bank second pipeline write address into a single SRAM bank address stream to read and write to the corresponding SRAM bank;

the self-timed first pipeline read bank pulse selects the non-bank first pipeline read address to be multiplexed into the SRAM bank address stream; the self-timed first pipeline write bank pulse selects the non-bank first pipeline write address to be multiplexed into the SRAM bank address stream;

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RECTMED SHEET (RULE 91) the self-timed second pipeline read bank pulse selects the non-bank second pipeline read address to be multiplexed into the SRAM bank address stream; and

the self-timed second pipeline write bank pulse selects the non-bank second pipeline write address to be multiplexed into the SRAM bank address stream.

118. The device or method of claim 1 17 or any claim herein, wherein the 4:1 address multiplexer comprises first through fourth mux inputs, first through fourth mux input selects with one dedicated per mux input, and a mux output, and first through fifth drivers, each of the drivers including an input, an enable, and an output, further comprising, in the device or method:

the output is equal to the input when the enable is active, and is tri-stated when the enable is inactive;

the first driver input is the first mux input, the second driver input is the second mux input, the third driver input is the third mux input, the fourth driver input is the mux input, and the fifth driver input is ground;

the first driver enable is the first mux input select, the second driver enable is the second mux input select, the third driver enable is the third mux input select, the fourth driver enable is the fourth mux input select, and the fifth driver enabler is a logical NOR of the first, second, third, and fourth mux input selects; the first through fifth driver outputs are dotted together to create the mux output; and

the fifth driver causes the mux output to be "low" when none of the mux input select signals are active.

119. The device or method of claim 103 or any claim herein, wherein the memory device further comprises a data input latch/mux, further comprising, in the device or method:

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RECTMED SHEET (RULE 91) the data input latch/mux captures the first and second beats of write data and time-multiplexes them into a single SRAM bank data stream bussed to the each SRAM bank.

120. The device or method of claim 1 19 or any claim herein, wherein a first portion of the data input latch/mux comprises a first data register/latch and a second data register/latch, further comprising, in the device or method:

the first data register/latch captures the first beat of write data on the rising edge of the first data input clock every cycle, regardless of the state of a first write control captured on the rising edge of the first input clock in the same cycle; and

the second data register/latch captures the second beat of write data on the rising edge of the second data input clock every cycle, regardless of the state of the first write control captured on the rising edge of the first input clock in the same cycle.

121. The device or method of claim 120 or any claim herein, wherein a second portion of the data input latch/mux comprises a third data register/latch and a fourth data register/latch, further comprising, in the device or method:

the third data register/latch re-latches the first beat of write data from the first data register/latch on the rising edge of the second input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle; and

the fourth data register/latch that re-latches the second beat of write data from the second data register/latch on the rising edge of the first input clock, thereby transferring the data from the data input clock domain to the input clock domain and allowing for the data input clock edges to lead or trail the input clock edges by approximately a half cycle.

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RECTMED SHEET (RULE 91)

122. The device or method of claim 121 or any claim herein, wherein a third portion of the data input latch/mux comprises a first 2:1 data mux, further comprising, in the device or method:

the first 2:1 data mux time-multiplexes the first and second beats of write data from the third data register/latch and the fourth data register/latch together into a single SRAM bank data stream that is subsequently bussed to the each SRAM bank;

the second input clock high selects the first beat of write data from the third data register/latch to be multiplexed into the SRAM bank data stream; and the first input clock high selects the second beat of write data from the fourth data register/latch to be multiplexed into the SRAM bank data stream.

123. The device or method of claim 122 or any claim herein, wherein the memory device further comprises six data registers/latches divided into a first group of four data register/latches for a first beat of write data path comprising a fifth data register/latch, a sixth data register/latch, a seventh data register/latch, and an eighth data register/latch; and a second group of two data

registers/latches for a second beat of write data path comprising a ninth data register/latch and a tenth data register/latch; further comprising, in the device or method:

the SRAM bank circuitry at each SRAM bank de-multiplexes the two beats of write data in the SRAM bank data stream four ways into separate bank first pipeline first beat of write data, a bank first pipeline second beat of write data, a bank second pipeline first beat of write data, and a bank second pipeline second beat of write data, based on the six data registers/latches;

the fifth data register/latch latches the first beat of write data in the SRAM bank data stream with the first pipeline write bank signal clock;

the sixth data register/latch latches the first beat of write data in the SRAM bank data stream with the second pipeline write bank signal clock;

the seventh data register/latch re-latches the first beat of write data from the fifth data register/latch with the third pipeline write bank signal clock, thereby generating the bank first pipeline first beat of write data valid for two cycles; the eighth data register/latch re-latches the first beat of write data from the sixth data register/latch with the fourth pipeline write bank signal clock, thereby generating the bank second pipeline first beat of write data valid for two cycles; the ninth data register/latch re-latches the second beat of write data in the SRAM bank data stream with the third pipeline write bank signal clock, thereby generating the bank first pipeline second beat of write data valid for two cycles concurrently with the associated bank first pipeline first beat of write data; and the tenth data register/latch re-latches the second beat of write data in the SRAM bank data stream with the fourth pipeline write bank signal clock, thereby generating the bank second pipeline second beat of write data valid for two cycles concurrently with the associated bank second pipeline first beat of write data.

124. The device or method of claim 123 or any claim herein, wherein the memory device further comprises a first 2:1 bank data mux at each SRAM bank and a second 2:1 bank data mux at each SRAM bank, further comprising, in the device or method:

the first 2:1 bank data mux at each SRAM bank time-multiplexes the bank first pipeline first beat of write data from the seventh register/latch and the bank second pipeline first beat of write data from the eighth register/latch into a single first beat of write data stream sent to the corresponding SRAM bank;

a first one-shot pulse selects the bank first pipeline first beat of write data to be multiplexed into the first 2:1 mux first beat of write data stream;

a second one-shot pulse selects the bank second pipeline first beat of write data to be multiplexed into the first 2:1 mux first beat of write data stream; the second 2:1 bank data mux at each SRAM bank time-multiplexes the bank first pipeline second beat of write data from the ninth register/latch and the bank second pipeline second beat of write data from tenth register/latch into a single second beat of write data stream sent to the corresponding SRAM bank; a first one-shot pulse selects the bank first pipeline second beat of write data to be multiplexed into the second 2:1 mux second beat of write data stream; and

a second one-shot pulse selects the bank second pipeline second beat of write data to be multiplexed into the second 2:1 mux second beat of write data stream.

125. The device or method of claim 124 or any claim herein, wherein the memory device further comprises a driver latch; the first 2:1 data mux, the first 2:1 bank data mux and the second 2:1 bank data mux each comprise two mux inputs, two mux input selects with one dedicated per mux input, and a mux output; and the first driver and the second driver each comprise an input, an enable, and an output, further comprising, in the device or method:

the output is equal to the input when the enable is active, and is tri-stated when the enable is inactive;

the first driver input is the first mux input and the second driver input is the second mux input;

the first driver enable is the first input select and the second driver enable is the second input select;

the first driver output and the second driver output are dotted together to create the mux output; and

the driver latch keeps the mux output at its current state when neither of the mux input selects is activated.

126. A Quad-B2 SRAM memory device comprising:

a memory array comprising a plurality of SRAM banks, wherein each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry, wherein the plurality of SRAM banks are active simultaneously; wherein the memory cell access circuitry comprises: a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle; and

a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock.

127. A method of operating a Quad-B2 SRAM memory device comprising a memory array comprising a plurality of SRAM banks, wherein each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry, wherein the plurality of SRAM banks are active simultaneously; wherein the memory cell access circuitry comprises a first read control input and a first write control input, the method comprising:

initiating read and write operations in the same clock cycle for each and every clock cycle via the first read control input and the first write control input for; and

providing a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock.

128. The device of claim 126, or the method of claim 127, or the invention of any claim herein, further comprising:

wherein a read operation initiated in any clock cycle is paired with a write operation initiated in a same clock cycle;

wherein the read operation and the write operation are executed sequentially over two cycles, either to a same SRAM bank or to a different SRAM bank;

wherein the read operation is executed for a duration of less than two cycles, the write operation is executed for less than or equal to a duration of one cycle; and

wherein a combined duration of the read operation and the write operation does not exceed two cycles.

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129. Systems and methods, such as in Multi-Bank, Dual-Pipe SRAMs, for:

(1) capturing read and write addresses, combining them into a single read/write address stream, and bussing it to each SRAM bank, where the single read/write address stream is split into two half-frequency read address streams and two half-frequency write address streams, and the two half-frequency read address streams and the two half-frequency write address streams are then recombined into a single read/write address stream to read and write a particular bank; and/or

(2) capturing two beats of write data, combining them into a single beat one / beat two write data stream, and bussing it to each SRAM bank, where the single beat one / beat two write data stream is split into two half-frequency beat one write data streams and two half-frequency beat two write data streams, and the two beat one write data streams are recombined into a single beat one write data stream to write beat one data to a particular bank, and the two beat two write data streams are recombined into a single beat two write data stream to write beat two data to a particular bank.

130. Systems and methods, such as in Multi-Bank SRAMs, for:

(1) capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they are split and/or combined via one or more splitting/combining processes to read and write a particular bank; and/or

(2) capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they are split and/or combined via one or more splitting/combining processes to write beat one data and beat two data to a particular bank.

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RECTMED SHEET (RULE 91)