[0001] This description relates generally to motor drivers.

BACKGROUND

[0002] Electric motors are found in automobiles, industrial fans and pumps, machine tools, household appliances, drones, gimbles, and disk drives. An electric motor is generally run by a motor driver circuit which may include a high-side transistor and a low-side transistor arranged in a bridge configuration. In some configurations, a pair of high-side/low-side transistors is used for each phase of the motor. The high-side transistor is coupled between an input voltage terminal and an output voltage terminal, and the low-side transistor is coupled between the output voltage terminal and a common potential (e.g. ground) terminal. The high-side and low-side transistors have respective body diodes. When a motor driver circuit is implemented in an integrated circuit (IC), a bond wire inductance is present due to the bond wire which connects the input voltage terminal to an external connector (e.g., external pin of IC), and another bond wire inductance is present due to the bond wire which connects the ground terminal to an external connector.

[0003] When the low-side transistor is turned on, due to the reverse recovery time of the high- side body diode, current through the high-side body diode starts to decrease but continues to flow as current through the low-side transistor starts to increase. In order to completely reverse bias the high-side body diode to prevent current flowing through the high-side body diode, the low-side transistor draws current that may have a magnitude greater than the current through the motor (motor current “Im”) in order to account for reverse recovery charge accumulated in the high-side body diode. As a result, current through the low-side transistor rises above the motor current Im, reaching a positive peak before falling to Im. Because the low-side transistor draws current greater than the motor current Im, a portion of the current through the low-side transistor is drawn from input voltage through the high-side body diode from the cathode to the anode (i.e., reverse direction). Thus, the current through the high-side body diode falls below zero, reaching a negative peak before rising to zero. The rising current through the low-side transistor induces a positive voltage across the bond wire inductance, and the falling current through the low-side transistor induces a negative voltage across the bond wire inductance. The induced voltages across the bond wire are generally referred to as a ground bounce voltage VB INT.

[0004] Because the ground bounce voltage VB INT is present at a source of the low-side transistor, VB INT dictates the voltage that must be applied to a gate of the low-side transistor to turn on the low-side transistor. Also, VB INT increases the voltage drop between a drain and a source of the low-side transistor.

[0005] If VB INT is +5V, the driver circuit must apply (Vt + 5V) to the gate to turn on the low- side transistor (Vt is the threshold voltage required to turn on the low-side transistor). Thus, if Vt is +5V, the driver circuit must apply +10V to the gate to turn on the low-side transistor. If VB INT is -4V, the driver circuit must apply +1V to the gate to turn on the low-side transistor. Also, if VB_INT is -4V and Vout is 15 V, the voltage across the low-side transistor rises to 19V.

[0006] One approach to mitigate the effects of the ground bounce voltage VB INT is to use additional circuitry which tracks VB INT and applies a corresponding gate-to-source voltage to turn on the low-side transistor and also to use a higher-rated transistor that can withstand high voltage drops between the drain and the source.

SUMMARY

[0007] In one aspect, a driver system operable to supply a drive signal to a motor includes a system input adapted to be coupled to an input voltage and a system output adapted to be coupled to the motor. The driver system includes a high-side transistor which has a first terminal coupled to the system input, a second terminal coupled to the system output, and has a control terminal. The driver system includes a low-side transistor which has a first terminal coupled to the system output, a second terminal coupled to a reference potential terminal, and has a control terminal. The driver system includes a low-side gate control circuit which has a first input coupled to the system output, a second input adapted to receive an upper reference voltage, a third input adapted to receive a low-side digital control signal, a fourth input adapted to be coupled to a voltage supply, and has an output coupled to the control terminal of the low-side transistor. The low-side gate control circuit provides, at the output of the low-side gate control circuit, a first level current responsive to the low-side digital control signal transitioning from a low state to a high state and provides a second level current, greater than the first level current, if drive signal is less than the upper reference voltage.

[0008] In another aspect, the low-side gate control circuit maintains the first level current to reduce an induced ground bounce voltage at the reference potential terminal until the drive signal falls below the upper reference voltage.

[0009] In another aspect, the low-side gate control circuit maintains the first level current to reduce the induced ground bounce voltage at the reference potential terminal by reducing the rate of change of current through the low-side transistor until the drive signal falls below the upper reference voltage.

[0010] In another aspect, the low-side gate control maintains the first level current which is lower than the second level current to reduce the rate of change of current through the low-side transistor until the drive signal falls below the upper reference voltage.

[0011] In another aspect, the low-side gate control circuit provides the second level current when the low-side transistor transitions to a Miller region.

[0012] In another aspect, the low-side gate control provides a third level current to the control terminal of the low-side transistor to turn off the low-side transistor responsive to the low-side digital control signal transitioning from the high state to the low state.

[0013] In another aspect, the low-side gate control circuit includes a first comparison circuit which has a first input coupled to the system output, and a second input adapted to receive the upper reference voltage. The first comparison circuit provides a slew start signal at an output responsive to the drive signal falling below the upper reference voltage.

[0014] In another aspect, the low-side digital control circuit includes a reverse recovery current source which has a first terminal adapted to be coupled to the voltage supply and has a second terminal. The low-side gate control circuit includes a reverse recovery switch which has a first terminal coupled to the second terminal of the reverse recovery current source, a second terminal coupled to the control terminal of the low-side transistor, a third terminal coupled to the output of the first comparison circuit, and a fourth terminal adapted to receive the low-side digital control signal. The reverse recovery switch couples the reverse recovery current source to the control terminal of the low-side transistor responsive to the low-side digital control signal transitioning from the low state to the high state, and disconnects the reverse recovery current source from the control terminal of the low-side transistor responsive to an assertion of the slew start signal by the first comparison circuit.

[0015] In another aspect, the low-side gate control circuit includes a first slew current source which has a first terminal coupled to the voltage supply and has a second terminal. The low-side gate control circuit includes a first slew current switch which has a first terminal coupled to the second terminal of the first slew current source, a second terminal coupled to the control terminal of the low-side transistor, a third terminal coupled to the output of the first comparison circuit, and a fourth terminal adapted to receive the low-side digital control signal. The first slew current switch couples the first slew current source to the control terminal of the low-side transistor responsive to the assertion of the slew start signal by the first comparison circuit.

[0016] In another aspect, the low-side gate control circuit includes a second slew current source which has a first terminal coupled to the reference potential terminal and has a second terminal. The low-side gate control circuit includes a second slew current switch which has a first terminal coupled to the control terminal of the low-side transistor, a second terminal coupled to the second terminal of the second slew current source, and a third terminal adapted to receive the low-side digital control signal. The second slew current switch couples the second slew current source to the control terminal of the low-side transistor to turn off the low-side transistor responsive to the digital control signal transitioning from the high state to the low state.

[0017] In another aspect, a driver system operable to supply an output voltage to a motor includes a system input adapted to be coupled to input voltage and a system output adapted to be coupled to the motor. The driver system includes a high-side transistor which has a first terminal coupled to the system input, a second terminal coupled to the system output, and has a control terminal. The driver system includes a low-side transistor which has a first terminal coupled to the system output, a second terminal coupled to a reference potential terminal, and has a control terminal. The driver system includes a low-side gate control circuit which has a first input coupled to the system output, a second input adapted to receive an upper reference voltage, a third input adapted to receive a low-side digital control signal, a fourth input adapted to be coupled to a voltage supply, and has an output coupled to the control terminal of the low-side transistor. The low-side gate control circuit provides a first level current to the control terminal of the low-side transistor and maintains the first level current to the control terminal of the low-side transistor to reduce ground bounce voltage at the reference potential terminal until output voltage falls below the upper reference voltage, and provides a second level current to the control terminal of the low-side transistor responsive to an assertion of a slew start signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 is a schematic diagram of an example driver system. [0019] FIG. 2 are example waveforms generated by the driver system of FIG. 1.

[0020] FIG. 3 is a block diagram of an example control circuit.

[0021] FIG. 4 is an example schematic diagram of a comparison circuit.

[0022] The same reference numerals or other feature designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0023] FIG. 1 illustrates an example driver system 100. The system 100 includes a high-side transistor MH which has a first terminal 104 (e.g., drain) coupled to an input 106. The high-side transistor MH has a second terminal 108 (e.g., source) coupled to an output 110. The high-side transistor MH has a control terminal 112 (e.g., gate). The high-side transistor MH includes a body diode DHB with the anode coupled to the source 108 and the cathode coupled to the drain 104.

[0024] In some embodiments, the driver system 100 can be implemented in an integrated circuit (IC). A bond wire inductance LBH (e.g., 1 nano-Henry) is present due to the bond wire which connects the first terminal 104 (e.g., drain) to an external connector (e.g., external pin of IC) which is designated as the input 106. A diode DI has the anode coupled to the source 108 and the cathode coupled to the gate 112. In a bridge driver circuit, the diode DI may be connected between the gate 112 and the source 108 of the high-side transistor MH to limit gate-to-source voltage of MH from falling too far below zero (i.e., too negative), which may cause reliability issues when MH is turned off.

[0025] The system 100 includes a low-side transistor ML which has a first terminal 120 (e.g., drain) coupled to the second terminal 108 and to the output 110. The low-side transistor ML has a second terminal 122 (e.g., source) coupled to a common potential terminal 124 (e.g., electrical ground). The low-side transistor ML has a control terminal 126 (e.g., gate). The low-side transistor ML includes a body diode DLB with the anode coupled to the second terminal 122 (e.g., source) and the cathode coupled to the first terminal 120 (e.g., drain). A bond wire inductance LBL (e.g., 1 nano-Henry) is present between the source 122 and an external connector designated as the common potential terminal 124.

[0026] The input 106 can be coupled to an input voltage Vm (e.g., 12V, 25V, 40V) and the reference potential terminal 124 can be coupled to an electrical ground.

[0027] In some examples, the transistors are n-channel field effect transistors (NFETs), and in another example, the transistors are p-channel field effect transistors (PFETs). In some examples, the transistors may be bipolar transistors and/or other types of power transistors (e.g., drain extended FETs). In some examples, the FETs are implemented in/over a silicon substrate. In other examples, the FETs are implemented using gallium nitride (GaN) and/or silicon carbide (SiC).

[0028] One phase of a motor, represented by an inductive load Lm, has a first terminal 130 coupled to the output 110, and has a second terminal 132 which can be coupled to the input 106 via a first switch SI or can be coupled to ground via a second switch S2. Depending on the number of phases (each phase may be determined by the number of winding pairs that are wrapped around a portion of the stator of the motor) used to drive the motor, additional features (e.g. MH, ML, SI and S2) are connected to drive each phase of the motor. To drive the motor Lm in one direction, a gate signal GATE H is applied to the gate 112 to turn on the high-side transistor MH, the low- side transistor ML is turned off (i.e., a gate signal GATE L is not applied to the gate 126), the switch S2 is turned on (i.e., closed/conducting) and the switch SI is turned off (i.e., opened/non- conducting). As a result, current Im flows from Vm through MH, then through the motor Lm, and finally through the switch S2 to ground. To drive the motor Lm in the reverse direction, the gate signal GATE L is applied to the gate 126 of ML, the high-side transistor MH is turned off (i.e., gate signal GATE H is not applied to the gate 112), the switch SI is turned on (i.e., closed/conducting), and the switch S2 is turned off (i.e., opened/non-conducting). As a result, current Im flows from Vm through the switch SI, then through the motor Lm, and finally through ML to ground. In an example, the gate signals GATE H and GATE L may be pulse width modulated (PWM) signals (which have varying pulse widths) or pulse frequency modulated (PFM) signals (which have a varying frequency but a fixed amplitude).

[0029] The system 100 includes a control circuit 140 which has a first input 142 coupled to the output 110, a second input 144 coupled to receive an upper reference voltage VREF H, a third input 146 coupled to receive a low-side digital control signal CNTR L, a fourth input 148 coupled to receive a high-side digital control signal CNTR H, and a fifth input 150 coupled to a voltage supply VCC (e.g., 5V, 7V). In some examples, the signals 144, 146 and/or 148 are provided by external inputs (e.g. user defined inputs) or by a controller (including, for example, a processor, state machine, digital logic, analog circuitry, memory and/or an application specific integrated circuit) that may be included on the same integrated circuit (IC) as MH and ML or may be implemented on a different IC. The low-side digital control signal CNTR L provides the timing for the low-side transistor ML, and the high-side digital control signal CNTR H provides the timing for the high-side transistor MH. The control circuit 140 provides the gate signal GATE L at an output 152 which is coupled to the gate 126 of the low-side transistor ML, and provides the gate signal GATE H at an output 154 which is coupled to the gate 112 of the high-side transistor MH. Also, the control circuit 140 provides a control signal CNTR S1 at an output 156 to control the switch SI, and provides a control signal CNTR S2 at an output 158 to control the switch S2. [0030] In some examples, the control circuit 140 mitigates the effect of the induced voltage VB INT without requiring additional circuitry and/or higher-rated transistors. The control circuit 140 applies a first level current (also referred to as reverse recovery current) to the gate 126 of ML during a reverse recovery period and then increases the current to a second level current (referred to as slew current) when the output voltage Vout falls below the upper reference voltage VREF H, which indicates ML has transitioned to the Miller region.

[0031] FIG. 2 illustrates waveforms used in or generated by the driver system 100. The x-axis represents time and the y-axis represents voltage with respect to voltage waveforms and current with respect to current waveforms. At time Tl, a low-side digital control signal CNTR L 204 transitions from a low state to a high state to start the process of turning on the low-side transistor ML. In response, the control circuit 140 applies a gate current I_GL 208 which has a magnitude equal to a first level current I_RR (also referred to as reverse recovery current I_RR) to the gate 126 of ML. In some examples, I_RR is approximately 500 micro-Amps (500 uA). In some examples, the magnitude of I_RR is chosen so that I_RR is sufficiently low to limit the reverse recovery period of the high-side body diode DHB but also adequate to prevent significant propagation delay (time required to turn on ML). As described before, when ML is turned on, SI is closed (conducting), MH is turned off, and S2 is opened (not conducting).

[0032] In response to I_RR, a gate-to-source voltage V GSL 212 of ML begins to rise. Because ML is still turned off at time Tl, motor current Im flows through the high-side body diode DHB from the anode to the cathode. Thus, at time Tl, a current I_HB 216 (flowing through the high- side body diode DHB) is equal to motor current Im, and a current I LS 220 (flowing through the low-side transistor ML) is zero. At time Tl, an output voltage Vout 224 is equal to (Vm + VDH), where VDH is the voltage across the high-side body diode DHB. Depending on the size of the body diode DHB, the voltage VDH can vary (e.g, 0.7V, 0.9V, 1.2V).

[0033] At time T2, the gate-to-source voltage VGS L 212 rises above the threshold voltage, Vt, required to turn on ML. Thus, the current I LS 220 through ML begins to rise. Although at time T2, ML is turned on, due to the reverse recovery time of the high-side body diode DHB, the current I_HB 216 continues to flow through DHB but starts to decrease as the current I LS 220 starts to rise through ML.

[0034] At time T2, the output voltage Vout 224 begins to fall, and at time T3, Vout 224 falls below Vm. In response, at time T3 the control circuit 140 increases the gate current I_GL from a first level current (reverse recovery current I_RR) to a second level current (slew current I SLEW). Thus, the control circuit 140 maintains a lower gate current (reverse recovery current I_RR) until Vout falls below Vm, and thereafter increases to a higher gate current (slew current I SLEW). In some examples, I SLEW is approximately 5 mA for a slew rate of around lOOV/us (100 volts per micro-second).

[0035] At time T3, the high-side body diode DHB is reverse biased, and as a result current I_HB 216 through the high-side body diode DHB falls to zero and motor current Im flows from Vm through SI and then through Lm and finally through ML. As described before, when ML is turned on, MH is turned off, SI is closed (conducting) and S2 is opened (not conducting).

[0036] The control circuit 140 slowly charges the gate 126 of ML by maintaining the lower gate current (reverse recovery current) until ML transitions to the Miller region at time T3 and DHB is reverse biased. As a result, a sharp rise in current I LS 220 through ML is prevented, which significantly reduces a ground bounce voltage VB INT 228 between T2 and T3. In the example of FIG. 2, the ground bounce voltage VB INT 228 refers to the ground bounce voltage at the source 122 of ML (shown in FIG. 1), and in some examples the ground bounce voltage is limited to around IV.

[0037] At time T3, the low-side transistor ML transitions to the Miller region which causes a gate-to-drain capacitor CGD (not shown) of ML to start charging. As a result, at time T3, the gate- to-source voltage VGS L 212 flattens (e.g., plateaus).

[0038] At time T4, the gate-to-drain capacitor CGD is charged at which time the low-side transistor ML transitions to the FET enhancement region. As a result, at time T4 the gate-to- source voltage VGS L 212 starts to rise again, reaching VCC (e.g, approximately 5V) at time T5. Because at time T4 the gate-to-drain capacitor CGD is charged, the gate current IG_L 208 begins to fall. [0039] At time T6, the low-side digital control signal CNTR L transitions from the high state to the low state to turn off the low-side transistor ML. In response, at time T6 the control circuit 140 applies the gate current IG_L 208 having a magnitude I SLEW but of negative polarity (e.g., - I SLEW) which is also referred to as a “pull-down current”. As a result, at time T7, VGS L 212 falls back to the same voltage level as the level in the Miller region (i.e., between T3 and T4). [0040] At time T7, the output voltage Vout 224 slews upward and at time T8, Vout 224 rises above Vm which causes the current I HB 216 (e.g. the current through the high-side body diode IHB) to start rising. As the current I HB 216 rises, the current IL S 220 (e.g. current through the low-side transistor ML) starts to fall. At time T9, current I LS 220 falls to zero, and, as a consequence, I HB 216 becomes equal to Im.

[0041] Because the current I LS 220 decreases between T8 and T9, the negative rate of change of current through ML induces the negative ground bounce voltage VB INT 228 between T8 and T9. In some examples, the magnitude of the negative ground bounce voltage can be limited by decreasing the magnitude (i.e., less negative) of the pull down current -I SLEW in a similar way the magnitude of the ground bounce voltage VB INT1 228 is limited between T2 and T3.

[0042] FIG. 3 illustrates a low-side gate drive circuit 304 of the control circuit 140 of an example. The low-side gate drive circuit 304 provides the gate signal GATE L to the gate 126 to drive ML (shown in FIG. 1). The control circuit 140 also includes a high-side gate drive circuit (not shown in FIG. 3) which provides the gate signal GATE H to drive MH (shown in FIG. 1).

[0043] The low-side gate drive circuit 304 includes a first comparison circuit 310 which has a first input 312 (e.g., input 142 of FIG. 1) coupled to the system output 110, a second input 314 (e.g., input 144 of FIG. 1) adapted to receive the upper reference voltage VREF H (e.g. input 144 of FIG. 1). The first comparison circuit 310 provides a slew start signal SLEW START at an output 316 if the output voltage Vout falls below the upper reference voltage VREF H.

[0044] The low-side gate drive circuit 304 includes a first current source 320 (also referred to as reverse recovery current source 320) which has a first terminal 322 coupled to the voltage supply VCC. The first current source 320 provides a first level current I_RR (also referred to as reverse recovery current I_RR) at an output 324.

[0045] The low-side gate drive circuit 304 includes a first switch 326 (also referred to as reverse recovery switch 326) which has a first terminal 328 coupled to the second terminal 324 of the first level current source 320 (reverse recovery current source 320), a second terminal 330 coupled to the gate 126 of the low-side transistor ML (not shown in FIG. 3), a third terminal 332 coupled to the output 316 of the first comparison circuit 310, and a fourth terminal 334 coupled to receive the low-side digital control signal CNTR L. The first current switch 326 couples the first current source 320 to the gate 126 of ML responsive to CNTR L transitioning from a low state to a high state and disconnects the first level current source 320 from the gate 126 of ML responsive to an assertion of the slew start signal SLEW START by the first comparison circuit 310.

[0046] The low-side gate drive circuit 304 includes a second current source 340 (also referred to as slew current source 340) which has a first terminal 342 coupled to the voltage supply VCC. The second level current source 340 provides a second level current I SLEW (also referred to as slew current I SLEW) at an output 344. The second level current I SLEW is greater than the first level current I_RR.

[0047] The low-side gate drive circuit 304 includes a second switch 346 (also referred to as slew current switch 346) which has a first terminal 348 coupled to the output 344 of the slew current source 340, a second terminal 350 coupled to the gate 126 of ML, a third terminal 352 coupled to the output 316 of the first comparison circuit 310, and a fourth terminal 354 coupled to receive the low-side digital control signal CNTR L. The slew current switch 346 couples the slew current source 340 to the gate 126 of ML responsive to the assertion of the slew start signal SLEW START by the first comparison circuit 310.

[0048] The low-side gate drive circuit 304 includes a third current source 360 which has a first terminal 362 coupled to the common potential (e.g. ground) terminal and has a second terminal 364. The low-side gate drive circuit 304 includes a third switch 368 which has a first terminal 370 coupled to the gate 126 of ML, a second terminal 372 coupled to the second terminal 364 of the second current source 360, and a third terminal 374 coupled to receive the low-side digital control signal CNTR L. The third switch 368 couples the third current source 360 to the gate 126 responsive to CNTR L transitioning from the high state to the low state. As a result, the gate 126 is discharged to ground by the slew current source 370 and ML is turned off.

[0049] The low-side gate drive circuit 304 maintains a lower level gate current (reverse recovery current I_RR) until the output voltage Vout falls below VREF H which indicates the low-side transistor ML has transitioned to the Miller region and the high-side body diode DHB is reverse- biased. Thereafter, the low-side gate drive circuit 304 increases the gate current to a higher level (slew current I SLEW) which allows the gate-to-drain capacitor CGD (not shown in FIG. 3) to be charged in the Miller region.

[0050] In some examples, the low-side gate drive circuit 304 slowly charges the gate 126 of ML by maintaining the lower gate current (reverse recovery current I_RR) until ML transitions to the Miller region and DHB is reverse biased. As a result, a sharp rise in current I LS 220 (FIG. 2) through ML is prevented, which significantly reduces the ground bounce voltage VB INT 224. Also, by slowly charging the gate 126 of ML by maintaining the reverse recovery current until the high-side body diode DHB is reverse biased, the control circuit 140 prevents the current I_BH 216 (FIG. 2) through the high-side body diode DHB from falling below zero. Thus, DHB is reverse biased relatively slowly without the need for current to flow in the reverse direction through DHB. As a result, in some examples, the current I LS through ML does not rise above Im (FIG. 2) and thus does not fall down to Im. Because the current I LS does not have a negative rate of change, the induced ground bounce voltage VB INT does not become negative. Thus, the induced voltage VB INT is characterized by a positive pulse. The effect of this is that a wide swing in the induced ground bounce voltage VB INT is prevented and the voltage drop between the drain 120 and the source 122 of ML is reduced.

[0051] In some examples, I_RR can be adjusted (e.g., increased) to allow I LS to rise above Im but limit the amount I LS rises above Im, and also to allow VB INT to fall below zero but limit the amount VB INT falls below zero.

[0052] In response to CNTR L transitioning from the high state (e.g. a binary “1” such as a higher voltage level) to the low state (e.g. a binary “0” such as a lower voltage level), the third switch 374 couples the slew current source 360 to the gate 126 ML. As a result, the gate 126 is discharged to ground by the slew current source 360.

[0053] FIG. 4 illustrates the comparison circuit 312 in an example. The comparison circuit 312 includes a first PMOS transistor MP1 which includes a source 404 coupled to the input voltage Vm, and includes a drain 406 and a gate 408. The comparison circuit 312 includes a second PMOS transistor MP2 which includes a source 410 coupled to the drain 406 of MP1, and includes a drain 412 and a gate 414. The comparison circuit 312 includes third PMOS MP3 which includes a source 420 coupled to Vm and to a gate 422 and includes a drain 424.

[0054] The comparison circuit 312 includes a fourth PMOS MP4 which includes a source 430 coupled to the drain 424 of MP3 and includes a gate 434 coupled to the gate 408 of MP1. MP4 includes a drain 432 adapted to receive the upper reference voltage VREF H and also coupled to the gate 414 of MP2. The comparison circuit 312 includes a fifth PMOS MP5 which includes a source 450 coupled to the gate 408 of MP1 and includes a source 452 coupled to output voltage Vout via a resistor Rl. MP5 includes a gate 454 adapted to receive the upper reference voltage VREF H. The comparison circuit 312 includes an NMOS transistor MN1 which includes a drain 460 coupled to the drain 414 of MP2, and includes a source 464 coupled to ground via a resistor R2. MN1 includes a gate 466 adapted to receive an enable signal ENABLE. In some examples, the enable signal ENABLE is derived from CNTR L. For example, the enable signal ENABLE may be asserted if CNTR L transitions from a low state to a high state, and the ENABLE may be de-asserted if CNTR L transitions from a high state to a low state.

[0055] The comparison circuit 312 includes a comparator 470 which includes a first input 472 coupled to the source 464 of MN1, a second input 474 coupled to a voltage supply VDD, and a third input 476 coupled to ground. The resistor R2 is coupled between the first input 472 and ground.

[0056] In an example, the comparator 470 is a Schmitt Trigger which includes a hysteresis loop defined by VDD and ground. The comparator 470 provides SLEW START at an output 478. In some examples, MP2 may be implemented using a drain extended MOSFET (DENMOS) so as to protect MP 1 which is a low voltage device. MN1 may be implemented using a DENMOS so as to protect the Schmitt Trigger 470.

[0057] In some embodiments, VREF H is approximately equal to Vm minus five volts (Vm - 5V). When Vout is greater than Vm plus the threshold voltage of the transistor minus five volts (Vm - 5V + Vt), MP5 conducts, thus coupling the gate 408 of MP1 to Vout. As a result, MP1 conducts. As Vout starts to fall to approximately Vm, MP1 does not conduct and the resistor R2 pulls down the first input 472 of the Schmitt Trigger 470 to ground. This results in the output 478 (SLEW START) of the Schmitt Trigger 470 to become at or near zero volts. In response, I_RR is applied by the control circuit 140 (not shown in FIG. 4) to the gate 126 of the low-side transistor ML.

[0058] When Vout is less than Vm minus the threshold voltage of the transistor (Vm - Vt) (e.g., Vout falls more than Vt below Vm), MP1 conducts, and the source 464 of MN1 is pulled up to a value of approximately the voltage of the ENABLE signal minus the gate-to- source voltage of the MN1 (ENABLE - Vgs), which causes the Schmitt Trigger 470 to assert SLEW_START (e.g., SLEW START becomes a logical high or “1” value) and the slew current I SLEW is supplied to the gate 126 of the low side transistor ML. When Vout is less than Vm minus approximately five volts (Vm - 5 V), the body diode (not shown in FIG. 4) of MP4 conducts and holds the source 450 of MP5 to one diode voltage drop below Vm - 5V, thereby preventing Vgs of MP5 VGS from rising too high (e.g., too positive).

[0059] In the description and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus mean “including, but not limited to. . . .” An element or feature that is “configured to” perform a task or function may be configured (e.g., programmed or structurally designed) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Also, uses of the phrases “ground” or similar in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of the present description.

[0060] Unless otherwise stated, “approximately” preceding a value means +/- 10 percent of the stated value. As used herein, the term “modulate” shall also mean “to vary” or “to change.” [0061] The terms “node”, “terminal”, “pin” and “interconnection”, for example, are interchangeably used and referred to any connection (or interconnection) between features. These terms are not meant to be limiting with respect to a certain type of physical structure. For example, the “terminals” of a circuit element are meant to be each connection to such circuit element. Hence, an integrated resistor would be referred to have two terminals (ends) even though these “terminals” are just the two connections to the integrated resistor.

[0062] While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (“MOSFET”) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJT - e.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other type of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

[0063] While some examples suggest that certain elements are included in an integrated circuit while other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.

[0064] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.