OF A SOLID-STATE MEMORY

BACKGROUND

Technical Field

[0001 ] This disclosure relates to data storage systems. More particularly, the disclosure relates to systems and methods of write precompensation to extend life of a solid-state memory.

Description of the Related Art

[0002] Certain solid-state memory devices, such as flash drives, store information in an array of memory cells constructed with floating gate transistors. In single-level cell (SLC) flash devices, each cell stores a single bit of information. In multi-level cell (MLC) devices, each cell stores two or more bits of information. When a read operation is performed, the electrical charge levels of the cells are compared to one or more voltage reference values (also called "reading voltage level" or "voltage threshold") to determine the state of individual cells. In SLC devices, a cell can be read using a single voltage reference value. In MLC devices, a cell is read using multiple voltage references values. Certain solid-state devices allow for a memory controller to set reading voltage levels.

[0003] Various factors can contribute to data retention errors in solid-state memory devices. These factors include charge loss or leakage over time, and device wear caused by usage. When the number of bit errors on a read operation exceeds the ECC (error correction code) correction capability of the storage subsystem, the read operation fails.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various embodiments are depicted in the accompanying drawings for illustrative purposes, and should in no way be interpreted as limiting the scope of the inventions. In addition, various features of different disclosed embodiments can be combined to form additional embodiments, which are part of this disclosure. Throughout the drawings, reference numbers may be reused to indicate correspondence between reference elements. [0005] Figure 1 is a block diagram illustrating an embodiment of a solid- state storage device that performs write precompensation.

[0006] Figure 2 illustrates an embodiment of a non-volatile solid-state memory cell.

[0007] Figure 3 is a graph illustrating a probability distribution of cells in a non-volatile solid-state memory array according to an embodiment.

[0008] Figure 4 is a graph illustrating shifts in probability distribution of cells in a non-volatile solid-state memory array according to an embodiment.

[0009] Figure 5 is a graph illustrating initially setting and adjusting program verify voltage levels according to an embodiment.

[0010] Figure 6 is a flowchart of a process of performing write precompensation according to an embodiment.

[0011 ] Figure 7 is a graph illustrating memory errors versus program/erase (P/E) counts according to an embodiment.

DETAILED DESCRIPTION

[0012] While certain embodiments of the inventions are described, these embodiments are presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions.

Overview

[0013] Data storage cells in solid-state memory, such as multi-level-per- cell (MLC) flash memory, may have distinct threshold voltage distribution (V _t ) levels, corresponding to different memory states. For example, in an MLC implementation, different memory states in solid-state memory may correspond to a distribution of voltage levels ranging between reading voltage (VR) levels; when the charge of a memory cell falls within a particular range, one or more reads of the page may reveal the corresponding memory state of the cell. Programming or program verify voltages are used to program the memory cells. According to the programming charge level, memory cells store different binary data representing user data. For example, based on the charge level, each cell generally falls into one of the memory states, represented by associated data bits. Voltage distributions of different memory states of the memory cells can be separated, and reading voltage levels can advantageously be set to values in the margins between memory states.

[0014] Over time, and as a result of various physical conditions and wear from repeated program/erase (P/E) cycles, the margins between the various distribution levels may be reduced, so that voltage distributions overlap to some extent. Such reduction in read margin may be due to a number of factors, such as loss of charge due to flash cell oxide degradation, device usage which results in subjecting memory to P/E cycles, over-programming caused by erratic program steps, programming of adjacent erased cells due to heavy reads or writes in the locality of the cell (or write disturbs), and/or other factors, all of which may contribute to retention problems in a solid-state storage device.

[0015] Disclosed embodiments relate to an advanced programming or write precompensation method that extends the life of solid-state memory (e.g., NAND flash memory). As described above, memory such as NAND wears out due to repeated P/E cycles. In the case of NAND, the wear out mechanism is related to wear out or buildup of charge traps in the oxide of the NAND device. A program operation typically involves driving charges at high voltage through the NAND gate oxide in order to generate the NAND threshold voltage levels. In the early life of the NAND, the levels are well separated. Over time, the levels start to overlap, to a point where the channel cannot properly decode the data.

[0016] In some embodiments, program verify voltage levels are lowered as compared to default levels in the early life of the solid-state memory and a storage device effectively starts with overlapped levels that can produce a level of errors that is tolerable for the error detection and correction mechanism, such as Low Density Parity Code (LDPC). As the levels start to overlap more, the program verify voltage level is increased in one embodiment to reduce the overlap. In one embodiment, the overlap can be repeatedly reduced by this incremental verify voltage increase process until the default verify voltage is reached, at which point the solid-state memory is worn out as per operation under the default voltage. However, during the time while the programmed levels are overlapped, lower program verify voltages are applied which leads to less wear on the gate oxide in the memory. This results in less oxide damage and extends the life of the solid-state memory. Various embodiments disclosed here are applicable to both single-level cell (SLC) and multilevel cell (MLC) memory.

System Overview

[0017] Fig. 1 illustrates an example solid-state storage device 1 20 according to one embodiment of the invention. As is shown, the storage device 1 20 (e.g., solid state drive, etc.) includes a controller 1 30 and a non-volatile solid-state memory array 140, which comprises one or more blocks of storage, identified as Block "A" 142 through Block "N". Each block comprises a plurality of flash pages (F- pages). For example, Block A 142 of Fig. 1 includes a plurality of F-pages, identified as F-pages A (143), B, through N. In some embodiments, each "F-page" is a smallest grouping of memory cells in the non-volatile solid-state memory array 140 that can be programmed in a single operation or as a unit. Further, each F-page includes one or more error correcting code pages (E-pages). In the illustrated embodiment, each F-page includes four E-pages that are illustrated as four boxes, including E-page 144. Other embodiments may use F-pages or E-pages that are defined differently or each F-page may include greater or fewer than four E-pages.

[0018] The controller 130 can receive data and/or storage access commands from a storage interface module 1 12 (e.g., a device driver) in a host system 1 10. Storage access commands communicated by the storage interface 1 12 can include write and read commands issued by the host system 1 10. The commands can specify a logical block address in the storage device 120, and the controller 130 can execute the received commands in the non-volatile solid-state memory array 140. In a hybrid hard drive, data may be stored in magnetic media storage component (not shown in Fig. 1 ) in addition to the non-volatile solid-state memory array 140.

[0019] The storage device 120 can store data received from the host system 1 10 so that the storage device 1 20 can act as memory storage for the host system 1 10. To facilitate this function, the controller 130 can implement a logical interface. The logical interface can present to the host system 1 1 0 storage device memory as a set of logical addresses (e.g., contiguous address) where data can be stored. Internally, the controller 130 can map logical addresses to various physical memory addresses in the non-volatile solid-state memory array 140 and/or other memory module(s).

[0020] To implement error detection and correction, in one embodiment the controller 1 30 includes an error correction module 150. The error correction module 150 includes an encoder module 154 and a decoder module 156. In one embodiment, the encoder module 1 54 encodes data (e.g., host or user data) to be written to memory pages, such as E-pages, of the non-volatile solid-state memory array 140. The encoder module 1 54 may dynamically use different coding parameters to accommodate changing condition of the non-volatile solid-state memory array 140. Similarly, the decoder module 156 decodes data read from the memory pages and can similarly use different coding parameters.

[0021 ] In one embodiment, where the error detection and correction is based on LDPC, the coding parameters can include LDPC coding parameters, such as the column weight of a G (generator) or H (parity check) coding matrix, the row weight of a G or H coding matrix, a P matrix size (e.g., where the P matrix is a sub- matrix of a G or H coding matrix), and the like. Further, the encoder and decoder modules 154 and 1 56 can determine parity data for unpadded or padded user data, as well as decode user data having corresponding parity data and padding. In addition, the encoder and decoder modules 154 and 1 56 can adjust a code rate for coding data by adjusting the coding parameters. The controller 1 30 can further include internal memory (not shown), which may be of one or more suitable memory types. In some embodiments, the controller 130 is configured to perform the write precompensation functions as further described below.

Write Precompensation

[0022] Flash memory, such as multi-level cell (MLC) NAND flash memory, may store two or more bits of information per cell. For example, two-bit-per-cell memory cells can have 4 distinct programming voltage levels, and 3-bit-per-cell memory cells can have 8 distinct programming voltage levels, and so on. Therefore, individual memory cells can store different binary bits according to the amount of charge stored thereon. While certain embodiments disclosed herein are described in the context of MLCs, it should be understood that the concepts disclosed herein may be compatible with single level cell (SLC), three-level cell (TLC) technology (a type of MLC NAND), and/or other types of technology. Data is generally stored in MLC NAND flash memory in binary format.

[0023] Fig. 2 illustrates an embodiment of a non-volatile solid-state memory cell 200. The cell 200 can be part of an F-page of the non-volatile solid- state memory array 140, and store a single or multiple bits of information. As is illustrated, the cell 200 can comprise a transistor. In one embodiment, charge is stored in the floating gate by applying a large voltage across control gate and base of the transistor. Charge is trapped in the floating gate between the two oxide layers. In an embodiment when a single bit is stored in the cell 200, this allows the transistor to represent a binary "1 ", whereas a transistor without the trapped charge represents a binary "0". This can serve as a basic principle behind operation of flash memory. In an embodiment when a multiple bits, such as two bits, are stored in the cell 200, stored charge allows the transistor to represent binary states "00," "01 ," "1 0," and "1 1 ."

[0024] Fig. 3 is a graph 300 illustrating a probability distribution of cells in a non-volatile solid-state memory array. In some embodiments, when new memory blocks are used in their early life, the voltage distributions are well separated as is illustrated on Fig. 3. The horizontal axis depicted in Fig. 3 represents cell threshold voltage level. The vertical axis represents the number of cells that have the corresponding threshold voltage values. Thus, the four distribution curves represent the number of cells, broken down by the four distributions, which have the corresponding threshold voltage values. As shown, the threshold voltage distribution of the memory cells may include a plurality of distinct levels, or states (e.g., States 0- 3 in this example 2-bit-per cell MLC configuration, as shown). Reading reference values (i.e., voltage threshold levels R1 -R3) may be placed between these levels, and can be used to determine the binary value stored in a memory cell.

[0025] While the graph 300 of Fig. 3 illustrates a distribution for 2-bit-per- cell flash memories, embodiments and features disclosed herein may be applicable to other types of coding schemes. With respect to the graph 300, the coding for States 0-3 (or E, A, B, and C respectively) can be, for example, Ί 1 ,' '01 ,' '00,' and Ί Ο,' or any other coding. Each cell may generally fall into one of the illustrated states and correspondingly represents two bits. For one word line (WL), which can be connected to tens of thousands of cells in a memory array (e.g., NAND memory array), the lower digit of the cells may be referred to as the "lower page," and the upper digit may be referred to as the "upper page." For 3-bit-per-cell flash memories, there may also be intermediate digits, which may be referred to as "middle pages." Reading voltage levels and operations are dependent on the coding of these states. For example, for the coding as shown in Fig. 3 for the 2-bit-per-cell flash memories, one read at R2 may be required to read out the lower page, and two reads at both R1 and R3 may be needed to read out the upper page. As shown in the graph 300, these reading voltages may be selected between state distributions in the case where the distributions for different states are narrow so that there is no overlap between them.

[0026] The gap between the levels (i.e., margin between programmed states), in which the reading voltage levels may advantageously be positioned in certain embodiments, can be referred to as a read margin. Over time, and as a result of various physical conditions and wear, for example from the memory being subjected to repeated P/E cycles, the read margins between the various distribution levels may be reduced, resulting in both data retention problems and high reading errors. This is shown in Fig. 4 which depicts a graph 400 illustrating shifts in probability distribution of cells in a non-volatile solid-state memory array. The horizontal axis depicted in Fig. 4 represents cell threshold voltage level (after being digitized by a digital-to-analog converter), and the vertical axis represents the number of cells that have the corresponding threshold voltage values. Various plots depicted in the graph 400 illustrate shifts due to the increase in the number of P/E cycles that memory is subjected to, such as 1 (or fresh memory), 1 0, 100, 500, 1 ,000, 2,000, 3,000, 6,000, 10,000, 15,000, 20,000, and 25,000. For example, the plot 404 illustrates the distribution of new (or fresh) memory that has been programmed for the first time. As another example, the plot labeled 406 illustrates the distribution of memory that has undergone 25,000 P/E cycles.

[0027] Over time, as memory wear builds up, the threshold voltage distributions become broader. In the graph 300 illustrated in Fig. 3, the voltage levels of the new (or lightly worn) memory blocks are well separated. This separation is also illustrated in Fig. 4 by plots of fresh (e.g., fresh memory that has not been programmed) or lightly worn memory, such as that illustrated by plot 404. At this point the residual or raw bit-error rate (RBER) is low, and few memory errors, such as reading errors, are experienced. However, as is illustrated by the arrow 402, the voltage distributions become wider as the P/E cycles count increases. For example, plot 406 is a voltage distribution of memory that has experienced a large number of P/E cycles (e.g., 25,000 P/E cycles). As the voltage distributions widen due to wear, the RBER and number or memory errors increase.

[0028] In some embodiments, in order to achieve a well-defined separation of voltage levels during beginning of life of the memory, high voltage levels (e.g., program verify voltage levels) are applied at programming. In some cases, high voltage levels are standard or default voltage levels that may be suggested by the memory manufacturer. Typically, such default voltage levels are used to program the memory cells.

[0029] Fig. 5 is a graph 500 illustrating initially setting and adjusting program verify voltage levels according to an embodiment. The horizontal axis depicted in Fig. 5 represents cell threshold voltage level, and the vertical axis represents the number of cells that have the corresponding voltage values. The voltage distributions depicted on the right side of the graph 500 can correspond to states 2 (or B) and 3 (or C). As is shown in Fig. 5, memory is initially and subsequently programmed such that the voltage distributions are less separated than those programmed at the default voltage values. This is evidenced by the overlap between the voltage distributions. For example, graph 500 illustrates that voltage distributions for the two states depicted on the right side of the graph (e.g., states 2 and 3) overlap when initial program verify voltage levels lower than default levels are used to program the memory at the beginning of life. For example, memory blocks and/or pages that have experienced less than about 100 P/E cycles may be at the beginning of life. This is in contrast with the well separated distributions depicted in graph 300 of Fig. 3. The initial program verify (or programming) voltage levels used to program unworn (or lightly worn) memory depicted in Fig. 5 are lower than those depicted in Figs. 3 and 4. For example, the initial program verify voltage level for state 2 (or B) can be between 0.5-1 V lower than its default value, such as approximately 0.6 V lower, and the initial program verify voltage level for state 3 (or C) can be between 1 -2 V lower than its default value, such as approximately 1 .2 V lower. Setting the initial program verify voltages levels to lower levels can result in worse bit error rates (BER) or RBER in the early life of the memory but places less stress on the memory cells (e.g., the oxide of the transistors, such as that depicted in Fig. 2). As long as the errors experienced as a result of lowering the program verify voltage levels are below one or more error thresholds within the corrective power of the error detection and correction mechanism, using lower program verify voltage levels advantageously extends the life of the solid-state memory array 140.

[0030] As the memory repeatedly undergoes program and erase cycles, it degrades which results in a higher number of errors associated with reading data stored in the memory. In one embodiment, one or more error thresholds are selected to reflect or correspond to the corrective power of the error detection and correction mechanism. For example, an error threshold can be set or selected from the range between 0.1 % and 5% RBER (or BER). For instance, 0.8% RBER error threshold is depicted in Fig. 7. In other embodiments, any suitable error level (or levels) can be used, such as less than 0.1 %, greater than 5%, etc. For example, when LDPC is used the error level (or levels) can be selected from the range between 0.1 % and 5%. Once the error threshold is reached, the program verify voltage levels are increased by the respective step sizes. As is illustrated in Fig. 5, state 2 (or B) program verify voltage level can be increased by a 0.2 V step size as is depicted by the arrow 502. State 3 (or C) program verify voltage level can be increased by 0.4 V step size as is depicted by the arrow 504. In one embodiment, program verify voltage levels for states 2 and 3 can be increased at the same time by the respective step sizes in order to decrease the overlap. Increasing the program verify voltage levels causes increase in the separation of the voltage distributions, which is turn can reduce the memory errors (as indicated by BER or RBER). Increasing program verify voltage levels can cause more stress on the memory cells (e.g., the oxide of the transistors, such as that depicted in Fig. 2). Although 0.2 V and 0.4 V step sizes are depicted in the embodiment illustrated in Fig. 5, in other embodiments any suitable voltage step sizes can be used, such as voltages selected from the range between 0.1 V or less and 1 .6 V or more. In some embodiments, the step sizes corresponding to different states can be the same.

[0031 ] In one embodiment, the process of adjusting or shifting program verify voltages levels outlined above is repeated until the default voltage levels are reached. At that point, the default voltage is used going forward without shifting. In various embodiments, the threshold error level (or levels) that triggers program verify voltage levels increases can vary depending on a number of factors, such as the capability of error detection and correction, performance of the overall system, etc. In one embodiment, the threshold error level can be set to correspond to the absolute or maximum corrective power of capability of the error detection and correction mechanism, or at a certain offset from or percentage of the maximum corrective capability. In addition, the size of the step can also vary depending on the embodiments. In some embodiments, program verify voltage level can be increased beyond the default voltage level. Although graph 500 illustrates treatment of two voltage distributions depicted on the right side of the graph, which can correspond to states 2 (or B) and 3 (or C), other memory states, such as states 0 (or E) and 1 (or A), can be treated similarly. In some embodiments, the illustrated approaches can be applied to SLC memory or MLC memory that stores more than two bits.

[0032] Fig. 6 is a flowchart of a process 600 of performing write precompensation according to an embodiment. The process 600 can be performed by the controller 1 30 and/or the error correction module 150. The process 600 starts in block 640 where it programs memory pages (and cells) of the non-volatile solid- state memory array 140 using an initial program verify voltage level (or levels) that is lower than the default program verify voltage level (or levels). In block 650, the process 600 monitors the error levels of the memory cells. For example, the BER or RBER can be monitored by the error correction module 1 50. If the process 600 determines in block 660 that the error levels are below an error threshold level (or levels), the process continues to program the memory cells using the initial program verify voltage level (or levels) and monitor the error levels. In one embodiment, the process 600 determines in block 660 whether the error levels are within a tolerance range of the error detection and correction mechanism. If the process 600 determines in block 660 that the error levels have reached (or exceed) the error threshold level (or levels), the process transitions to block 670 where it adjusts the program verify voltage level (or levels) by a respective step size (or sizes). The adjusted program verify voltage level (or levels) is higher than the initial program verify voltage level (or levels). [0033] Fig. 7 is a graph 700 illustrating memory errors versus program/erase (P/E) counts according to an embodiment. The horizontal axis depicted in Fig. 7 represents P/E counts, and the vertical axis represents RBER. Curve 704 illustrates the RBER vs. P/E count of the memory operating under an embodiment of the write precomensation mechanism, while curve 702 illustrates the RBER vs. P/E count of the memory operating without write precomensation. In one embodiment, curve 702 is generated by plotting RBER vs. P/E counts for memory Blocks C and D and fitting a function. For example, a regression can be performed. In one embodiment, curve 704 is generated by plotting RBER vs. P/E counts for memory Blocks A and B and fitting a function. Line 706 illustrates an error threshold (or target RBER) for performing program verify voltage level adjustment, which corresponds to approximately 0.8% RBER.

[0034] The error threshold(s) at which the program verify voltage adjustments are made can correspond to a predetermined value(s), or different value(s) corresponding to different adjustment(s). In one embodiment, multiple levels of absolute or maximum corrective capacity of the error detection and correction mechanism can be used due to different code rates used by the corresponding error detection and correction mechanism (e.g., LDPC). In one embodiment, the lower the code rate (e.g., more bytes are used for error detection and correction), the higher the corrective capacity. In one embodiment, the error threshold depicted by line 706 (e.g., approximately 0.8% RBER) can correspond to the error threshold for the first code rate (or code rate 1 ), and the error threshold depicted by line 730 (e.g., approximately 1 .5% RBER) can correspond to the error threshold for the second code rate (or code rate 2). The first code rate has an absolute or maximum corrective capacity depicted by line 720 (e.g., approximately 1 .2% RBER), and the second code rate has a higher absolute or maximum corrective capacity as depicted by line 740 (e.g., approximately 2.0% RBER). In some embodiments, more than two different code rates are used. In some embodiments, various different error detection and correction mechanisms can be used. For example, one mechanism may be based on LDPC and another mechanism may be based on a different ECC scheme.

[0035] In one embodiment, the error levels experienced by memory after wear exceed the error threshold (which may correspond to maximum correction capability of the error detection and correction mechanism) as illustrated by point 708 for operation without write precomensation and 710 for operation with write precomensation. In the illustrated embodiment, curve 704 exceeds the error threshold at approximately 23,000 P/E counts, which is approximately 18% more than the point at which curve 702 exceeds the error threshold (at approximately 19,500 P/E counts). Using write precomensation results in additional life of the memory of approximately 18%. This additional life is at least in part due to reduced stress on the transistor oxide as a result of reduced or lowered program verify voltage levels. Although approximately 18% extension of memory life is illustrated in Fig. 7, in other embodiments greater or smaller gains are achieved.

[0036] Fig. 7 illustrates that utilizing write precomensation (curve 704) causes greater RBER (or number of errors) than not utilizing write precomensation (curve 702) at or near beginning of life. This increase in the error levels due to using lower program verify voltage levels is within the corrective capacity of the error detection and correction mechanism, such as LDPC. Curve 704 reaches the error threshold (which can be a signifier of the "end of life" of the memory) after a greater number of P/E cycles (or operational life) than curve 702. This results in gains of additional life of the memory. Projected RBER without using write precomensation (curve 702') and projected RBER with using write precomensation (curve 704') also illustrate that using write precomensation provides additional life of the memory as curve 704' exceeds the maximum corrective capacity of the first code rate (line 720) after a greater number of P/E cycles than curve 702'.

[0037] In one embodiment, curves 702 and 704 correspond to memory operations which do not take into account data retention issues. It is illustrative to depict RBER vs. P/E counts for memory subjected to data retention. For example, data retention can be stimulated by subjecting the memory to higher temperatures (e.g., baking the memory). For instance, memory can be baked to stimulate storing data for three months at 40 °C. Points 71 2 and 71 6 illustrate RBER vs. P/E counts for memory (e.g., Block E) in which data retention is taken into account. As is illustrated, the error levels are higher for same P/E counts as those depicted in curves 702 and 704. For example, point 714 depicts approximately 0.5% greater RBER than the point of curve 704 which corresponds to the same P/E count. As is illustrated by point 71 6, the error level of memory in which data retention is taken into account reaches the absolute corrective capacity depicted by line 720 (e.g., approximately 1 .2%). The P/E count at which this occurs can be an indicator for performing program verify voltage adjustment for memory in which data retention is not taken into account. As is illustrated by the RBER drop in curve 704, program verify voltage adjustment (increase) is performed at the P/E count corresponding to point 716. The RBER of curve 704 for the point at the P/E count of point 716 can be used as the error threshold 706.

[0038] In one embodiment, when multiple levels of maximum corrective capacity of the error detection and correction mechanism are used by the error detection and correction mechanism, the second code rate has higher corrective capacity than the first code rate. As is illustrated in Fig. 7, line 740 which corresponds to the maximum corrective capacity of the second code rate (e.g., approximately 2.0% RBER) is higher than line 720 which corresponds to the maximum corrective capacity of the first code rate (e.g., approximately 1 .2% RBER). When all program verify voltage adjustments corresponding to write precompensation at the first code rate have been performed, the code rate can be switched (e.g., lowered) to the second code rate. This increases the corrective capacity. In one embodiment, when the projected RBER with using write precomensation (curve 704') exceeds the maximum corrective capacity of the first coder rate (line 720), the error detection and correction mechanism can lower the code rate to the second code rate, which has a higher maximum corrective capacity (line 740). At that time, the error threshold can be set higher to the error threshold of the second code rate (line 730), and write precompensation can be executed at the second code rate. Life of the memory can thus be extended.

Other Variations

[0039] Those skilled in the art will appreciate that in some embodiments, other approaches and methods can be used. For example, although the example embodiments are described in the context of an LDPC encoder and decoder, the embodiments are applicable to iterative decoders other than LDPC decoders such as soft decision decoding of Reed-Solomon codes, polar decoders, turbo codes, etc. As another example, voltage levels associated with programming other than program verify voltage levels can be lowered and adjusted instead of or in addition to program verify voltage levels. For instance, programming voltage levels can be lowered initially and adjusted over lifetime of the memory. As yet another example, the non-volatile solid-state memory array can be implemented using NAND flash memory devices. Other types of solid-state memory devices can alternatively be used, such as array of flash integrated circuits, Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC- RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete NVM (non-volatile solid-state memory) chips, or any combination thereof. In one embodiment, the non-volatile solid-state memory array preferably includes multi-level cell (MLC) devices having multi-level cells capable of storing more than a single bit of information, although single-level cell (SLC) memory devices or a combination of SLC and MLC devices may be used. In one embodiment, the storage device 120 can include other memory modules, such as one or more magnetic memory modules. Other forms of storage (e.g., battery backed-up volatile DRAM or SRAM devices, magnetic disk drives, etc.) may additionally or alternatively be used. The actual steps taken in the disclosed processes, such as shown in Fig. 6, may differ from those shown in the figures. Depending on the embodiment, certain of the steps described above may be removed, others may be added.

[0040] While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. For example, the various components described may be implemented as software and/or firmware on a processor, ASIC/FPGA, or dedicated hardware. For example, those skilled in the art will appreciate that in some embodiments, the actual steps taken in the processes of some embodiments may differ from those shown in the figures. Depending on the embodiment, certain of the steps described in the example above may be removed, others may be added, and the sequence of steps may be altered and/or performed in parallel. Also, the features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. Although the present disclosure provides certain preferred embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure.