Title:
TAMPER-RESISTANT MEMORY INTEGRATED CIRCUIT AND ENCRYPTION CIRCUIT USING SAME
Document Type and Number:
WIPO Patent Application WO/2012/014291
Kind Code:
A1
Abstract:
A circuit, to which random number data outputted from a random number generating circuit using an arbiter circuit is input so as to equalize the transition probabilities of the signal lines, is configured in a memory integrated circuit in which domino RSL circuits are used to constitute a row decoder, a column decoder and a sense amplifier and in which reading or writing data from or to the memory cells in a memory cell array is performed via two complementary bit lines and which can be used in the S-Boxes of an encryption circuit.
Inventors:
FUJINO, Takeshi (Ritsumeikan University Biwako-Kusatsu Campus, 1-1-1, Nojihigashi, Kusatsu-sh, Shiga 77, 〒5258577, JP)
Application Number:
JP2010/062689
Publication Date:
February 02, 2012
Filing Date:
July 28, 2010
Export Citation:
Assignee:
THE RITSUMEIKAN TRUST (1-7 Toganoo-cho, Nishinokyo Nakagyo-ku, Kyoto-sh, Kyoto 20, 〒6048520, JP)
学校法人立命館 (〒20 京都府京都市中京区西ノ京栂尾町１番地の７ Kyoto, 〒6048520, JP)
学校法人立命館 (〒20 京都府京都市中京区西ノ京栂尾町１番地の７ Kyoto, 〒6048520, JP)
International Classes:
H04L9/10; G09C1/00; G11C7/00
Attorney, Agent or Firm:
Saegusa & Partners (Kitahama TNK Building, 1-7-1 Doshomachi, Chuo-ku, Osaka-sh, Osaka 45, 〒5410045, JP)
Claims:
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