Technical Field

The present disclosure relates to the field of integrated circuits. More specifically, the present disclosure is related to targeted burn-in on an integrated circuit.

Background

The aggressive miniaturization of semiconductor technology poses ever- increasing demands for lower minimum feature sizes running into fundamental limitations of traditional lithographic printing. Combined with processing of complex materials, semiconductor manufacturing processes have become increasingly intricate introducing a large class of processing related random and systematic defects.

Consequently, early life failures has become the single most important quality and reliability threat to in-field device functionality for the semiconductor device industry. The probability of these failures increase tremendously for high performance CPU (central processing unit) and graphics applications, server segments, and may not be addressable by engineering use conditions to meet reliability.

The traditional solution to address these manufacturing defects is to implement "burn-in" to drive early life failures within the manufacturing plant by subjecting chips to high stress conditions. This may be achieved using large expensive burn-in ovens with high temperatures up to 125 Celsius and high voltage stress. To save cost and time, the oven process may be applied to a batch, and all units in the oven may be subject to the same voltage and temperature. Conditions of the oven burn-in, such as temperature and voltage, may be determined through projections of defect distributions.

Brief Description of the Drawings

Figure 1 is an illustration of a system for targeted burn-in on an integrated circuit.

Figure 2 is a flow chart of a process for targeted burn-in on an integrated circuit. Figure 3 is a flow chart of a process for designing an integrated circuit for targeted burn-in.

Figure 4 is an illustration of selection circuitry in another system for targeted burn-in on an integrated circuit, according to various embodiments.

Figure 5 is an illustration of an interposer implementing one or more

embodiments of the present disclosure.

Figure 6 is an illustration of a computing device built in accordance with an embodiment of the present disclosure. Detailed Description

Described herein are systems and methods of targeted burn-in on an integrated circuit. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the described embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure; however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

Implementations of the disclosed embodiments may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the

semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.

Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a

semiconductor device may be built falls within the spirit and scope of the present disclosure.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosed embodiments, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosed embodiments may also be carried out using nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO ₂ ) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workf unction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some

implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and oxygen- containing metal alloys such as conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbon-containing metal alloys such as metal carbides of these metals, for example hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosed embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U- shaped layers.

In some implementations of the disclosed embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from materials such as silicon, nitrogen, carbon, and oxygen, for example silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some

implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. The dielectric materials may include elements such as silicon, oxygen, carbon, nitrogen, fluorine, and hydrogen. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 ₂ ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Referring again to oven burn-in, conditions, such as temperature and voltage, may be determined through projections of defect distributions; however, units with high defects may limit these determined conditions for the entire batch. Also, the oven may apply uniform stress conditions for all units when units with low defects do not require high stress burn-in. Furthermore, defects are may not be randomly distributed across various types and spatially on the die even though stresses may be applied uniformly in the oven. However an oven burn-in for the entire chip may lead to significant performance degradation of healthy transistors.

The drive to enable Moore's law at sub-lOnm resolution has introduced a myriad of systematic lithography related defects that significantly outnumber random process and material defects, which is a trend that is expected to grow further. Since the oven process may be transparent to distribution of defects on die, its applications to 14nm and beyond may be ineffective in weeding out systematic defects and may increasingly become severely cost prohibitive.

Some systems and methods described herein may incorporate, into the integrated circuit, functionality to burn-in at sort-test, which addresses deficiencies with some oven processes for burn-in. In some embodiments, an integrated circuit may be fabricated with first resistors of a metal layer below a substrate on which active circuitry may be formed (e.g., back-end precision template resistors) and/or second resistors on the substrate (e.g., front-end resistors such as poly resistors). The second resistors may be placed circumferentially around selected circuits/cells of the active circuitry (such as those cells with high activity and/or systematic layout defects) in order to provide highly localized temperature and voltage acceleration. This temperature and voltage acceleration can be used to eliminate the need for oven burn-in or can be used in combination with a different oven burn-in, e.g., a shorter total duration and/or lower temperature oven burn-in. These resistors may be developed and validated extensively for each process technology certification and reliably used for various elements of the integrated circuit.

In one embodiment, the selected circuits/cells may be of relatively high activity regions, relatively high power consumption regions, local hotspot regions and/or regions with high defect density. In some chips, these regions may include high density clock circuits, data inverters and/or input/out speed paths operating at high frequency and/or high activity. Such regions may draw high power and/or suffer from locally high temperatures in use, and accordingly may undergo disproportionately higher stress from a reliability perspective. The higher stress time may result in higher probability of early life failure than rest of the circuits in the chip (e.g., circuits with low to moderate activity factors). In some embodiments in which the integrated circuit is a processor, these cells/circuits may be a graphics logic block, a core logic block, a memory logic block, and/or any other block associated with high defect density due to local layout specific systematic defects and use of complex lithographic elements.

In contrast to whole die burn-in processes that may be done purely by accelerating stress time by increasing voltage and temperature over the entire chip, targeted burn-in may be utilized with considerations to local layout and distribution within specific blocks. Whole die burn-in stresses devices on the entire die, which may accelerate the degradation of devices with high defects but may also cause undesirable degradation to devices with no defects - devices that make up a majority of the chip. In contrast, targeted burn-in may target the stress to only high activity and/or high defect circuits, thus reducing degradation to the rest of the devices.

With whole-die burn-in there is no ability to target the systematic defects that arise purely out of layout specific lithographic patterning. In some embodiments of targeted burn-in, some of the associated circuitry for targeted burn-in may be fabricated around pre-identified systematic defect layouts in regions of the chip treating their burn-in independent from the rest of the chip. Since each die is different due to the position on the wafer and process variations, each die may receive a different amount of burn-in. In some embodiments, targeted burn-in may utilize a feedback mechanism from die temperature to the burn-in control. In contrast to whole-die burn-in, where a natural distribution of temperature gradients over the die can overstress/under stress regions without any control, targeted burn-in using feedback may allow precise control of temperature acceleration with accurately characterized precision resistors whose local temperature is a function of voltage and current.

Targeted burn-in may be used in addition to or instead of whole die burn-in. However, the use of whole die burn-in and targeted burn-in at the same time or in sequence may provide superior performance by reducing total burn-in time compared to whole die burn-in alone. This may significantly reduce the burn-in time in the oven by treating region-specific burn-in as part of sort test. The impact of temperature gradients may be reduced by building resistor layouts to generate hotspots. Figure 1 is an illustration of a system 100 for targeted burn-in on an integrated circuit 110. The system 100 includes a number of resistors 1-N (N may be two or more) to receive current for targeted burn-in. A first resistor of the resistors 1-N may receive current to heat a corresponding region 130 of the integrated circuit 110 to a first predetermined burn-in temperature. An Nth resistor of the resistors 1-N may receive current to heat a different corresponding region 139 of the integrated circuit 110 to a second predetermined burn-in temperature (e.g., a different predetermined burn-in temperature).

The resistors 1-N may be used for targeted burn-in on the integrated circuit 110. With targeted burn-in, better reliability may be achieved because each region may be burned-in using independent burn-in parameters (e.g., temperature, time) that are based on properties of the region (e.g., based on components of that region as opposed to a uniform burn-in temperature/time across all regions. Targeted burn- in may provide a reduction in net burn-in time. Targeting specific regions may reduce the imposed stress on devices overall in the chip, for example realizing less degradation in gate dielectric and/or transistor threshold voltage before the chip is used in the field (thus leading to better performance). Targeted burn-in may improve quality, reliability and/or performance of the outgoing products, and it also may significantly reduce burn-in time and cost, particularly for server products which may have required one hour of oven burn-in without targeted burn-in.

Some embodiments using targeted burn-in may include one or more of the other components illustrated in system 100. In some embodiments, inputs into the selection circuitry 101 may include a signal 111 to select a subset of the resistors 1- N to be activated (e.g., an address line(s) corresponding to selected resistor(s) 1-N and a burn-in enable signal). The selection circuitry 101 may also receive current 113 from a burn-in voltage supply via, for instance, a burn-in voltage rail. Selection circuitry 101 may be used to burn-in different regions at different times and/or to selectively switch on circuitry of the regions 130 and 139 at various stages of targeted burn-in to identify systematic marginal defects. Some embodiments may include a programmable cell specific burn-in voltage supply 105 to generate the signal 111 to select the subset of the resistors 1-N to receive current 113. The programmable cell specific burn-in voltage supply 105 may receive a feedback 115, such as a temperature readout line. The feedback 115 may be based on measurements output from sensors 131 and 138, which may be thermal diodes in some embodiments. The sensors 131 and 138 may output measurements indicating characteristics of the corresponding regions 130 and 139. The characteristics may be a temperature reading or information that can be used to derive a temperature reading. In some examples, a processing device (not shown) of the integrated circuit 110 or the programmable cell specific burn-in voltage supply 105 may calculate temperatures of the different regions based on changes in the resistance of the resistors 1-N. In some examples, the sensors 131 and 138 may be current sensors and the changes the in the resistance of the resistors may be detected by current sensing.

The programmable cell specific burn-in voltage supply 105 may change the signal 111 and/or 113 to stress the integrated circuit 110 differently based on the feedback 115. For instance, the programmable cell specific burn-in voltage supply 105 may increase the current 113 delivered to an active one of the resistors 1-N in order to heat the selected region to a predetermined burn-in temperature if the feedback 115 indicates that the predetermined burn-in temperature has not been reached. In another example, the programmable cell specific burn-in voltage supply 105 may decrease the current 113 delivered to an active one of the resistors 1-N if the feedback 115 indicates that a duration for applying the predetermined temperature is complete.

A first terminal of each of the resistors 1-N may be coupled to the selection circuitry 101. In some embodiments, a second terminal of each of the resistors 1-N may be coupled to a reference voltage (such as ground) and/or coupled to a component of the corresponding circuit/cell (so that the current 113 is delivered to cells/circuits of the regions 130 and 139).

In some embodiments, the resistors 1-N include a number of low resistance pathways to provide direct circuit access from a high voltage local burn-in rail to circuits of the regions 130 and 139 for voltage acceleration and/or to generate a local uniform hotspot for temperature acceleration. In some embodiments, the resistors 1-N may each consume less than 0.5 mW in response to application of the current 113. In some embodiments, the selection circuitry 101 may be an on-die multiplexor or some other component to select a burn-in resistance pathway to receive current 113. Some embodiments may use feedback 115 for accurate temperature and/or voltage control.

Figure 2 is a flow chart of a process 200 for targeted burn-in on an integrated circuit, such as the integrated circuit 110 (FIG. 1). In block 203, a subset of different active circuitry regions of an integrated circuit are selected to heat to at least a predetermined burn-in temperature for a period of time. The selection may be based on the identification of systematic defects.

In block 209, current is delivered to resistive element(s) associated with region(s) of the selected subset in order to cause the resistive element(s) to heat only the region(s) of the selected subset to at least the predetermined burn-in temperature for the period of time. Current may be delivered to the resistive element(s) corresponding at least some of the selected active circuitry regions concurrently (e.g., fully

concurrently or partially concurrently) in some examples, but in other examples current may be delivered at different times. In some examples, a duration of current delivery may be different for different resistive elements and/or different region(s) of the selected subset may be heated to different predetermined temperatures. In some embodiments, current delivery may be coupled with a feedback mechanism to indicate temperature, and current passing through a given resistor may be tuned based on this feedback. In block 214, an operability of the integrated circuit may be tested. Since no external oven or other stimulus is needed to perform the locally tunable burn-in described above, sort-test and power on may be performed in parallel (e.g., partially or fully in parallel) with targeted burn-in if the burn-in rail is powered at an appropriate voltage. In order to identify systematic marginal defects, circuit areas may be individually burned in, and test patterns may be run to excessively stress the localized burn-in area driving it to failure that would be seen early in use life due to existing manufacturing or material defects. This may be repeated for different areas, and the failures may be recorded in order to measure systematic defects.

In block 215, subsequent to an end of the targeted burn-in, in some

embodiments the resistive element(s) may be permanently disconnected from a burn-in rail used to deliver the current. For instance, a single fuse of selection circuitry similar to the selection circuitry 101 of FIG. 1 may be blown out and/or fuses of resistive element(s) may be blown out.

In block 222, in some embodiments oven burn-in of the integrated circuit may be performed to heat the active circuitry regions differently than the targeted heating of the region(s) of the selected subset. Some of the problematic regions, e.g., a majority of the problematic regions, may have been identified from targeted burn-in, which may result in a shorter duration and/or lower temperature for oven burn-in (thus minimizing an effect of oven burn-in on regions with low defects, reducing active use time of the oven, and/or enabling improvements in total manufacture time). Oven burn-in may be associated with separate operability testing in connection with the oven burn-in.

Figure 3 is a flow chart of a process 300 for designing an integrated circuit for targeted burn-in. The process 300 may be used with a hybrid burn-in scheme (e.g., a scheme that includes targeted burn-in for high risk cells and another different burn-in, such as oven burn-in).

Blocks 301-304 may be performed during circuit design and/or prior to fabricating an integrated circuit to be tested. In block 301, a designer may identify targeted circuits and/or cells of the integrated circuit based on high activity and systemic defect layouts.

In block 302, a design may classify circuits based on front-end (FE) and back-end (BE) dominated defects. The classification may be done in numerous ways, examples being based on test circuits fabrication and testing, data from previous and current process generation , yield fallout analysis of the circuits or there subcomponents, or the like, or combinations thereof.

In block 303, a designer may circumferentially layout first resistors for heating the BE circuits/cells and/or second resistors for heating the FE circuits/cells. The first resistors may be formed above a substrate on which the active circuitry is formed, and the second resistors may be formed below the substrate. In block 304, a designer may incorporate additional circuitry to deliver, e.g., selectively deliver, current to the first resistors and/or the second resistors.

After fabricating an integrated circuit based on the design, in block 305 a first sub-process of burn-in may be performed, e.g., targeted burn-in may be performed. In block 306, a second different sub-process of burn-in may be performed, e.g., oven burn- in may be performed.

Figure 4 is an illustration of selection circuitry 401 in another system for targeted burn-in on an integrated circuit, according to various embodiments. The selection circuitry 401 may be utilized in a system similar to the system 100 (FIG. 1). The selection circuitry 401 is only one example of a circuit that may be used for targeted burn-in.

Selection circuitry 401 may receive a number of address indications 449 and a burn-in enable signal 450. These signals may be similar to signal 111 of FIG. 1. Selection circuitry 401 may receive a burn-in voltage 451 to cause current (similar to current 113 of FIG. 1) to be delivered to selected circuits/cells.

Current may be output on some or all of the outputs 458 that are coupled to resistors (similar to resistors 1-N of FIG. 1). In the illustrated example, there are four of the outputs 458 each coupling to one of these resistors (e.g., four resistors). Each resistor may correspond to a different region of an integrated circuit (e.g., four regions). The resistors of the regions to be stressed may be isolated from other regions of the integrated circuit so that less stress is applied to these other regions. In some examples, each resistor may be at least a threshold distance (e.g., a predetermined distance utilized in layout/design of the integrated circuit) from every one of the other regions to isolate (e.g., partially or fully isolate) the other regions from the burn-in.

Figure 5 illustrates an interposer 1000 that includes one or more embodiments described herein. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for instance, an integrated circuit die. The second substrate 1004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004. In some embodiments, the first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000.

The interposer 1000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.

The interposer may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.

In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1000.

Figure 6 illustrates a computing device 1200 in accordance with various embodiments of the present disclosure. The computing device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208. In some implementations the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202. The integrated circuit die 1202 may include a CPU 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM).

Computing device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 1214 (GPU), a digital signal processor 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some implementations two or more antenna may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1228 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass 1230, a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1234, a camera 1236, user input devices 1238 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1240 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 1200 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 1200 includes a radio that is used to

communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

The communications logic unit 1208 enables wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1200 may include a plurality of communications logic units 1208. For instance, a first communications logic unit 1208 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1204 of the computing device 1200 includes one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments described herein. In some embodiments, the processor 1204 may include the resistors 1-N of FIG. 1, and in some embodiments the processor 1204 may also include the selection circuitry 101 of FIG. 1. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communications logic unit 1208 may also include one or more devices, such as transistors or metal interconnects, that are formed in accordance with embodiments described herein. In some embodiments, the communications logic unit 1208 may include the resistors 1-N of FIG. 1, and in some embodiments the communications logic unit 1208 may also include the selection circuitry 101 of FIG. 1.

In further embodiments, another component housed within the computing device 1200 may contain one or more devices, such as transistors or metal

interconnects, that are formed in accordance with embodiments described herein. In some embodiments, the computing device 1200 may include the resistors 1-N of FIG. 1, and in some embodiments the computing device 1200 may also include the selection circuitry 101 of FIG. 1.

In various embodiments, the computing device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1200 may be any other electronic device that processes data.

Some embodiments of targeted burn-in may apply high voltage and

temperature to only specific circuits. Some embodiments may utilize on die burn-in region selection circuitry to select the localized burn-in region.

Application of high voltage to the selected circuits may be achieved through a burn-in supply line, which may be fused out after an end of targeted burn-in. A burn-in enable signal may activate this supply line to provide the selected circuit with high voltage.

In some embodiments, a digital thermal sensor DTS (implemented using standard IC elements or using a thermal diode) may be placed in the cell to measure the local temperature generated by precision resistors (also controlled using the burn-in supply voltage). In some embodiments, temperature may be calculated via the change in resistance of the precision resistors and its effect on the current detected by a current sensor. Since resistance is temperature dependent, the temperature may be dynamically calculated by the monitoring the change in the current through a change in resistance I = f(R) = f(R ₀ (l+TCR*AT)), where TCR is the temperature coefficient of resistance and ΔΤ is the temperature change. The proportionality constant used may be process and/or integrated circuit dependent, and calibrated through test chips.

To provide local hotspots for targeted burn-in, precision resistors may be fabricated around the circuit of interest and powered with a burn-in rail to achieve the desired temperature. An example analog metal layer precision resistor with a resistance of 3000Ω running at 1.2V may produce a local hotspot of 120C (typical oven burn-in temperature ranges from 100-110 C). These hotspots may be highly localized spanning the area enclosed in the targeted cells and they may consume negligible power (<0.5 mW per resistor). A finite element simulation of

temperature hotspot caused by one such resistor used in a typical process technology (modified to represent dimensions different from the actual technology) may cause temperature increase only in a very narrow region to target local defects and small circuits in the micron range or smaller. Local temperature may rise due to a back-end precision resistor. The simulated temperature rise may be locally confined to the resistor footprint.

Examples Example 1 may be a device, comprising: resistors coupled to respective different regions of an integrated circuit; selection circuitry to select a resistor of the resistors to receive a current to cause the selected resistor to heat a corresponding region of the regions according to a predetermined burn-in temperature for the corresponding region.

Example 2 may include the subject matter of example 1 and/or any other example herein, and the different regions of the integrated circuit are formed above a substrate and at least one of the resistors are located below the substrate.

Example 3 may include the subject matter of any of examples 1-2 and/or any other example herein, and the different regions of the integrated circuit are formed above a substrate and at least one of the resistors are located above the substrate.

Example 4 may include the subject matter of any of examples 1-3 and/or any other example herein, and sensors to identify respective temperatures of the different regions of the integrated circuit.

Example 5 may include the subject matter of any of examples 1-4 and/or any other example herein, and a current generator coupled to the sensors and to generate the current based on sensor data of one of the sensors that corresponds to the selected resistor.

Example 6 may include the subject matter of any of examples 1-5 and/or any other example herein, and wherein the sensors comprise thermal diodes.

Example 7 may include the subject matter of any of examples 1-6 and/or any other example herein, and a processing device coupled to the resistors, the processing device to calculate temperatures of the different regions based on changes in resistance of the resistors; and a current generator coupled to a component to generate the current based on the identified temperatures.

Example 8 may include the subject matter of any of examples 1-7 and/or any other example herein, and the regions of the integrated circuit include only a subset of active circuitry regions of the integrated circuit. Example 9 may include the subject matter of any of examples 1-8 and/or any other example herein, and a fuse to permanently disconnect at least one of the different regions from a burn-in rail from which the current is delivered.

Example 10 may include the subject matter of any of examples 1-9 and/or any other example herein, and a first terminal of each of the resistors is coupled to the selection circuitry and a second terminal of at least one of the resistors is coupled to at least one of a cell or circuit of its corresponding region.

Example 11 may be an integrated circuit, comprising: a substrate; circuitry formed above the substrate; resistors coupled to respective different regions of the circuitry; and selection circuitry to select a resistor of the resistors to receive a current to cause the selected resistor to heat a corresponding region of the regions to a predetermined burn-in temperature.

Example 12 may include the subject matter of example 11 and/or any other example herein, and the circuitry includes at least one other region, wherein the resistors are located at least a predetermined distance from the other region to isolate the other region from the heat.

Example 13 may include the subject matter of any of examples 11-12 and/or any other example herein, and at least one of the resistors is formed above the substrate.

Example 14 may include the subject matter of any of examples 11-13 and/or any other example herein, and at least one of the resistors is formed below the substrate.

Example 15 may include the subject matter of any of examples 11-14 and/or any other example herein, and a first terminal of each of the resistors is coupled to the selection circuitry and a second terminal of at least one of the resistors is coupled to at least one of a cell or circuit of its corresponding region.

Example 16 may include a system, comprising: a processor; and at least one of a network device, a display, or a memory coupled to the processor; wherein the processor includes an integrated circuit, the integrated circuit including: circuitry formed above a substrate of the integrated circuit; resistors coupled to respective different regions of the circuitry; and selection circuitry to select a resistor of the resistors to receive a current to cause the selected resistor to heat a corresponding region of the regions to a predetermined burn-in temperature.

Example 17 may include the subject matter of example 16 and/or any other example herein, and the circuitry includes at least one other region, wherein the resistors are located at least a predetermined distance from the other region to isolate the other region from the heat.

Example 18 may include the subject matter of any of examples 16-17 and/or any other example herein, and at least one of the resistors is formed above the substrate.

Example 19 may include the subject matter of any of examples 16-18 and/or any other example herein, and at least one of the resistors is formed below the substrate.

Example 20 may include the subject matter of any of examples 16-19 and/or any other example herein, and a first terminal of each of the resistors is coupled to the selection circuitry and a second terminal of at least one of the resistors is coupled to at least one of a cell or circuit of its corresponding region.

Example 21 is a method of performing targeted burn-in on an integrated circuit, the method comprising: selecting a subset of different active circuitry regions of an integrated circuit to heat to at least a predetermined burn-in temperature for a period of time; delivering a current to one or more resistive elements associated with region(s) of the selected subset in order to cause the one or more resistive elements to heat only the region(s) of the selected subset to at least the predetermined burn-in temperature for the period of time.

Example 22 may include the subject matter of example 21 and/or any other example herein, and testing an operability of the integrated circuit subsequent to an end of the period of time.

Example 23 may include the subject matter of any of examples 21-22 and/or any other example herein, and blowing out a fuse subsequent to an end of the period of time to permanently disconnect the one or more resistive elements from a burn-in rail used to deliver the current. Example 24 may include the subject matter of any of examples 21-23 and/or any other example herein, and performing oven burn-in of the integrated circuit to heat the active circuitry regions differently than the heating of the region(s) of the selected subset.

Example 25 may include the subject matter of any of examples 21-24 and/or any other example herein, and the oven burn-in associated with at least one of a maximum temperature that is lower than the predetermined burn-in temperature or a maximum period of time that is less than the period of time.

The above description of illustrated implementations of various embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific implementations of, and examples for, various embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.