BACKGROUND OF THE INVENTION The ultimate purpose of a communication system is to transmit information from an information source to a destination over a communication channel. A communication channel is any medium over which information can be transmitted.

In many types of communication channels, such as radio communication channels, noise is inherent. The inherent noise causes errors to occur in the information transmitted over the communication channel. In order to combat the noisy channel, and hence reduce bit errors, digital cellular radio systems typically employ both error-detecting and error-correcting codes. These error control techniques introduce controlled redundancy into the information transmitted over the communication channel which can be used at the destination to detect and possibly correct errors in the channel corrupted signal.

One well-known technique for error-correction uses convolutional codes as described by Andrew Viterbi and Jim Omura in their publication Principles of Digital Communication and Coding published by McGraw-Hill, Inc., New York, N. Y. 1979.

With convolutional encoding, information bits are encoded and decoded in such a way as to estimate bits that were corrupted in transmission. Convolutional codes are typically described by the rate of the code, its constraint length, and the parity equations.

A convolutional code having a rate of k/n, where n output bits are produced for each set of k information bits. In a convolutional encoder, k information bits are shifted into the register at each interval, and n bits (where n>k) are produced to be transmitted. The redundancy bits are combinations (linear algebraic functions) of the contents of the shift register and the most recent input bit, with the specific combinatorial function depending on the convolutional code implemented. The state of the encoder at a given time is defined as the contents of the shift register. In practice, such convolutional codes may be divided into two classes: recursive and non-recursive codes. The implementation of non-recursive codes typically involves the incorporation of a feed-forward type shift register, while recursive codes generally require an encoder with a feedback circuit.

Tail bits and tail-biting are commonly used methods to terminate the trellises or coding paths, of convolutional codes for short block lengths. When tail-bits are used, the encoder is forced to a known state at the end of the block. Tail-biting constrains the encoder to begin and end at the same state, which necessarily depends on the data sequence being transmitted.

For the feed-forward or non-recursive case, it is relatively easy to find the initial state of the encoder which satisfies the tail-biting requirement. In practice, the feed-forward shift register is simply initialized with the last m bits of the input sequence, where m is the memory of the code. However, in the case of recursive codes, it is not as easy to find the initial state of the encoder which satisfies the tail- biting requirement. This is primarily the result of the feedback nature of the recursive encoder.

Therefore, there is and continues to be a need for a practical and efficient technique for determining the initial or starting state of a recursive convolutional feedback encoder to enable the use of tail-biting codes.

SUMMARY OF THE INVENTION The present invention is a convolutional feedback encoder for encoding short information sequences. The encoder comprises a shift register with a feedback circuit and an output circuit. During each coding interval, k bits from the information sequence are input to the encoder and n coded output bits are generated. Before encoding begins, the encoder is initialized to a starting state selected so that the ending state will be the same as the starting state. Thus, the present invention implements a recursive, tail-biting code.

The present invention employs an input buffer and logic circuit to initialize the convolutional feedback encoder before encoding of the information sequence begins. The information sequence is stored temporarily in an input buffer before it is passed to the convolutional feedback encoder. A logic circuit is connected between the input buffer and the convolutional feedback encoder. The logic circuit forms linear combinations of the input bits in the information sequence. Each linear combination represents one element in the shift register of the convolutional feedback encoder.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of an encoding apparatus which implements a recursive, tail-biting convolutional code.

Figure 2 is a schematic illustration of a convolutional feedback encoder used in the present invention.

Figure 3 is a schematic illustration of a logic circuit used in the encoding apparatus of the present invention.

DETAILED DESCRIPTION OF THE INVENTION Shown in Fig. 1 is a schematic diagram of an encoding apparatus generally indicated by the numeral 10. Encoding apparatus 10 is adapted to receive an uncoded, information sequence {I} comprising a plurality of input bits and produce a coded output. Encoding apparatus 10 generally includes an input buffer 12, a convolutional feedback encoder 20, and an initializing means 14 connected between the input buffer 12 and encoder 20. The input buffer 12 receives the entire information sequence {I} before passing the information sequence {I} to the convolutional feedback encoder 20. The convolutional feedback encoder 20 receives the information sequence {I} from the input buffer 12 after the convolutional feedback encoder 20 has been initialized to a predetermined starting state. The initializing means 14 determines the starting state of the encoder 20 based upon the data in the input buffer 12 and initializes the convolutional feedback encoder 20 before coding of the information sequence {I} begins. The starting state is chosen so that the encoder 20 will begin and end in the same state. Thus the encoder 10 of the present invention implements what is known as a tail-biting code.

Referring now to Figure 2, the convolutional feedback encoder 20 is shown in more detail. The encoder 20 shown in Fig. 2 is a rate 1/2 encoder. It should be appreciated, however, that encoders 20 of different rates could also be used to practice the present invention. Convolutional feedback encoder 20 comprises, in part, a shift register 22, which includes a series of shift register elements 24. The individual elements 24 comprising shift register 22, are coupled in a manner such that the contents of the register 22 may be sequentially passed or shifted serially from the first element 24 towards last element 24 of the shift register 22.

Encoder 20 further comprises a feedback circuit, indicated generally by the numeral 30. Feedback circuit 30 includes a series of feedback product nodes 32.

Each feedback product node 32 has an associated feedback coefficient denoted a,, a,...., anZ,. There is a separate feedback product node 32 associated with each element 24 of the shift register 22. The feedback product nodes 32 multiply the contents of the associated shift register elements 24 by the feedback coefficient.

The outputs of all of the feedback product nodes 32 are coupled to a feedback summation node 34 located at the front end of the shift register 22. The feedback summation node 34 also receives input from an input product node 36 whose coefficient is denoted ao. In the embodiment shown, the coefficient ao = 1. For purposes of this application, the coefficients ao, a,, a"..., a,"_, will be referred to as the feedback coefficients. The input product node 36 is not associated with a specific shift register element 24, but instead takes as input the incoming uncoded bit 14 from the input buffer 12. As shown in Fig. 1, the output of the feedback summation node 34 is then provided as an input to the first element 24 of the shift register 22, hence the recursive nature of the convolutional feedback encoder 20.

The convolutional feedback encoder 20 further includes an output circuit, generally indicated by the numeral 40. Output circuit 40 includes a series of feed- forward product nodes 42.. Each feed-forward product node 34 has an associated feed-forward coefficient denoted bo, b,..., bk. There is a separate feed-forward product node 32 associated with each element 24 of the shift register 22. It should also be noted that the first feed-forward product node 42, is not associated with a specific shift register element 24, but instead takes input directly from the output of the feedback summation node 34. The outputs of all of the feed-forward product nodes 42 are further coupled to a feed-forward summation node 44, with the output of this summation node 44 forming a first output bit A. A second output 50 is connected directly to the input of the encoder 20 which produces a second output bit B. Thus, for each bit input to the encoder 20, two coded output bits A and B are generated. These output bits A and B are sampled during each coding interval to generate a coded output.

In the particular embodiment considered and described herein, both the feedback and feed-forward coefficients are assigned binary values (0 or 1).

However, those skilled in the art will readily appreciate that the encoding apparatus 10 of the present invention is not restricted to the use of binary tap coefficients and, in fact, can be made to operate in a functionally similar manner using coefficients from any multi-level alphabet or finite field for the feedback and feed-forward taps.

Given the binary nature of the shift register contents and the coefficients of the present embodiment, it should be appreciated that both the feedback and feed- forward summation nodes 34 and 44, respectively, operate on the principle of modulo 2 arithmetic. In general, the application of modulo 2 arithmetic to a binary system leads to the following generalized summation rules which apply to both summation nodes 34 and 44: summation of all zeros equals zero, summation of an even number of ones equals zero, and summation of an odd number of ones equals one.

The binary nature of the feedback coefficients serves to effectively gate the contents of their associated register element 24. That is, with regard to the product nodes 32 and 42, a coefficient value of"1"multiplied by the contents of an associated register element 24 results in a product node output value which is equal to the contents of the register element 24, while a coefficient value of"0"results in a product node output value which is always equal to zero, regardless of the contents of the associated register element 24.

In operation, bits in the information sequence {I} are shifted into the convolutional encoder 20 one bit at a time. After entering in each bit, the outputs A and B are sampled in succession to produce two output bits. At this point, it should be appreciated that the use of tail-biting schemes with convolutional feedback encoders of the type contemplated herein necessarily requires that the shift register 22 be initialized prior to the input of the first uncoded bit. The initial state is chosen so that the final state of the encoder 20 will the same as the starting state.

As encoding begins, the first input bit is presented to the summation node 34 at the input of the encoding apparatus 10. The remaining inputs to the summation node 34 are fed back from respective elements 24 of the shift register 22. More particularly, the remaining four inputs to the summation node 34 are the outputs of each of the feedback product nodes 32 associated with the m elements of the shift register 22. Thus, the output of the convolutional feedback encoder 20 corresponding to the input bit depends upon this input bit and the bits stored in the shift register 22. The shift register 22 may be thought of as existing in one of 2m possible states where m is the number of elements 24 in the shift register 22. The output of the encoder 20 will depend on this state, and on the value of the incoming bit. When the outputs A and B have been sampled, the output of the summation node 34 is shifted into the register 22 replacing the bit in the first element of the register 22. The contents of the shift register 22 are shifted to the right one position.

The bit in the last element of the shift register 22 is effectively pushed out of the register 22. Thus, the state of the encoder 20 will change during each coding interval. The process or operation described above is repeated or executed for each incoming bit 12 in the information sequence {I}. After the final bit is input, the shift register 22 will return to its starting state.

Given the basic operational discussion of the tail-biting, recursive convolutional encoding apparatus 10 provided above, attention is now turned to the significant and non-trivial task of determining the correct initial state of the encoder 20. For feed-forward or non-recursive type encoders, it is relatively easy to find the initial state of the encoder 20 which satisfies the tail-biting requirement. In practice, the feed-forward shift register 22 is simply initialized with the last m bits of the information sequence {I}, where m is the memory of the code. However, in the case of recursive encoders such as that described above, it is not as easy to find the initial state of the encoder which satisfies the tail-biting requirement.

To understand the present invention, the operation of the convolutional feedback encoder 20 will be described in mathematical terms. This mathematical model will then be used to explain the technique used by the present invention for finding the initial state of the encoder 20. <BR> <BR> <BR> <P> The state of the encoder 20 at time n-1 is denoted as Son_,, which is defined<BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> as the state of the shift register 22 at time n-1 (i. e., the starting state). Thus, where sn is given by sn +a1sn-1+a2sn-2+...+amsn-mEq.(3)aodn It should be noted that the + sign in Equation (3) represents addition modulo 2 and dn represents the incoming bit. For a tail-biting code to exist, the starting state and the ending state of the encoder 20 must be equal. If the input sequence is N blocks long and the starting time is n=0, then the ending state is {sn-1, sn-2, sn-m+1}. This condition can be expressed as follows: s-1s-1= sN-2,s-3=sN-3,...,s-m=sN-mEq.(4)= Given the variables or terms described above, the relationship between the starting state of the encoder 20 and the information sequence {I} can be expressed as a system of linearly independent equations as follows: do = a0s0 + a1sN-1 + a2sN-2 +...+ amsN-m Eq. (5) d, =,+a,+,+...+a,Eq.(6) ... Eq.

(7) d = = a0sN-1 + a1sN-2 + a2sN-3 +...+ amsN-m-1 Eq. (8) where m is the memory of the code, dn is a bit in the information sequence {I}, and N is the length of or number of bits in the information sequences. Expressed in matrix form, Equations (5)- (8) becomes: In other words, As =d Eq. (10) In Equation (10), capital letters denote a matrix and lower case letters denote vector quantities.

It should be noted that the first row in matrix A is given by the feedback coefficients of the convolutional feedback encoder 20 and each subsequent row is a circular shift of the previous row. Row 0 (i. e., the first row) can be written in polynomial form as a (x) =aO +a, x+a2x2 + +amxm Eq. (11) <BR> <BR> <BR> <BR> <BR> Row f can be written in polynomial form as:<BR> <BR> <BR> <BR> <BR> <BR> xea (x) mod (l + XN) Eq. (12) A linear combination of rows can be written as: #g#x#a(x)mod(1 + xN) = g(x)a(x) mod (I + x Eq. (13) where g (x) has a degree less than N. Note that each g,, in g (x) has a value of"0" or"1". A value of"1"means that the corresponding row is included in the linear combination. A value of"0"means that the corresponding row is excluded.

The elements vector s in the above described model of the convolutional. feedback encoder 20 represent elements of the state of the encoder 20 at various times. Each element of the vector s represents the state of one element in the shift register 22 at different time instants. The vector d represents the information sequence {I} which is to be encoded, that is, each element of the vector d represents a bit in the information sequence {I}. As mentioned previously, it should be further appreciated that a mathematically meaningful solution to the set of simultaneous equations represented by Equation (9) can be obtained only if the system of equations is linearly independent. A detailed explanation of this mathematical requirement is beyond the scope of this disclosure, and as such will not be discussed in further detail herein. However, it should suffice to state that the requirement of linear independence exists, and that linear independence of the system of equations may be verified using well known and commonly employed mathematical techniques. More particularly, linear independence of the system of simultaneous equations may be insured through careful selection of the feedback coefficients for the convolutional feedback encoder 20. Those skilled in the art will appreciate that sets or libraries of suitable feedback coefficients have been previously calculated and tabulated, and are well known and readily available for implementation in convolutional feedback encoders of the type contemplated herein.

It can be shown that a tail-biting circle exists for a given set of feedback coefficients if and only if a (x) and (1 + xN) are relatively prime, where a (x) is the feedback polynomial and N is the number of bits in the information sequence. If a unique tail- biting circle does not exist, this implies that the matrix A is singular and may not be inverted, i. e., the rows are linearly dependent. This also implies that if a (x) divides (1 + un) or if the Hamming weight of a (x) is even, a unique tail-biting circle does not exist for the given set of feedback coefficients. Thus care should be exercised in selecting a feedback polynomial a (x) to ensure that these conditions are satisfied.

Given that a particular set of feedback coefficients is capable of providing a unique tail-biting circle, as discussed above, the next concern becomes actually solving the system of equations and determining the starting state of the encoder 20.

The brute force method of finding the starting state of the encoder 20 would be to start the encoder 20 at every possible state and check whether it converges to the same state at the end of the information sequence {I}. If the starting and ending states are the same, then the tail-biting circle has been found. While this approach is certainly functional, it is not particularly efficient.

Another approach involves solving Equation (10) for the starting state vector s by inverting the matrix A, which results in the following relation: s = A-'d Eq. (14) where s is a vector whose elements {Sn l,, Sn m}. denote the starting state and d is a vector representing the uncoded information sequence {I}.

The matrix A-'functions as a selection matrix. To find the starting state of the encoder, the information sequence {I} represented by the vectord, is multiplied by the selection matrix A-'. The initial state of the first register element of the encoder 20 is equal to the vector d multiplied by the first row of the selection matrix A-', and the initial state of the plh element is equal to the vector d multiplied by the pth row of the selection matrix A-'. The multiplication of the vector d by a row in the selection matrix A-'results in a linear combination of the selected bits in the information sequence {I}. Thus, each row on the selection matrix A-'represents one linear combination of selected input bits in the information sequence {I}. These linear combinations represent the starting state of each element 24 in the shift register 22. Thus, the rows of the selection matrix A-'can be thought of as selection vectors for corresponding elements of the shift register 22.

13 It should be noted that since the same encoder configuration will be used in any communication application over repeated calls, the calculation of the selection <BR> <BR> <BR> <BR> <BR> <BR> matrix A-'need be done only once, and can be performed off-line. Also, it should be noted that only the first m elements of the vector s determine or define the initial state of the shift register 22. Thus, only a subset of the matrix multiplication needs to be performed. All multiplication and addition is modulo 2.

Still another method takes advantage of the circular nature of the matrix A to directly compute the starting state of each shift register element 24 without having to first compute the matrix A. More particularly, this approach assumes that functions p (x) and q (x) exist such that: p (x)a(x) + q(x)(1 + xN) = 1 Eq. (15) <BR> <BR> <BR> <BR> <BR> <BR> where p (x) and q (x) can be found using Euclid's algorithm. Stated another way:<BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> p (x) a (x) = 1 mod (l+ x N) Eq. (16) Thus, xkp (x) a (x) =x mod (l+x () Eq. (17) Therefore, if a matrix P is chosen such that its #th row is given by xf p (x), then it follows that: IEq.(18)PA= where I is the identity matrix, and consequently P must be the inverse of A. With these relationships established, the s vector and hence the starting state of the shift register 22 can be found from the following equation: In other words, to find the state of the element sN-f of the encoder 20, first find the vector p (x) by Euclid's algorithm. Euclid's algorithm is described in Finite Fields for Computer Scientists and Engineers by Robert J. McEliece published by Kluwer Academic Publishers. The vector p (x) is equal to the first row of the selection matrix A-'. Multiply the information sequence {I} by p (x) to obtain the starting state of the first element. For each subsequent element, circularly shift p (x) to the right and multiply by the information sequence {I} to get the starting state.

The encoding method described above can be implemented in a variety of ways. One way to implement the encoding method would be to use a shift register for the input buffer 12. The input buffer 12 would receive the entire input sequence before passing the input sequence to the convolutional feedback encoder 20. A microprocessor could be used to calculate the starting state of the encoder 20 based upon the contents of the input buffer 12. The microprocessor could use any of the methods described above to calculate the starting state of the encoder 20. After calculating the starting state, the microprocessor would initialize the encoder 20. At that point in time, the bits in the information sequence {I} stored in the input buffer 12 would be clocked into the convolutional feedback encoder 20 for encoding.

Another implementation uses a logic circuit 16 connected between the input buffer 12 and the shift register 22 of the convolutional feedback encoder 20 to initialize the encoder 20. In this embodiment, which is shown in Figure 3, the elements of the input buffer 12 are connected in a predetermined fashion to a series of summation nodes 18 which are connected to elements 24 of the shift register 22.

The summation nodes 16 form linear combinations of selected bits in the information sequence {I} which are then passed to a respective element 24 in the shift register 22. The logic circuit 16 could be hard-wired. The output of the summation nodes 18 in the logic circuit 16 would be clocked so that the encoder 20 is initialized after the input buffer 12 is filled with a new information sequence {I}.

From the forgoing, it is apparent that the techniques described above to find the starting state of the encoder 20 can be implemented easily using a either a processor or logic circuit. These techniques enable the use of tail-biting codes in recursive convolutional encoders which are useful for encoding relatively short information sequences.

It is to be appreciated that encoders involving multiple bit inputs with multiple shift registers can be treated as encoders with a single multilevel input and a single multilevel arithmetic being performed. Thus, the methods of this application are applicable in these cases also.

The present invention may, of course, be carried out in other specific ways than those herein set forth without departing from the spirit and essential characteristics of the invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.