Title:
TECHNIQUE FOR SUB-MICROSECOND LATENCY MEASUREMENT ACROSS A BUS
Document Type and Number:
WIPO Patent Application WO/2014/167421
Kind Code:
A3
Abstract:
Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus.
Inventors:
BATTYANI MARC (US)
CLAIREMBAULT JONATHAN (FR)
XU LONG (FR)
CLAIREMBAULT JONATHAN (FR)
XU LONG (FR)
Application Number:
PCT/IB2014/001423
Publication Date:
January 08, 2015
Filing Date:
March 10, 2014
Export Citation:
Assignee:
NOVASPARKS S A (FR)
International Classes:
G06F1/04
Other References:
DANIEL GALLANT: "Choose The Optimum Clock Source For PCI Express Applications", 23 May 2012 (2012-05-23), XP055146096, Retrieved from the Internet [retrieved on 20141013]
Attorney, Agent or Firm:
HARBSMEIER, Felix et al. (Beselerstrasse 4, Hamburg, DE)
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