SUBSTRATE

This application claims priority of U.S. Provisional Application Serial No.

61/770642, filed February 28, 2013, the disclosure of which is herein incorporated by reference in its entirety.

FIELD

The present disclosure relates to an electrostatic clamp, more particularly to a method of clamping and declamping a target on an electrostatic clamp.

BACKGROUND

Ion implantation process is used in manufacturing electrical and optical devices. It is a process by which dopants or impurities are introduced into a target to alter the target's mechanical, electrical, and/or optical property. In integrated circuit (IC) device manufacturing, the target may be silicon or other semiconductor wafers, or one or more features or films thereon. Generally, the dopants or impurities may have one or more properties that differ from the properties of the target. Once implanted into a region in the target, the dopants or impurities may alter the region's properties. During the ion implantation process, the target or the wafer 102 may be supported on a platen 112. As illustrated in FIG. 1, the platen 112 may comprise one or more electrodes 114 that are electrically connected to a power supply 116. In some embodiments, multiple concentric electrodes 114 are provided where one of the electrodes may be an inner electrode 114a and another electrode may be an outer electrode 114b. In other embodiments, multiple electrodes are provided at opposite sides of the platen 112. To electrostatically clamp the wafer 102 onto the platen, the bias voltage may be applied to the electrodes 114. In some embodiments, opposite voltage may be applied to different electrodes. For example, one of the electrodes 114 may be applied with positive voltage, whereas negative voltage is applied to another electrode 114. The magnitude of the clamping voltage may be the same or different.

Referring to FIG. 2, there is shown timing of the clamping voltage provided from the power supply 116 to one or more electrodes 114 in the platen 112. After the wafer 102 is loaded onto the platen 112, clamping voltage (Vi) is applied to the electrodes 114 at Ti and the wafer 102 is electrostatically clamped onto the platen 112. Although not illustrated, those skilled in the art will recognize that if two or more electrodes are provided, one of the electrodes will be applied positive Vi and the other electrode will be applied with negative Vi. The voltage applied to the electrodes 114 may be maintained during the ion implantation process, and the wafer 102 may remain clamped on the platen 112. After the ion implantation is completed (i.e. T ₂ ), the clamping voltage Vi is no longer applied to the electrodes 114, and the wafer 102 is removed from the platen 112. In some embodiments, the wafer 102 removal process may include lifting and separating the wafer 102 from the platen 112 with lift pins (not shown) and removing the wafer 102 from the platen 112. As known in the art, the voltage applied to the electrodes 114 is different from the voltage directly applied to the wafer 102 to process the wafer 102. For example, in some process, negative voltage is applied to the wafer 102 to attract positively charged ions. To clamp the wafer 102, voltage is applied to the electrodes 114 in the platen 112 to electrostatically clamp the wafer 102 onto the platen 112. As is also known in the art, a dielectric layer is disposed between the electrodes 114 and the wafer 102 to electrically isolate the wafer 102 from the electrodes 1 14.

The ion 10 directed and implanted into the wafer 102 may be positively charged ions 10. The residual charge in the wafer 102 due to implanting charged ions may cause at a portion of the wafer 102 to stick to the platen 1 12 surface. Unloading such a wafer 102 may be difficult. Also, if a layer of dielectric film is coated on the lower surface of the wafer 102, the neutralization of the charged ions and electrons may be delayed, thus causing the wafer 102 to remain attached to the platen 1 12 surface even when the clamping voltage has been removed. Attempting to separate the wafer 102 from the platen 1 12 surface using excessive force may result in wafer breakage. The wafer breakage may be more frequent if a layer of dielectric film (not shown) is coated on the lower surface of the wafer 102.

As such, a new method of clamping and declamping is needed.

SUMMARY

Methods of clamping and declamping a wafer from a platen are disclosed. The platen comprises one or more electrodes, which are electrically biased to electrostatically clamp the wafer to the platen. The electrode is biased to a first voltage where the wafer may be processed. Thereafter, one or more voltages are subsequently applied to the electrodes. In some embodiments, each subsequent voltage is less than the previously applied voltage. In other embodiments, one or more of the subsequent voltages may be greater than the previously applied voltage. This sequence of voltage may reduce the likelihood that the wafer will stick or adhere to the platen during the removal process.

In one embodiment, the method of clamping and declamping a wafer from a platen comprises placing the wafer on the platen, where the platen comprises an electrode for clamping the wafer onto the platen, while the electrode is biased at an initial voltage; applying a first voltage to the electrode of the platen to electrostatically clamp the wafer to the platen, the first voltage greater than the initial voltage; applying a second voltage to the electrode, the second voltage less than the first voltage and greater than the initial voltage; and removing the wafer from the platen after the application of the second voltage to the electrode.

In another embodiment, the method of clamping and declamping a wafer from a platen comprises placing the wafer on the platen where the platen comprising an electrode for clamping the wafer onto the platen, while the electrode is biased at an initial voltage; applying a first voltage to the electrode to electrostatically clamp the wafer to the platen, the first voltage greater than the initial voltage; applying a second voltage to the electrode, lower than the first voltage and greater than the initial voltage; applying a third voltage, higher than the second voltage and lower than the first voltage, to the electrode; and removing the wafer after application of the third voltage to the electrode.

In another embodiment, the method of clamping and declamping a wafer from a platen comprises placing the wafer on the platen, the platen comprising an electrode for clamping the wafer, while the electode is biased at 0 volts; applying a first voltage to the electrode to electrostatically clamp the wafer to the platen, the first voltage between 100V and 1000V; applying a second voltage to the electrode, the second voltage less than the first voltage and between 5V and 600V; applying a third voltage to the electrode after application of the second voltage, wherein the third voltage is less than the second voltage and between 5V and 600 V; and removing the wafer from the platen after the application of the third voltage to the electrode. BRIEF DESCRIPTION OF THE FIGURES

For a better understanding of the present disclosure, reference is made to the accompanying drawings, which are incorporated herein by reference and in which:

FIG. 1 shows an exemplary system for clamping and declamping a wafer to a platen according to the prior art;

FIG. 2 shows a timing diagram that may be used with the system of FIG. 1 according to the prior art;

FIG. 3 shows a timing diagram that can be applied to the system of FIG. 1 according to one embodiment;

FIG. 4 shows a timing diagram that can be applied to the system of FIG. 1 according to a second embodiment;

FIG. 5 shows a timing diagram that can be applied to the system of FIG. 1 according to a third embodiment; and

FIG. 6 shows a timing diagram that can be applied to the system of FIG. 1 according to a fourth embodiment.

DETAILED DESCRIPTION

The present disclosure will now be described in more detail with reference to particular embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to particular embodiments, it should be understood that the present disclosure is not limited thereto.

Referring to FIG. 3, there is shown an exemplary method of clamping and declamping a wafer according to one embodiment of the present disclosure. In this figure, the method is described with respect to the timing of the clamping voltage provided from the power supply 116 to one or more electrodes 114 in the platen 112. For clarity and simplicity, the method of the present embodiment will be described with respect to components shown in FIG. 1. As such, the method of the present embodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen 112. Thereafter, at T _ls the electrodes 114 in the platen 112 may be applied with a first voltage Vi, and the wafer 102 may be electrostatically clamped onto the platen 112. Prior to applying the first voltage Vi, the electrodes 114 may be applied with V ₀ . In the present disclosure, the Vo may be zero voltage or some other voltage less than Vi. In the present disclosure, the first voltage Vi may be the clamping voltage, and the voltage may be in the range of about 100 V to about 1 kV. In one embodiment, the first voltage may be about 150 V. In another embodiment, the first voltage may be about 250 V. In another embodiment, the first voltage may be about 500 V. Yet in another embodiment, the first voltage may be about 750 V. If the platen comprises inner and outer electrodes 114a and 114b, one of the electrodes 114a and 114b may be applied with positive first voltage Vi and the other one of the electrodes 114a and 114b may be applied with negative first voltage. The first voltage Vi may be maintained until T ₂ as illustrated in the figure, when a second voltage V ₂ is applied to the electrodes 114. Between Ti and T ₂ , the ion implantation process is performed.

As illustrated in FIG. 3, the second voltage V ₂ applied to the electrode 114 may be less than the first voltage Vi. For example, the second voltage V ₂ may range from about 5 V to about 100 V. In one embodiment, the second voltage V ₂ may be about 5 V. In another embodiment, the second voltage V ₂ may be about 15 V. In another embodiment, the second voltage V ₂ may be about 25 V. Yet in another embodiment, the second voltage V ₂ may be about 35 V.

After T ₂ , the process to dechuck/remove the wafer 102 from the platen 1 12 may be performed. For example, the wafer 102 may be dechucked from the platen 1 12 and the wafer 102 may be removed from the platen 1 12 at T ₂ or after T ₂ . For example, the process to dechuck/remove the wafer 102 from the platen 1 14 may be performed at or after T ₂ , when the electrodes 1 14 are applied with the second voltage V ₂ that is less than the first voltage Vi, but greater than Vo applied to the electrodes prior to Ti. In one embodiment, the process may be performed at or after T _f when Vo is applied to the electrodes 1 14.

Referring to FIG. 4, there is shown another exemplary method of clamping and declamping a wafer according to another embodiment of the present disclosure. In this figure, the method is described with respect to the timing of the clamping voltage provided from the power supply 1 16 to one or more electrodes 1 14 in the platen 1 12. For clarity and simplicity, the method of the present embodiment will be described with respect to components shown in FIG. 1. As such, the method of the present embodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen 1 12. Thereafter, at T _ls the electrodes 1 14 in the platen 1 12 may be applied with a first voltage Vi, and the wafer 102 may be electrostatically clamped onto the platen 1 12. Prior to applying the first voltage Vi, the electrodes 1 14 may be applied with Vo. In the present disclosure, the Vo may be zero voltage or some other voltage less than Vi. In the present disclosure, the first voltage Vi may be the clamping voltage, and the voltage may be in the range of about 100 V to about 1 kV. In one embodiment, the first voltage may be about 150 V. In another embodiment, the first voltage may be about 250 V. In another embodiment, the first voltage may be about 500 V. Yet in another embodiment, the first voltage may be about 750 V. If the platen comprises inner and outer electrodes 1 14a and 1 14b, one of the electrodes 1 14a and 1 14b may be applied with positive first voltage Vi and the other one of the electrodes 1 14a and 1 14b may be applied with negative first voltage. The first voltage Vi may be maintained until T ₂ as illustrated in the figure, when a second voltage V ₂ is applied to the electrodes 1 14. Between Ti and T _2j the ion implantation process is performed.

As illustrated in FIG. 4, the second voltage V ₂ applied to the electrode may be less than the first voltage Vi, but greater than V ₀ . In the present embodiment, the second voltage V ₂ may be any voltage ranging from about 75 V to about 800 V. In one example, the second voltage may be about 100 V. In another example, the second voltage may be about 150 V. In another example, the second voltage may be about 300 V. In another example, the second voltage may be about 400 V. In another example, the second voltage may be about 500 V. Yet in another example, the second voltage may be about 600 V.

The second voltage V ₂ may be applied to the electrodes 1 14 until T ₃ when the electrodes 1 14 in the platen 1 12 are applied with a third voltage V ₃ . In the present embodiment, the third voltage V ₃ applied to the electrode may be less than the second voltage V ₂ , but greater than V ₀ . In the present embodiment, the third voltage V ₃ may be any voltage ranging from about 50 V to about 600 V. In one example, the third voltage V ₃ may be about 80 V. In another example, the third voltage V ₃ may be about 150 V. In another example, the third voltage V ₃ may be about 300 V. In another example, the third voltage V ₃ may be about 450 V. In another example, the third voltage V ₃ may be about 500 V. Yet in another example, the third voltage V ₃ may be about 550 V. The third voltage V ₃ may be applied to the electrodes 114 until T ₄ when the electrodes 114 in the platen 112 are applied with a fourth voltage V ₄ . In the present embodiment, the fourth voltage V ₄ applied to the electrode may be less than the third voltage V ₃ , but greater than V ₀ . In the present embodiment, the fourth voltage V ₄ may be any voltage ranging from about 25 V to about 500 V. In one example, the fourth voltage V ₄ may be about 25 V. In another example, the fourth voltage V ₄ may be about 75 V. In another example, the fourth voltage V ₄ may be about 100 V. In another example, the fourth voltage V ₄ may be about 200 V. In another example, the fourth voltage V ₄ may be about 300 V. Yet in another example, the second voltage may be about 400 V.

The fourth voltage V ₄ may be applied to the electrodes 114 until T5 when the electrodes 114 in the platen 112 are applied with a fifth voltage V ₅ . In the present embodiment, the fifth voltage V ₅ applied to the electrode may be less than the fourth voltage V ₄ , but greater than V ₀ . In the present embodiment, the fifth voltage V ₅ may be any voltage ranging from about 5 V to about 50 V. In one example, the fifth voltage V ₅ may be about 10 V. In another example, the fifth voltage V ₅ may be about 15 V. In another example, the fifth voltage V ₅ may be about 30 V. In another example, the fifth voltage V ₅ may be about 50 V. In another example, the fifth voltage V ₅ may be about 75 V. Yet in another example, the fifth voltage V ₅ may be about 100 V. The fifth voltage V ₅ may be applied until T _f when Vo is applied to the electrodes 114.

After T ₂ , the process to dechuck/remove the wafer 102 from the platen 112 may be performed. For example, the wafer 102 may be dechucked from the platen 112 and the wafer 102 may be removed from the platen 112 at T ₂ of after T ₂ . In particular, the process to dechuck/remove the wafer 102 from the platen 114 may be performed at T ₂ , T ₃ , T ₄ , T5 or T _f . Referring to FIG. 5, there is shown another exemplary method of clamping and declamping a wafer according to another embodiment of the present disclosure. In this figure, the method is described with respect to the timing of the clamping voltage provided from the power supply 116 to one or more electrodes 114 in the platen 112. For clarity and simplicity, the method of the present embodiment will be described with respect to components shown in FIG. 1. As such, the method of the present embodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen 112. Thereafter, at T _ls the electrodes 114 in the platen 112 may be applied with a first voltage Vi, and the wafer 102 may be electrostatically clamped onto the platen 112. Prior to applying the first voltage Vi, the electrodes 114 may be applied with V ₀ . In the present disclosure, the Vo may be zero voltage or some other voltage less than Vi. In the present disclosure, the first voltage Vi may be the clamping voltage, and the voltage may be in the range of about 100 V to about 1 kV. In one embodiment, the first voltage may be about 150 V. In another embodiment, the first voltage may be about 250 V. In another embodiment, the first voltage may be about 500 V. Yet in another embodiment, the first voltage may be about 750 V. If the platen comprises inner and outer electrodes 114a and 114b, one of the electrodes 114a and 114b may be applied with positive first voltage Vi and the other one of the electrodes 114a and 114b may be applied with negative first voltage. The first voltage Vi may be maintained until T ₂ as illustrated in the figure, when a second voltage V ₂ is applied to the electrodes 114. Between Ti and T _2j the ion implantation process is performed.

At T ₂ , the second voltage V ₂ applied to the electrodes 114. The second voltage V ₂ in the present embodiment may be less than the first voltage Vi, but greater than Vo. In the present embodiment, the second voltage V ₂ may be any voltage ranging from about 5 V to about 600 V. In one example, the second voltage may be about 15 V. In another example, the second voltage may be about 50 V. In another example, the second voltage may be about 75 V. In another example, the second voltage may be about 100 V. In another example, the second voltage may be about 150 V. Yet in another example, the second voltage may be about 300 V.

The second voltage V ₂ may be applied to the electrodes 114 until T ₃ when the electrodes 114 in the platen 112 are applied with a third voltage V ₃ . In the present embodiment, the third voltage V ₃ applied to the electrode may be greater than the second voltage V ₂ , but less than the first voltage Vi. In the present embodiment, the third voltage V ₃ may be any voltage ranging from about 50 V to about 400 V. In one example, the third voltage V ₃ may be about 75 V. In another example, the third voltage V ₃ may be about 150 V. In another example, the third voltage V ₃ may be about 250 V. In another example, the third voltage V ₃ may be about 350 V. In another example, the third voltage V ₃ may be about 400 V. Yet in another example, the third voltage V ₃ may be about 450 V.

The third voltage V ₃ may be applied to the electrodes 114 until T ₄ when the electrodes 114 in the platen 112 are applied with a fourth voltage V ₄ . In the present embodiment, the fourth voltage V ₄ applied to the electrode may be less than the third voltage V ₃ , but greater than Vo. In the present embodiment, the fourth voltage V ₄ may be equal to the second voltage V ₂ . However, the present disclosure does not preclude the fourth voltage being greater or less than the second voltage V ₂ . In the present embodiment, the fourth voltage V ₄ may be any voltage ranging from about 25 V to about 600 V. In one example, the fourth voltage V ₄ may be about 15 V. In another example, the fourth voltage V ₄ may be about 50 V. In another example, the fourth voltage V ₄ may be about 75 V. In another example, the fourth voltage V ₄ may be about 100 V. In another example, the fourth voltage V ₄ may be about 150 V. Yet in another example, the fourth voltage V ₄ may be about 300 V.

In the present embodiment, the fourth voltage V ₄ may be applied to the electrodes 114 until T _f when the electrodes 114 in the platen 112 are applied with V ₀ .

After T ₂ , the process to dechuck/remove the wafer 102 from the platen 112 may be performed. Although the wafer 102 dechucking/removing process may be performed any time after T ₂ , the process may preferably performed after T ₄ , or any time after the third voltage V ₃ higher than the second voltage V ₂ is applied.

Referring to FIG. 6, there is shown another exemplary method of clamping and declamping a wafer according to another embodiment of the present disclosure. In this figure, the method is described with respect to the timing of the clamping voltage provided from the power supply 116 to one or more electrodes 114 in the platen 112. For clarity and simplicity, the method of the present embodiment will be described with respect to components shown in FIG. 1. As such, the method of the present embodiment should be understood in relation to FIG. 1.

In the present embodiment, the wafer 102 may be loaded onto the platen 112. Thereafter, at T _ls the electrodes 114 in the platen 112 may be applied with a first voltage Vi, and the wafer 102 may be electrostatically clamped onto the platen 112. Prior to applying the first voltage Vi, the electrodes 114 may be applied with V ₀ . In the present disclosure, the Vo may be zero voltage or some other voltage less than Vi. In the present disclosure, the first voltage Vi may be the clamping voltage, and the voltage may be in the range of about 100 V to about 1 kV. In one embodiment, the first voltage may be about 150 V. In another embodiment, the first voltage may be about 250 V. In another embodiment, the first voltage may be about 500 V. Yet in another embodiment, the first voltage may be about 750 V. If the platen comprises inner and outer electrodes 114a and 114b, one of the electrodes 114a and 114b may be applied with positive first voltage Vi and the other one of the electrodes 114a and 114b may be applied with negative first voltage. The first voltage Vi may be maintained until T ₂ as illustrated in the figure, when a second voltage V ₂ is applied to the electrodes 114. Between Ti and T ₂ , the ion implantation process is performed.

At T ₂ , the second voltage V ₂ applied to the electrodes 114. The second voltage V ₂ in the present embodiment may be less than the first voltage Vi, but greater than Vo. In the present embodiment, the second voltage V ₂ may be any voltage ranging from about 5 V to about 600 V. In one example, the second voltage may be about 15 V. In another example, the second voltage may be about 50 V. In another example, the second voltage may be about 150 V. In another example, the second voltage may be about 250 V. In another example, the second voltage may be about 350 V. Yet in another example, the second voltage may be about 450 V.

The second voltage V ₂ may be applied to the electrodes 114 until T ₃ when the electrodes 114 in the platen 112 are applied with a third voltage V ₃ . In the present embodiment, the third voltage V ₃ applied to the electrode may be less than the second voltage V ₂ , but greater than Vo. In the present embodiment, the third voltage V ₃ may be any voltage ranging from about 5 V to about 600 V. In one example, the third voltage V ₃ may be about 15 V. In another example, the third voltage V ₃ may be about 50 V. In another example, the third voltage V ₃ may be about 75 V. In another example, the third voltage V ₃ may be about 100 V. In another example, the third voltage V ₃ may be about 150 V. Yet in another example, the third voltage V ₃ may be about 300 V.

The third voltage V ₃ may be applied to the electrodes 114 until T ₄ when the electrodes 114 in the platen 112 are applied with a fourth voltage V ₄ . In the present embodiment, the fourth voltage V ₄ applied to the electrodes 114 may be greater than the third voltage V ₃ , but less than the first voltage Vi. In the present embodiment, the fourth voltage V ₄ may be equal to the second voltage V ₂ . However, the present disclosure does not preclude the fourth voltage V ₄ being greater or less than the second voltage V ₂ . In the present embodiment, the fourth voltage V ₄ may be any voltage ranging from about 5 V to about 600 V. In one example, the fourth voltage V ₄ may be about 15 V. In another example, the fourth voltage V ₄ may be about 50 V. In another example, the fourth voltage V ₄ may be about 150 V. In another example, the fourth voltage V ₄ may be about 250 V. In another example, the fourth voltage V ₄ may be about 350 V. Yet in another example, the fourth voltage V ₄ may be about 450 V.

The fourth voltage V ₄ may be applied to the electrodes 114 until T5 when the electrodes 114 in the platen 112 are applied with a fifth voltage V ₅ . In the present embodiment, the fifth voltage V ₅ applied to the electrodes 114 may be less than the fourth voltage V ₄ , but greater than V ₀ . In the present embodiment, the fifth voltage V ₅ may be equal to the third voltage V ₃ . However, the present disclosure does not preclude the fifth voltage V ₅ being greater or less than the third voltage V ₃ .

After T ₂ , the process to dechuck/remove the wafer 102 from the platen 112 may be performed. Although the wafer 102 dechucking/removing process may be performed any time after T ₂ , the process may preferably performed after T ₃ or T5, or any time after the fourth voltage V ₄ higher than the third voltage V ₃ is applied.

Herein, techniques for chucking and dechucking a wafer during wafer processing process are disclosed. The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.