Title:
TEMPLATED MEMORY TEST PATTERN GENERATOR AND METHOD
Document Type and Number:
WIPO Patent Application WO/2023/221620
Kind Code:
A1
Abstract:
Disclosed in the present invention are a templated memory test pattern generator and a method. The templated memory test pattern generator comprises a test processor, a simple memory pattern generator (SMPG), a channel timing and formatter, and a pin electronic, wherein the SMPG comprises an X address generator, a Y address generator, a D data generator, and SMPG and channel mapping; an incoming-wire end of the channel timing and formatter is connected to the SMPG and channel mapping, and an outgoing-wire end of the channel timing and formatter is connected to the pin electronic; and pieces of parallel data which are obtained by means of calculation by the SMPG according to an SMPG resource mapping table provided by an upper computer are mapped to pins of a device under test on a one-to-one basis. The present invention can effectively reduce the number of test vectors in an image file. In addition, by means of the solution, after templating, the reuse rate of a test program can be improved, and the development cycle of a test scheme is shortened.
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Inventors:
MAO GUOLIANG (CN)
Application Number:
PCT/CN2023/081506
Publication Date:
November 23, 2023
Filing Date:
March 15, 2023
Export Citation:
Assignee:
MACROTEST SEMICONDUCTOR TECH CO LTD (CN)
International Classes:
G06F11/22
Foreign References:
| CN114637638A | 2022-06-17 | |||
| CN113687994A | 2021-11-23 | |||
| CN113722171A | 2021-11-30 | |||
| CN113742260A | 2021-12-03 | |||
| US7302623B2 | 2007-11-27 |
Attorney, Agent or Firm:
NANJING XINZHONGHE PATENT AGENCY (GENERAL PARTNERSHIP) (CN)
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