Title:
TERNARY DIGIT LOGIC CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/010637
Kind Code:
A1
Abstract:
A ternary digit logic circuit according to the present invention comprises: a pull-up device (100) and a pull-down device (200) connected in series between power source voltages (VDD and GND); and an input voltage (VIN) and an output voltage (VOUT). Both the pull-up device (100) and the pull-down device (200) operate as simple resistors, which are affected by only the output voltage (VOUT), and form a ternary digit ("1" state) through voltage distribution, when both of the devices have been turned off by the input voltage (VIN). When only one of the pull-up device (100) and the pull-down device (200) is turned on to allow the current to flow therethrough, VDD ("2" state) or GND ("0" state) is output as an output voltage (VOUT) to dramatically raise a bit density.
Inventors:
KIM KYUNG ROK (KR)
SHIN SUN HAE (KR)
JANG E SAN (KR)
JEONG JAE WON (KR)
SHIN SUN HAE (KR)
JANG E SAN (KR)
JEONG JAE WON (KR)
Application Number:
PCT/KR2015/014377
Publication Date:
January 19, 2017
Filing Date:
December 29, 2015
Export Citation:
Assignee:
UNIST(ULSAN NAT INST OF SCIENCE AND TECHNOLOGY) (KR)
International Classes:
H03K19/20; H03K19/0948
Foreign References:
| KR20010082557A | 2001-08-30 | |||
| US7567094B2 | 2009-07-28 | |||
| JP2006033060A | 2006-02-02 | |||
| KR20000077151A | 2000-12-26 | |||
| JP2008187384A | 2008-08-14 |
Attorney, Agent or Firm:
HAN, Sang Min et al. (KR)
Download PDF:
Previous Patent: COLOR-TREATED SUBSTRATE AND COLOR TREATMENT METHOD THEREFOR
Next Patent: HANOK TEACHING METHOD USING HANOK MODEL, AND HANOK MODEL
Next Patent: HANOK TEACHING METHOD USING HANOK MODEL, AND HANOK MODEL