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Patent Searching and Data


Title:
TERNARY MEMORY CELL AND MEMORY DEVICE COMPRISING SAME
Document Type and Number:
WIPO Patent Application WO/2020/204651
Kind Code:
A1
Abstract:
In a memory device comprising a ternary memory cell, the ternary memory cell may comprise: a first inverter and a second inverter which are cross-connected at a first node and a second node, and comprise a pull-up device and a pull-down device enabling a constant current to pass through during turn-off; a first read transistor and a first write transistor which are mutually connected in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are written and are mutually connected in parallel between the second node and a second bit line, wherein, as a response to an activated read word line, the first read transistor and the second read transistor may enable a read access current, equal to or smaller than the constant current, to pass through.

Inventors:
KIM KYUNG ROK (KR)
JEONG JAE WON (KR)
CHOI YOUNG EUN (KR)
Application Number:
PCT/KR2020/004558
Publication Date:
October 08, 2020
Filing Date:
April 03, 2020
Export Citation:
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Assignee:
ULSAN NAT INST SCIENCE & TECH UNIST (KR)
International Classes:
G11C11/419; G11C11/412
Foreign References:
JPH0765582A1995-03-10
JPH10172287A1998-06-26
KR100955251B12010-04-29
Other References:
CHO, GEUNHO ET AL.: "Design and process variation analysis of CNTFET-based ternary memory cells", THE VLSI JOURNAL INTEGRATION, vol. 54, June 2016 (2016-06-01), pages 97 - 108, XP029468772, DOI: 10.1016/j.vlsi.2016.02.003
SHIN, SUNHAE: "Ultra-Low Power Ternary CMOS Platform for Physical Synthesis of Multi-Valued Logic and Memory Applications", GRADUATE SCHOOL OF UNIST., 2017, XP055747001, Retrieved from the Internet [retrieved on 20200622]
Attorney, Agent or Firm:
Y.P.LEE, MOCK & PARTNERS (KR)
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