Title:
TEST CHIP AND TEST SYSTEM
Document Type and Number:
WIPO Patent Application WO/2014/133125
Kind Code:
A1
Abstract:
Provided are a test chip and a test system that improve precision for quantifying samples and reagents. The test chip (2) is provided with a supply section (112), a quantitation section (114), a first guide section (115), a second guide section (117), and a surplus section (116). A wall surface on the supply section (112) side in the first guide section (115) is a first wall surface (171). A wall surface on the first guide section (115) side in the supply section (112) is a second wall surface (172). A third end section (175) on the left side of the first wall surface (171), and a fourth end section (176) on the left side of the second wall surface (172) are linked by a third wall surface (173). A fourth wall surface (174) correspondingly provided to the third wall surface is positioned to the left of the third wall surface (173). The fourth wall surface (174) is positioned further to the left of the quantitation section (114) than a second end section (122). An imaginary vertical line (751) drawn in a direction perpendicular to the second wall surface (172) from the third end section (175) intersects the first guide section (115).
Inventors:
OSHIKA YUMIKO (JP)
YOSHIMURA CHISATO (JP)
YOSHIMURA CHISATO (JP)
Application Number:
PCT/JP2014/055041
Publication Date:
September 04, 2014
Filing Date:
February 28, 2014
Export Citation:
Assignee:
BROTHER IND LTD (JP)
International Classes:
G01N35/00; G01N37/00
Foreign References:
| JP2012078094A | 2012-04-19 | |||
| JP2012202736A | 2012-10-22 | |||
| JP2009139369A | 2009-06-25 | |||
| JP2009276143A | 2009-11-26 | |||
| JP2009121912A | 2009-06-04 | |||
| JP2009300433A | 2009-12-24 |
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