Title:
TEST DEVICE AND METHOD FOR ANALYZING REFIEF
Document Type and Number:
WIPO Patent Application WO/2011/007383
Kind Code:
A1
Abstract:
A test device for testing a memory under test, provided with an address fail memory that stores address fail data for indicating whether or not there is any defective cell at every address in the memory under test; a block fail memory that stores block fail data for indicating whether or not there is any defective cell at every block including a plurality of cells in the memory under test; a reading-out unit that reads out the address fail data from the address fail memory at every block in the memory under test; a row fail counter that counts, at every row address in a group having a part of a plurality of blocks in the memory under test, the default cell indicated in the address fail data read out from the reading-out unit; and a column fail counter that counts, at every column address in a group, the bad cell indicated in the address fail data read out from the reading-out unit.
Inventors:
FUJISAKI KENICHI (JP)
Application Number:
PCT/JP2009/003271
Publication Date:
January 20, 2011
Filing Date:
July 13, 2009
Export Citation:
Assignee:
ADVANTEST CORP (JP)
FUJISAKI KENICHI (JP)
FUJISAKI KENICHI (JP)
International Classes:
G11C29/56; G11C29/44
Domestic Patent References:
| WO2006001164A1 | 2006-01-05 |
Foreign References:
| JPH1092195A | 1998-04-10 | |||
| JP2000123595A | 2000-04-28 | |||
| JPH03269279A | 1991-11-29 | |||
| JPH06259993A | 1994-09-16 |
Attorney, Agent or Firm:
RYUKA IP LAW FIRM (JP)
Ryuka international patent business corporation (JP)
Ryuka international patent business corporation (JP)
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