TEST TRAY INSERT

Technical Field

[1] The present invention relates to a test tray insert and, more particularly, to a test tray insert arranged on a test tray of a test handler. Such a test tray insert is used for accommodating a semiconductor device therein so as to allow them to be brought into electrical contact with sockets arrayed on a test head provided with guide pins at a time of testing the semiconductor device. In particular, the present invention is directed to a test tray insert capable of allowing secure contact between the semiconductor devices and the sockets even though a thermal expansion or a thermal contraction occurs in a high-temperature or a low-temperature environment. Background Art

[2] In a typical manufacturing process for semiconductors, a test is conducted to investigate whether semiconductor devices fabricated through a predetermined assembling process can function to achieve their purposes. A test handler is used for the test.

[3] The test handler includes a loading unit, a chamber unit and an unloading unit. The chamber unit has a soak chamber, a test chamber and an unsoak chamber.

[4] While passing through the chamber unit, the semiconductor devices are arranged on a test tray in a matrix pattern by being loaded into test tray inserts (hereinafter, simply referred to as "inserts". The semiconductor devices loaded on a user tray of the loading unit are then transferred to the test tray. Thereafter, a thermal stress of heating or cooling is imposed on the semiconductor devices in the soak chamber. Then, in a test chamber, the semiconductor devices are brought into electrical contact with sockets arranged in a matrix pattern on a Hi-Fix board of a test head of anexternal test equipment, so that the test of the semiconductor devices is conducted. After the test is completed, the semiconductor devices on the test tray are returned to a room temperature in the unsoak chamber, so that the thermal stress is removed. Then, the semiconductor devices are sorted out into good/inferior goods by a sorting unit and then are unloaded onto the user tray by an unloading unit.

[5] Here, a rotator (a turn over module) for changing the posture of the test tray in a horizontal or a vertical direction is installed, for example, over each of the soak chamber and the unsoak chamber. By using the turn over module, the test tray is set horizontally in the loading and unloading unit, while it is kept vertically in the test chamber.

[6] Meanwhile, a plurality of inserts are installed on the test tray to secure the semi-

conductor devices at their right positions while preventing their separation from the test tray when the semiconductor devices are circulated in the test handler as described above. The semiconductor devices are loaded in the inserts and maintained therein. Most typically, the inserts are fixed on the test tray in a manner that they can accommodate the semiconductor devices in one-to-one correspondence. Since, however, a fastening structure such as a screw through hole should be installed at each insert to allow each insert to be fixed to the test tray, the size of the inserts increases, which results in a reduction of the total number of semiconductor devices that can be loaded on a test tray of a standardized size. As a consequence, test yield is reduced accordingly.

[7] As a solution to the above-mentioned drawback of the conventional inserts, there has been proposed a technique for installing every set of four inserts in a 2 x 2 matrix pattern on the test tray by using sub frames, wherein semiconductor devices are loaded in the inserts in one-to-one correspondence as well.

[8] Fig. 1 sets forth an exploded perspective view to show an insert 10, a sub frame 20 and a part of a test tray 30 in accordance with the prior art. In this drawing, four inserts 10 are grouped into a single unit of a 2 x 2 matrix pattern, and the set of the four inserts 10 is installed in a single sub frame 20. Then, sub frames 20 are fixed on the grid-patterned test tray 30 in a matrix structure.

[9] Further, the semiconductor devices are loaded in the openings of the inserts 10 in the one-to-one correspondence.

[10] Also, first and second guide holes 22 and 24 are provided at upper and lower peripheries of the sub frame 20, respectively. When testing is conducted, first and second guide pins, which are provided on a facing surface of a test head to be described later, are inserted into the first and the second guide hole 22 and 24, respectively.

[11] Referring to Fig. 2, there is shown a side cross sectional view to show a state before the test tray 30 is brought into contact with a test head 50 of the external testing equipment after the sub frame 20 including the above-described inserts is connected to the test tray 30. In this drawing, only two inserts 10 and 10' among the four mounted in the single frame 20 are shown, and semiconductor devices 72 and 72' are loaded in the inserts 10 and 10', respectively.

[12] Further, the sub frame 20 is fixed on the test tray 30, and sockets 82 and 82' and first and second guide pin 52 and 54 are installed on the facing surface of the test head 50 which faces the test tray 30.

[13] When conducting the test of the semiconductor devices, the test tray 30 is moved toward the test head 50 by a press unit (not shown) within the test handler while the test head 50 is stationary. The first and the second guide pin 52 and 54 are inserted into the first and the second guide hole 22 and 24 provided in the upper and the lower pe-

ripheries of the sub frame 20, so that the inserts 10 and 10' are guided to the right positions with respect to the sockets by the guide pins 52 and 54. As a result, the semiconductor devices 72 and 72' loaded in the inserts 10 and 10' are electrically brought into contact with the sockets 82 and 82' on the facing surface of the test head 50. Then, the semiconductor devices 72 and 72' are tested based on predetermined electric signals outputted from the sockets 82 and 82'.

[14] However, the above-mentioned structure also has some problems. Typically, the sub frame 20 and the inserts 10 and 10' would experience thermal expansion or contraction due to a thermal stress of a high or a low temperature, which is imposed to the soak chamber in order to inspect the thermal durability of the semiconductor devices 72 and 72'. Thus, the overall size of the sub frame 20 and the inserts 10 and 10' and the relative positions of the semiconductor devices in a vertical direction would be changed even though the first and the second guide hole 22 and 24 are fixedly inserted into the first and the second pin 52 and 54, so that the contact state of the semiconductor devices 72, 72' and the sockets 82, 82' will be changed as well. If the contact between the semiconductor devices 72, 72' and the sockets 82, 82' is poor, the reliability of the test will be degraded greatly.

[15] Besides, with regard to the above-described conventional mechanism for grouping the four inserts 10 into a single unit via the sub frame 20, the interval between two adjacent inserts 10 between two neighboring sub frames 20 of the test tray 30 is larger than the interval between two adjacent inserts 10 within the single sub frame 20.

[16] That is to say, when the inserts 10 and the sub frames 20 are fixed on the test tray

30 while allowing the semiconductor devices 72 loaded in the inserts 10 to be arranged in a matrix pattern, let's put an interval between the inserts 10 on the first and the second column to refer to as an odd pitch, while let's put an interval between the inserts in the second and the third column to refer to as an even pitch. Since a grid structure for fixing the sub frames 20 should be provided in the even pitch, the relationship of " pitch < even pitch (i.e., odd pitch being less than even pitch)" is established.

[17] Accordingly, the intervals between two neighboring inserts 10 on the single test tray

30 have two different values depending on their columnar location. Thus, the design of the test tray 30 and the Hi-Fix board becomes complicated, and, at the same time, there occurs a problem that the test tray 30 should be replaced depending on the type of the semiconductor device 72.

[18] Further, it would be understood by those skilled in the art that the above structure with the insert array of 2 x 2 matrix pattern, the sub frames 20 and the test tray 30 is i nferior in terms of durability, while its unit cost is high. Disclosure of Invention

Technical Problem

[19] It is, therefore, a primary object of the present invention to provide a test tray insert capable of minimizing the probability of a wrong contact between semiconductor devices and sockets due to a thermal expansion or contraction of the insert itself, wherein the test tray insert can be installed on a test tray without a sub frame.

[20] It is another object of the present invention to provide a test tray insert capable of maximizing the number of semiconductor devices to be loaded on a single test tray. Technical Solution

[21] In accordance with the present invention, there is provided a test tray insert arrayed with other ones on a test tray in a matrix pattern, the test tray insert for loading and maintaining semiconductor devices therein while allowing the semiconductor devices to be brought into contact with sockets on a test head electrically at a time of testing the semiconductor devices by using the test head having the sockets and a first guide pin, comprising: a first device accommodating portion for accommodating and maintaining a semiconductor device therein; a second device accommodating portion for accommodating and maintaining a semiconductor device therein; a middle portion between the first and the second device accommodating portion; a first end portion outside the first device accommodating portion; and a second end portion outside the second device accommodating portion, wherein the first end portion, the first device accommodating portion, the middle portion, the second device accommodating portion and the second end portion are provided in sequence in a lengthwise direction of the insert, and a first guide hole is provided at the middle portion to correspond to the first guide pin of the test head. Advantageous Effects

[22] As described above, the insert in accordance with the present invention is advantageous in that it allows an effective electrical contact between semiconductor devices and sockets on a test head in spite of a thermal expansion or a contraction at a high or a low temperature. Therefore, the reliability of the testing process for the semiconductor devices can be improved considerably.

[23] Furthermore, since no additional component such as a frame is required for the installation of the insert, the number of semiconductor devices capable of being loaded on a test tray of a standardized size can be increased. Besides, the structural durability of the test tray can also be improved and manufacturing costs can be reduced. Brief Description of the Drawings

[24] The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

[25] Fig. 1 is an exploded perspective view of a test tray, a frame and a test tray insert in accordance with the prior art;

[26] Fig. 2 sets forth a sectional side elevation view to show a state before the test tray and the test tray insert shown in Fig. 2 contact a test head of a test equipment;

[27] Fig. 3 depicts an exploded perspective view of a test tray insert and a test tray in accordance with the present invention;

[28] Fig. 4 provides a plan view of a test tray insert in accordance with the present invention;

[29] Fig. 5 offers a sectional side elevation view to illustrate a state before a test tray insert and a test tray in accordance with the present invention contact a test head of a test equipment;

[30] Fig. 6 shows a plan view to describe a coupling between a test tray insert in accordance with the present invention and a guide pin of a test head when the test tray insert thermally expands; and

[31] Fig. 7 is a plan view of a comparative example of a test tray inset in accordance with the present invention. Best Mode for Carrying Out the Invention

[32] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[33] Fig. 3 illustrates a perspective view of an insert 120 in accordance with the present invention, wherein a test tray 110 is also shown therewith. The test tray 110 is provided with a plurality of mounting holes 112 in a matrix pattern. In general, the test tray 110 is maintained horizontally at a time of loading/unloading semiconductor devices, whereas it is set either vertically or horizontally during the test time depending on the posture of a test head. Below, the insert 120 will be explained in detail for the case the test tray 110 is in a vertical position, for example. However, it is to be noted that the posture of the test tray 110 may be changed if necessary and, thus, it will be understood by those skilled in the art that the present invention is not limited to the insert to be installed on the test tray in a vertical state.

[34] In accordance with the present invention, inserts are secured in the mounting holes

112 such that they are arrayed in a matrix pattern. Each insert 120 has a first and a second device accommodating portion formed in a lengthwise direction thereof (or a vertical direction in case the test tray is in a vertical state). Each of the device accommodating portions 122 and 124 accommodates one semiconductor device therein. Thus, a set of two semiconductor devices can be loaded next to each other in each single insert 120. Accordingly, if the mounting holes 112 of the test tray 110 form N x M matrix (N and M are integer numbers), the inserts 120 also make N x M matrix on

the test tray 110, and semiconductor devices loaded in the inserts 120 form 2N x M matrix.

[35] Further, since the first and the second device accommodating portion 122 and 124 are formed in each insert 120 in the lengthwise direction thereof, a first end portion 120a at a lower periphery of the insert 120, a middle portion 120b between the first and the second device accommodating portion 122 and 124 and a second end portion 120c at an upper periphery of the insert 120 are defined. Also, a first guide hole 132 is formed at the middle portion 120b. That is, the first end portion 120a, the first device accommodating portion 122, the middle portion 120b, the second device accommodating portion 120b and the second end portion 120c are located in this order upwards from the bottom along the lengthwise direction of the insert 120. Preferably, they are integrally formed as one body. Further, it is preferred that the first guide hole 132 is a through hole.

[36] Moreover, a second guide hole 134 is formed at the middle portion 120b to face the first guide hole 132. It is preferred that the first and the second guide hole 132 and 134 are formed such that their centers lie at a same height in the lengthwise direction of the insert 120. Preferably, the second guide hole 134 is also a through hole, and one of the first and the second guide hole 132 and 134 is a circular hole while the other is a slit hole. For example, in the preferred embodiment of the present invention, the first guide hole 132 is a circular hole while the second guide hole 134 is a slit hole elongated in a row direction of the test tray (i.e., in a widthwise direction of the insert).

[37] Furthermore, a third and a fourth guide hole 136 and 138 can be formed at the first and the second end portion 120a and 120c, respectively. In such a case, it is preferred that the center of at least the third guide hole 136 lies on a same line as the center of the first guide hole 132 with respect to the lengthwise direction of the insert 120. Preferably, each of the third and the fourth guide hole 136 and 138 is a slit hole elongated in a direction perpendicular to a longer axis of the second guide hole 134 (i.e., in a lengthwise direction of the insert 120).

[38] Besides, two screw through holes 114 can be formed at two different inner edge portions of each mounting hole 112 of the test tray 110 in a manner that they are symmetrical to each other in a diagonal direction. The screw through holes 114 are for fixing the insert 120 loaded in the mounting hole 112. Further, two screw securing holes 140 can also be formed at the first and the second end portion 120a and 120b, respectively, in a diagonal direction to correspond to the screw through holes 114. Also, it is preferable that the size of the mounting hole 112 of the test tray 110 is larger than that of the insert 120 in order to accommodate the insert 120 with a clearance. Furthermore, though not shown in the figure, fixing and locking members for detachably securing semiconductor devices are provided in the first and the second

device accommodating portion 122 and 124.

[39] Below, the insert 120 in accordance with the present invention will be described in further detail in conjunction with Figs. 3 to 5.

[40] Fig. 4 is a plan view of the insert 120. Fig. 5 sets forth a sectional side elevation view to show: the test tray 110 on which a plurality of inserts 120 (only one of them is shown in this figure) are arranged in a matrix pattern; two semiconductor devices 170 and 172 loaded in the insert 120; and sockets 180 and 182 of a test head 150 which are to be brought into electrical contact with the semiconductor devices 170 and 172 respectively during a test thereof.

[41] Referring to Fig. 4, as described above, the first guide hole 132 of the insert 120 is a through hole similar to a perfect circle with a predetermined diameter, and the second guide hole 134 is a slit-shaped through hole formed by elongating a perfect circle of a predetermined diameter in a widthwise direction of the insert 129 by a preset length (i.e., a substantially elliptical shape formed by elongating a perfect circle of a predetermined diameter in a horizontal direction by a designated length when the insert 120 stands upright in the lengthwise direction thereof). In other words, the second guide hole 134 is a slit-shaped through hole whose longer axis is parallel to the widthwise direction of the inset 120. Besides, at least one of the third and the fourth guide hole 136 and 138 is a slit-shaped through hole formed by elongating a perfect circle of a preset diameter in the lengthwise direction of the insert 120 by a predetermined length (i.e., a substantially elliptical shape formed by elongating a perfect circle of a predetermined diameter in a vertical direction by a predetermined length when the insert 120 stands upright). In other words, at least one of the guide holes 136 and 138 is a slit-shaped through hole whose longer axis is parallel to the lengthwise direction of the insert 120. In particular, the third guide hole 136 preferably has a shape and a size obtained by elongating a perfect circle having the same diameter as that of the first guide hole 132 by a designated length, while the fourth guide hole 138 preferably has a shape and a size obtained by elongating a perfect circle having a diameter larger than that of the first guide hole 132 by a preset length.

[42] Further, it is preferred that the first guide hole 132 is located at the middle portion

120b between the first and the second device accommodating portion 122 and 124 such that its center lies closer to an upper end of the first device accommodating portion 124 than a lower end of the second device accommodating portion 124. In Fig. 6, a dashed line Ll indicates a middle position between the first and the second device accommodating portion 122 and 124.

[43] The above-described structure of the insert 120 has been designed to minimize the possibility of a wrong contact between the sockets 180 and 182 of the test head 150 and the semiconductor devices 170 and 172 shown in Fig. 5. Further detailed de-

scription of this structure and its effect will be provided later.

[44] As shown in Fig. 5, the insert 120 in accordance with the present invention is made to face the test head 150 while it is fixed on the mounting hole 112 of the test tray 110, and the first and the second device accommodating portion 122 and 124 accommodate therein semiconductor devices 170 and 172, respectively. Further, provided on the surface of the test head 150 which faces the insert 120 are: sockets 180 and 182 to be brought into electrical contact with the semiconductor devices 170 and 172, respectively; and first to fourth guide pins 162, 164, 166 and 168 to be inserted into the first to the fourth guide holes 132, 134, 136 and 138, respectively.

[45] To be more specific, a Hi-Fix board (not shown) is attached on the facing surface of the test head 150, and a socket guide (not shown) is installed on the Hi-Fix board. Though the first to the fourth guide pin 162 to 168 are installed on the socket guide, the illustration of the socket guide is omitted for the simplicity of explanation, and only the guide pins 162 to 168 and the test head 150 are shown in the figure.

[46] When testing the semiconductor devices, the first to the fourth guide pins 162 to

168 are inserted into the first to the fourth guide holes 132 to 138 as the test tray 110 is made to approach the test head 150 by a press unit (not shown), so that the insert 120 is guided to its right position with respect to the sockets, and the sockets 180 and 182 come into electrical contact with the semiconductor devices 170 and 172, respectively, in one-to-one correspondence. Accordingly, the electrical characteristics of the semico nductor devices 170 and 172 can be tested by using electrical signals outputted from the sockets 180 and 182.

[47] In this connection, the test of the semiconductor devices 170 and 172 using the insert 120 in accordance with the present invention includes a performance test at a high or a low temperature. Accordingly, the test tray 110, the insert 120 and the semiconductor devices 170 and 172 are made to contact the test head 150 in heated or cooled state.

[48] As a result, thermal expansion or contraction of the insert 120 might be caused because of a change in temperature. Nevertheless, in accordance with the present invention, even when the insert 120 thermally expands, reliable contact between the semiconductor devices 170 and 172 and the sockets 180 and 182 is still possible due to an inventive coupling mechanism between the insert 120 and the first to the fourth guide pin 162 to 168. Such a coupling mechanism is illustrated in Fig. 6, which will be described hereinafter with reference to Figs. 3 to 5 as well.

[49] First of all, when approaching the test tray 110 to the test head 150, the portions serving as reference points for determining the relative positions of the semiconductor devices 170 and 172 and the sockets 180 and 182 are: the first guide hole 132 provided between the first and the second device accommodating portion 122 and 124; and the

first guide pin 162 of the test head 150 to be inserted into the first guide hole 132.

[50] Here, since the first guide hole 132 serving as a reference point for the contact is located between the first and the second guide accommodating portion 122 and 124, the thermal expansion from the first guide hole 132 to the first semiconductor device 170 in the first device accommodating portion 122 and the thermal expansion from the second guide hole 132 to the second semiconductor device 172 in the second device accommodating portion become relatively uniform with respect to the first guide hole 132, though the thermal expansion of the insert 120 occurs over the entire length and width of the insert 120 due to a high temperature. Accordingly,difference ofa contact discrepancy is greatly reduced between the first and the second semiconductor devices 170 and 172 and the first and the second socket 180 and 182.

[51] More specifically, referring to Fig. 5, assume that the interval between the first guide hole 132 serving as the reference point and a lower end of the first semiconductor device 70 is A, and the interval between the first guide hole 132 and the lower end of the second semiconductor device 172 is B. Since A and B are defined with respect to the first guide hole 132 located therebetween, a difference in variations (i.e., variations of A and B) in the positions of the first semiconductor device 170 and the second semiconductor device 172 due to the thermal expansion becomes comparatively small. As a result, a discrepancy in the variations of the positions of the whole semiconductor devices can be reduced.

[52] In other words, referring to Fig. 6, when the insert 120 thermally expands, the interval A between the first guide hole 132 and the lower end of the first semiconductor device 170 becomes A', while the interval B between the first guide hole 132 and the lower end of the second semiconductor device 172 becomes B'. Since, however, A and B are dispersed with separate values owing to the first guide hole 132 between the first and the second device accommodating portion 122 and 124, the possibility of the wrong contact between the first and the second semiconductor device 170 and 172 and the first and the second socket 180 and 182 is greatly reduced.

[53] To facilitate understanding of the insert 120 in accordance with the present invention, Fig. 7 illustrates a comparative example in which an insert 120 which differs from the present invention is provided. Here, parts having functions identical to those described above will be assigned same reference numerals.

[54] As for the insert 120 in Fig. 7, a first guide hole 132 of a middle portion 120b is omitted. Instead, the insert 120 has a fifth and a sixth guide hole 192 and 194 at its first and second end portion 120a and 120c, respectively. In this case, a test head 150 is configured to have a fifth and a sixth guide pin (not shown) to be inserted into the fifth and the sixth guide hole 192 and 194.

[55] Assume that the fifth guide hole 192 at the first end portion 120a serves as a

reference when the insert 120 with semiconductor devices loaded therein is fixed to the test head to contact the test head electrically. Then, the interval between the fifth guide hole 192 and a lower end of the semiconductor device loaded in a first device accommodating portion 122 is set as C, while the interval between the fifth guide hole 192 to a lower end of the semiconductor device loaded in a second device accommodating portion 124 is set as D. If the insert 120 thermally expands, there is established relationships that C = C + α (α>0) and D' = D + β (β>0).

[56] Here, D includes C, and D' includes C. Therefore, the amount β of thermal expansion of D includes the amount α of thermal expansion of C plus the amount of thermal expansion amount of the section D-C. As a result, there is established a relationship of α (\ β. In other words, C and D increases to C and D', respectively, due to the thermal expansion of the insert 120'. Since D' includes the thermal expansion amount of the section D-C as well as the thermal expansion amount α of C, D' exhibits a greater variation than C

[57] As a result, with respect to the fifth guide hole 192 at the first end portion 120a, there occurs a discrepancy between the semiconductor devices and sockets. Particularly, though the discrepancy between the semiconductor device in the first device accommodating portion 122 and its corresponding socket might be overcome by providing a clearance in a design stage, the discrepancy between the semiconductor device in the second device accommodating portion 124 and its corresponding socket is too great to be resolved.

[58] Referring back to Figs. 5 and 6, as for the insert 120 in accordance with the present invention, since the first guide hole 132 serving as the reference point is located between the first and the second device accommodating portion 122 and 124, the respective intervals A and B from the first guide hole 132 to the first and the second semiconductor device 170 and 172 have two separate values that are not relevant to each other at all. Accordingly, the influence of the thermal expansion upon the position of the semiconductor devices can be distributed uniformly, so that the discrepancy in position variations of the first and the second semiconductor devices can be reduced considerably.

[59] In this regard, in order to minimize the discrepancy in the position variations of the semiconductor devices 170 and 172, it is preferable to locate the first guide hole 132 as close to the first device accommodating portion 122 as possible such that the difference between A and B gets as small as possible.

[60] Further, the second guide hole 134 is configured to be of a slit shape elongated in the widthwise direction of the insert 120 in order to provide a clearance in left- and-right direction when the insert 120 thermally expands, thus allowing the second guide pin 164 to be stably guided to the second guide hole 164. Such configuration of

the second guide hole 134 prevents the insert 120 from being bent because of its thermal expansion. Moreover, since the second guide hole 134 is located on a substantially same height as the first guide hole 132, a distortion of the insert 120 can also be avoided.

[61] Likewise, at least one of the third and the fourth guide hole 136 and 138 (especially, the third guide hole 136) is configured to have a slit shape elongated in the lengthwise direction of the insert 120 in order to provide a clearance in a vertical direction, thus allowing the third and the fourth guide pin 166 and 168 to be guided thereto stably. By this configuration, the insert 120 can be prevented from being bent. Further, by locating the third guide hole 136 on a substantially same line as the first guide hole 132, a distortion of the insert 120 can be avoided.

[62] Meanwhile, though the above preferred embodiment of the present invention has been described for the case where a thermal expansion occurs at a high temperature, it can also be applied to a case of a thermal contraction at a low temperature.

[63] While the invention has been shown and described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.